KR19990061575A - Command Length Reduction Method of Central Processing Unit and Its Device - Google Patents

Abstract

The present invention provides a method and apparatus for reducing the length of an instruction in a central processing unit that can efficiently maintain the performance of the central processing unit by reducing the length of the instructions. To this end, the instruction length reduction method of the present invention is directed to an instruction processing method of a central processing unit for fetching an N-bit instruction stored in an external storage means in units of M bits and executing the instruction; Storing a plurality of N-bit instructions inside the central processing unit; An input step of program inputting instructions by a programmer; A reading step of reading out the instructions stored therein using K (N / K) bit compression instructions fetched from the external storage means according to the program; And a decoding step of decoding the instructions read in the reading step into an executable command code. In addition, the instruction length reduction apparatus of the present invention comprises: a central processing unit for fetching N-bit instructions stored in an external storage means in units of M bits and executing the instructions; A plurality of N-bit instructions used when executing the central processing unit therein, and instructions executable by reading the internally stored instructions using (N / K) bit compression instructions fetched from the external storage means And reduction means for decoding and outputting the code.

Description

Method and apparatus for reducing instruction ging of central processing unit

The present invention relates to a central processing unit, and more particularly, to an instruction length reduction method and apparatus for reducing the length of an instruction in the central processing unit.

In general, in a 32-bit central processing unit, when the instruction length is 32 bits, the width of the data bus is 32 bits. In this case, when using a 32-bit central processing unit in an 8-bit or 16-bit system, the external memory access cycle must be executed four or two times to fetch one 32-bit instruction. .

As a result, frequent instruction fetch cycles, compared to 32-bit external memory widths, ultimately degrade the performance of the central processing unit. This is because the central processing unit pauses during instruction fetch.

To solve this problem, the following two methods are used. That is, the first case is that the central processing unit takes only 16 bits of instruction length as much as possible even though it can process 32 bits instructions. This is the case of Hitachi, Japan's SH series central processing unit. This is a 32-bit instruction because it violates the general principle that the function definition of the central processing unit can be made stronger when the instruction length is long. Performance may be degraded compared to 32-bit CPUs with

The second defines a 16-bit instruction on the assumption that the structure of the 32-bit central processing unit is not used in full, and the 16-bit instruction enters the central processing unit and is converted into a 32-bit instruction to execute the instruction. That's the way.

Here, a 32-bit central processing unit is not used as a pool. For example, in a 32-bit instruction, the number of internal registers that can be designated by one instruction is three, whereas the constraint or immediate field that only two are used is available. It is a method of constructing 16-bit instructions under the assumption that the (immediate value field) is limited to 12 bits to 8 bits. An example of such a scheme is an ARM central processor unit, which is illustrated in FIG. 1.

That is, the bonus central processing unit includes a register 22, a first multiplexer 24, a bonus instruction extender 26, a second multiplexer 28, a third multiplexer 32, and an instruction decoder 34. It is configured by.

The 32-bit register 22 receives a command from the external memory map 10 via a data bus D-BUS. The external memory map 10 is composed of at least one ROM 10A and at least one RAM 10B, and instructions of a central processing unit are stored in the ROM 10A. The memory widths of the ROM 10A and the RAM 10B can be composed of 8 bits, 16 bits, or 32 bits.

The first multiplexer 24 toggles and outputs the lower 16 bits and the upper 16 bits of the 32-bit register 22 by a selection control signal. In the bonus type central processing unit, a 32-bit normal instruction code (ARM code) and a 16-bit bonus instruction can be used interchangeably.

The control signal (BX) shown in the figure is a programmer's specific program for toggling between an ARM routine that handles 32-bit instructions in normal mode (ARM mode) and a dumb routine that handles 16-bit compressed instructions in dumb mode. It occurs at the core of the central processing unit when a program BX, which is an instruction, is executed. At the time of execution of an ARM instruction, for example, the logic level is 0, and when the bonus instruction is executed, for example, logic 1 level.

Accordingly, the first multiplexer 24 is disabled by the control signal BX of logic level 0 in the normal mode (ARM mode), while the control signal of logic level 1 in the dumb mode. (BX) is enabled, and the upper and lower 16 bits of the 32-bit register 22 are toggled and output according to a selection control signal (not shown).

The bonus instruction expander 26 expands a 16-bit bonus instruction input via the first multiplexer 24 into a 32-bit ARM instruction in the bonus mode. For example, (ADd Rd, #Constant) The dumb instruction as an operation instruction of is shown in Fig. 5 (a), and an example of converting the dumb instruction into an ARM instruction is shown in Fig. 5 (d).

That is, the lower 8 bits of the bonus instruction shown in FIG. 5 (a) are immediate values, 2 bits of Rd represent a source (or destination) register, and 10 of bits 10 and 11 represent an ADD instruction. A minor operation code is shown, and one of the upper three bits is a major operation code indicating the format of the ADD instruction with the measured value. This bonus instruction is expanded to a 32-bit ARM instruction as shown in FIG. 5B when the bonus instruction extender 26 passes. Here, in the 32-bit code converted to the ARM instruction, 1110, the upper four bits, is always a fixed status code.

The second and third multiplexers 28 and 32 select and output 32-bit instructions from the register 22 and 32-bit decompression instructions from the dumb instruction extender 26 according to the control signal S.

The control signal S is a control signal generated according to an instruction status code assigned to a specific code among the instruction codes, that is, whether the currently input instruction is an instruction that extends a dumb instruction or an ARM instruction. In the case of the decompression instruction, the logic level is, for example, the logic level. For ARM instructions, the logic level is, for example, the logic level. Accordingly, the second and third multiplexers 28 and 32 select the output of the dumb instruction extender 26 when the control signal S is at logic 1 level, while the registers when the control signal S is at logic 0 level. Select the 32-bit ARM instruction from (22).

Here, as an example of the ARM instruction, a data processing instruction is illustrated in FIG. 4. As shown in FIG. 4 (a), the upper 4 bits are the status field of the instruction, the 25th bit represents an immediate operand, and the 20th bit (s) is a setting status code of 0 for an ARM instruction. Set to 1 for the bonus command. Rn and Rd of 4 bits indicate a first operand register and a destination register, respectively, and Operrand 2 of 12 bits indicates a second operand. The Operand 2 is composed of the lower 4 bits for representing the second operand register and the upper 8 bits, which are shift bits applied to the second operand, or the lower 8 bits for representing the immediate value, and the shift bit applied to the immediate value. Consists of the upper 4 bits. In the lower part of FIG. 4A, the instructions are divided when they are stored in an 8-bit wide memory, a 16-bit wide memory, and a 32-bit wide memory, respectively. In addition, Fig. 4 (b) shows a state in which a bonus instruction for "ADD R1 ← R2, R3" is expanded by the bonus instruction extender 26 as an example of an operation instruction, and bit 20 is set to 1. .

The instruction decoder 34 decodes and outputs an instruction input through the third multiplexer 32 into an executable code using a codebook consisting of a look-up table.

An instruction processing operation of the conventional bonus type central processing unit configured as described above will be described with reference to FIGS. 2 to 5. Here, it is assumed that the instruction flow as shown in Fig. 2 is input as the instruction flow programmed by the programmer.

First, when the command word flow is input, the corresponding instruction data stored in the ROM 10A of the external memory map 10 is read and sequentially fetched into the register 22. In the case where the width of the ROM 10A is 8 bits, the instruction data is stored as shown in FIG. 3 (a). In this case, 4 cycles are required to fetch 32-bit ARM instructions 1 (A_INT 1). Corresponding instruction data (A_INT 1-1, A_INT 1-2, A_INT 1-3, A_INT 1-4) can be fetched into the register 22 by the fetch operation of the 16-bit bonus instruction 5 (T_INT). In order to fetch 1), corresponding instruction data (T_INT 1-1, T_INT 1-2) can be fetched into the register 22 by a 2-cycle fetch operation.

When the width of the ROM 10A is 16 bits, the instruction data is stored as shown in FIG. 3 (b). In this case, in order to fetch 32-bit ARM instructions (A_INT 1), two cycles of fetching are performed. By the operation, the corresponding instruction data (A_INT 1-1, A_INT 1-2) can be fetched into the register 22, while in order to fetch a 16-bit dumb instruction 5 (T_INT 1), one cycle of fetch operation is performed. Corresponding instruction data T_INT 1 can be fetched into the register 22 by this.

In addition, when the width of the ROM 10A is 32 bits, the instruction data is stored as shown in Fig. 3 (c). In this case, in order to fetch 32 bits of ARM instruction 1 (A_INT 1), one cycle is used. The corresponding instruction data A_INT 1 can be fetched into the register 22 by the fetch operation. On the other hand, in order to fetch the 16-bit dumb instruction 5 (T_INT 1), the corresponding instruction data (1_Fetch operation) is fetched. T_INT 1) can be fetched into the register 22.

Thereafter, the BX instruction BX1 defines that subsequent instructions are normal mode (ARM mode) instructions, so that instructions 1 to 4 (A_INT 1 to A_INT 4) of the ARM routine 1 are assigned to the register 22 and the second. In addition to being output through the multiplexer 28, it is also input to the command decoder 34 through the third multiplexer 32 and decoded.

Subsequently, since the subsequent instructions are defined by the BX instruction BX2 as a dumb mode instruction, the 16-bit instructions 5 through 7 (T_INT 1 through T_INT 3) in the bonus routine 1 are assigned to the register 22 and the first multiplexer. (24) and the extra command expander 26 is expanded to 32-bit instructions, and then output through the second multiplexer 28, and is also input to the instruction decoder 34 via the third multiplexer 32, Decoded.

Next, the ARM routine 2 and the dumb routine 2 also perform the instruction processing operation by repeating the same operations as the above-described ARM routine 1 and the dumb routine 1.

The bonus central processing unit described above is similar to that of Hitachi, Japan's SH series central processing unit, but the SH series has a limited structure because it can drive hardware with a 32-bit structure internally. It may be somewhat better in performance than the central processing unit.

However, even in the above-described dumb central processing unit, since the dumb instruction is defined as 16 bits, a system having an 8-bit or 16-bit bus width still has a problem of insufficient performance of 32-bit data processing. In particular, this problem is remarkable when applied to a system having an 8-bit bus width, because two cycles of fetch operation must be performed to fetch a 16-bit dumb instruction.

Accordingly, the present invention has been made to solve the above problems, and provides a method and apparatus for reducing a command length of a central processing unit that can efficiently maintain the performance of the central processing unit by reducing the length of instructions used in the central processing unit. The purpose is to.

Another object of the present invention is to store instructions of a central processing unit which are frequently used in a chip of the central processing unit, and to reduce the length of the instructions by using their pointers as instructions. The purpose is to provide the device.

The instruction length reduction method of the central processing unit according to the present invention for achieving the above object is to the instruction processing method of the central processing unit for fetching the N-bit instruction stored in the external storage means in units of M bits and executing the instruction. In; Storing a plurality of N-bit instructions inside the central processing unit; An input step of program inputting instructions by a programmer; A reading step of reading the internally stored instructions using K (N / K) bit compression instructions fetched from the external storage means according to the program; And a decoding step of decoding the instructions read in the reading step into an executable command code.

Here, the reading step includes a storing step of temporarily storing the fetched N-bit instructions, wherein the stored K (N / K) bit compression instructions are stored as the address signals corresponding to each stored in the storing step. N-bit instructions are read sequentially.

In addition, the instruction length reduction method of the central processing unit according to another aspect of the present invention for achieving the above object, the central processing unit for fetching the N-bit instruction stored in the external storage means in units of M bits, and executes the instruction. In the instruction processing method of; A first storage step of storing a plurality of N-bit instructions and compressed (N / K) bit compression instructions for a plurality of N-bit instructions frequently used in the central processing unit in the external storage means; A second storing step of storing the frequently used plurality of N-bit instructions in a central processing unit; An input step of program inputting instructions by a programmer; Determining whether N-bit instructions inputted from the external storage means are normal instructions or compressed instructions according to the instruction sequence of the instruction program; A first decoding step of decoding the input N-bit instructions into an executable command code in the case of the normal instruction; Reading the corresponding N-bit instructions stored therein by using the compression instructions when the N-bit instructions are K compressed instructions; And a second decoding step of decoding the read N-bit instructions into executable command codes.

Herein, the present invention includes a storing step of temporarily storing the fetched N-bit instructions, and one of the first decoding step and the reading step of the N-bit instructions stored in the storing step according to the determination result of the determining step. It further comprises a forwarding step of transmitting to the reading step, the reading step using the K (N / K) bit compression instructions delivered in the delivery step as an address signal sequentially the K N-bit instructions stored at the corresponding addresses Read out.

In addition, the instruction length reduction apparatus of the central processing unit according to the present invention for achieving the above object comprises a central processing unit for fetching the N-bit instructions stored in the external storage means in units of M bits to execute the instructions; A plurality of N-bit instructions used when executing the central processing unit therein, and instructions executable by reading the instructions stored therein using (N / K) bit compression instructions fetched from the external storage means And instruction reduction means for decoding and outputting the code.

Here, the instruction reducing means may include: storing means for temporarily storing the fetched N-bit instruction; Internal storage means for storing the N-bit instructions corresponding to the compression instruction, receiving K-compression instructions stored in the storage means as address signals, and sequentially reading corresponding N-bit instructions; And instruction decoding means for sequentially decoding the N-bit instructions read from the internal storage means.

In addition, the instruction length reduction apparatus of the central processing unit according to another aspect of the present invention for achieving the above object, to the central processing unit for fetching the N-bit instructions stored in the external storage means in units of M bits to execute the instructions. In; The external storage means stores a plurality of N-bit instructions and (N / K) bit compression instructions in compressed form for a plurality of N-bit instructions frequently used in the central processing unit; The frequently used N-bit instructions are stored therein, and when the N-bit instructions inputted from the external storage means are normal instructions instead of compressed instructions according to the instruction sequence, the N-bit instructions are directly decoded and executed as executable command codes. In the case where the input N-bit instruction is K compression instructions, the apparatus further includes an instruction reduction means for reading out corresponding N-bit instructions stored therein using the compression instructions, and then decoding and outputting them into executable instruction codes. .

Here, the instruction reducing means may include: storing means for temporarily storing the fetched N-bit instruction; Demultiplexing means for switching and outputting an N-bit command stored in the storing means to any one of a first output terminal and a second output terminal according to a control signal; Internally storing the frequently used N-bit instructions, and sequentially reading K N-bit instructions stored at the corresponding addresses by using K compression instructions applied through the first output terminal of the multiplexing means as address signals. Storage means; Multiplexing means for selectively outputting any one of a second output terminal of the multiplexing means and a read command of the internal storage means according to a control signal; And instruction decoding means for decoding the output N-bit instruction of the multiplexing means.

1 is a circuit block diagram showing an example of an instruction length reduction apparatus of a conventional central processing unit;

2 is a view for explaining an instruction processing flow in the instruction length reduction apparatus shown in FIG.

3 is a view for explaining an instruction storing state according to a memory width of an external memory map shown in FIG. 1;

4 is a view for explaining an example of a 32-bit instruction used in the central processing unit shown in FIG.

5 is a view for explaining the operation of the bonus command extender shown in FIG.

6 is a schematic circuit block diagram of an instruction length reduction apparatus of a central processing unit according to the present invention;

7 is a circuit block diagram for explaining the main part of FIG. 6 in detail;

FIG. 8 is a view illustrating a command processing flow for explaining a command length reduction method that may be employed in the command length reduction apparatus of the central processing unit shown in FIG. 6;

FIG. 9 is a view for explaining an instruction storage state and an instruction storage state of the internal memory according to the memory width of the external memory map shown in FIG.

* Explanation of symbols for main parts of the drawings

100: external memory map 100A: ROM

100B: RAM 200: Central Processing Unit

220: register 240: demultiplexer

260: internal memory 280: multiplexer

300: command decoder

Hereinafter, a method and apparatus for reducing the command length of a central processing unit according to the present invention will be described in detail with reference to the accompanying drawings.

6 is a schematic circuit block diagram of an instruction length reduction apparatus of a central processing unit according to an embodiment of the present invention.

As shown in the figure, the instruction reduction apparatus of the central processing unit according to an embodiment of the present invention, the register 220, the demultiplexer 240, the internal memory 260, the multiplexer 280 and the instruction decoder 300 It is configured to include).

The 32-bit register 220 receives a command from the external memory map 100 via a data bus D-BUS. The external memory map 100 includes at least one ROM 100A, which is a nonvolatile semiconductor memory, and at least one RAM 100B, which is a volatile semiconductor memory, and instructions of a central processing unit are stored in the ROM 100A. It is. These ROMs 100A can be configured as ROMs having 8-bit, 16-bit, or 32-bit memory widths as shown in Figs. 9A, 9B, and 9C.

Here, in the present invention, the normal mode using the N-bit (for example, 32-bit in the present embodiment), and the N-bit (for example, 32-bit) instructions a predetermined multiple (for example, In the embodiment, there is a compression mode using an instruction of N / 4 bits (for example, 8 bits in the present embodiment) compressed to 1/4 times.

Accordingly, as shown in FIG. 9A, n 32-bit instructions used in the normal mode are divided into four in the 8-bit wide ROM 100A. For example, one 32-bit instruction is divided into NR_INT 1-1, It is separately stored as NR_INT 1-2, NR_INT 1-3, NR_INT 1-4. Then, n 8-bit compression instructions used in the compression mode are respectively COM_INT 1, COM_INT 2,... Followed by COM_INT n.

As shown in Fig. 9B, n 32-bit instructions used in the normal mode are divided into two in the 16-bit wide ROM 100A. For example, one 32-bit instruction is divided into NR_INT 1-1, NR_INT 1-2 is stored separately. Then, n 8-bit compression instructions used in the compression mode are, for example, two COM_INT 1 and COM_INT 2; COM_INT 3, COM_INT 4,... ; It is stored in the order of COM_INT n-1, COM_INT n.

As shown in Fig. 9C, the 32-bit wide ROM 100A includes n 32-bit instructions used in the normal mode, for example, NR_INT 1, NR_INT 2,... NR_INT n is stored in order. And n 8-bit compressed instructions used in the compression mode, for example, COM_INT 1, COM_INT 2, COM_INT 3, COM_INT 4; ; It is stored in the order of COM_INT n-3, COM_INT n-2, COM_INT n-1, and COM_INT n.

The demultiplexer 240 outputs a 32-bit command stored in the 32-bit register 22 to any one of two output terminals according to a control signal mode. Here, the control signal Mode becomes complementary to, for example, a logic zero level in the normal mode and a logic one level in the compression mode in accordance with the normal mode and the compression mode. Accordingly, the demultiplexer 240 switches to the multiplexer 280 to be described later in the normal mode, and switches to the internal memory 260 to be described later in the compressed mode.

The internal memory 260 is a storage means having a memory width of N bits (for example, 32 bits in the present embodiment) installed inside a chip of the central processing unit, and the storage means includes N / 4 bits in a compression mode. Stores 32-bit instructions that are frequently used to correspond to (eg, 8-bit) instructions. The storage means may include, for example, a nonvolatile semiconductor memory such as a ROM, an EPROM, an EEPROM, a flash memory, and a volatile semiconductor memory such as a RAM. When the storage means is configured as a nonvolatile memory, the 32-bit instructions frequently used during manufacturing are embedded to be used.In the case of the nonvolatile memory, the original instructions are stored in an external system memory. It can also be loaded and used at system boot time.

The internal memory 260 stores and uses 256 32-bit instructions that are frequently used, as shown in FIG. Here, the 8-bit instruction in the compression mode is a storage address of the corresponding 32-bit instruction stored in the internal memory 260.

In this case, if the instruction in the compressed mode is an address, for example, if 256 instructions are used frequently, four instructions are defined at once in the 32-bit field, and if the instruction defines 16 instructions, eight instructions at the same time. Since it can be defined, it is possible to improve the code density of about 2 times or 4 times than that of the central processing unit and the bonus type central processing unit of the SH series described in the conventional example. In addition, the frequency of instruction fetches is similarly reduced, further improving performance significantly in terms of effectively exploiting the advantages of the 32-bit central processing unit architecture.

The multiplexer 280 selects and outputs one of a 32-bit command output from the demultiplexer 240 and a 32-bit command read from the internal memory 260 according to a control signal (Mode). Here, the control signal Mode becomes complementary to, for example, a logic zero level in the normal mode and a logic one level in the compression mode in accordance with the normal mode and the compression mode. Accordingly, the multiplexer 260 selectively outputs 32-bit instructions from the demultiplexer 240 in the normal mode, and selectively outputs 32-bit instructions from the internal memory 260 in the compression mode.

The instruction decoder 300 decodes a 32-bit instruction input through the multiplexer 280 into a code in an executable state using a codebook consisting of a look-up table.

Hereinafter, a command length reduction apparatus and a method of a central processing unit according to the present invention configured as described above will be described in detail with reference to FIGS. 7 to 9.

FIG. 7 is a circuit block diagram illustrating the main part of FIG. 6 in detail. FIG. 8 is a flowchart illustrating an instruction length reduction method that may be employed in the instruction length reduction apparatus of the central processing unit of FIG. 6. FIG. 9 is a diagram for explaining an instruction storage state and an instruction storage state of the internal memory according to the memory width of the external memory map shown in FIG. 6.

In this example, 256 cases of frequently used commands are explained as an example. The 256 instructions are already stored in the internal memory 260 as storage means in the central processing unit.

First, in the normal mode (when the control signal Mode is, for example, logic 0), when a 32-bit instruction is fetched from the ROM 100A of the external memory map 100 into the register 220, the register 220 ) Is directly applied to the multiplexer 280 via the demultiplexer 240 and then entered by the multiplexer 280 and then input to the input of the command decoder 300. As a result, execution of instructions of a normal 32-bit central processing unit occurs.

Next, in the compression mode (when the control signal Mode is, for example, logic 1), when a 32-bit instruction is fetched into the register 220 from the ROM 100A of the external memory map 100, the register ( The instructions stored at 220 are applied to the internal memory 260 through the demultiplexer 240. In this case, since the 32-bit command is an address of the internal memory 260 which is four 8-bit compression commands, they are divided into 8-bit units and applied as the address of the internal memory 260 as shown in FIG. 7. Accordingly, 32-bit instructions stored at the addresses accessed by the four compression instructions are read out and sequentially input to the multiplexer 280. Thereafter, the multiplexer 280 selects a 32-bit command applied from the memory 260 and outputs the 32-bit command to the command decoder. As a result, execution of instructions of a normal 32-bit central processing unit occurs.

Therefore, in the above compression mode, four compression commands can be executed at once with 32 fields.

On the other hand, in order to smoothly execute the central processing unit, the assembler needs to distinguish between the instructions of the normal mode and the instructions of the compression mode.

Therefore, as shown in FIG. 8, the normal mode instructions (instruction 1 (NR_INT 1), instruction 2 (NR_INT 2), command 3 (NR_INT 3), instruction 4 (NR_INT 4) at the time of programming by the programmer). By inserting the normal mode command NR 1 at the start position of, it is possible to enter a sequence of normal mode commands (ie, the normal mode routine 1). Here, the syntax of the normal mode instruction NR 1 corresponds to a 32-bit instruction that enables the normal mode to be changed by the actual assembler. Executing this command converts the state of the central processing unit into a state capable of executing the normal mode command.

In addition, the compression mode command (COM_INT 1), the compression command 2 (COM_INT 2), the compression command 3 (COM-INT 3), the compression command 4 (COM_INT 4) at the beginning of the compression mode commands (COM_INT 4) By inserting 1) it is possible to enter a sequence of compressed mode commands (ie, compressed mode routine 1) afterwards. Here, the syntax of the compressed mode command (COMP 1) corresponds to a 32-bit command that allows the actual assembler to change from the normal mode to the compressed mode. After executing this command, the state of the central processing unit is converted into a state capable of executing the compressed mode command.

Next, the normal mode command NR 2 and the normal mode routine 2 and the compression mode command COM 2 and the compression mode routine 2 thus performed are performed as described above.

Here, the N instructions executed in the compression mode are preferably multiples of four times for simplicity of hardware in relation to the alignment of data fields.

On the other hand, the present invention is not limited to the above specific embodiments, but can be modified and modified in various ways without departing from the gist of the present invention.

For example, in the above specific embodiment, the instruction length of the central processing unit has been described as being limited to 32 bits, but the present invention can be applied to other cases in which the instruction length is 16 bits, 64 bits, or the like. Those of ordinary skill in the art will readily understand.

In addition, in the above-described specific embodiment, the length of the compression instruction is limited to 8 bits, but this may vary depending on the length of the instruction used by the central processing unit, and also depending on how many instructions are used. Of course, it can be varied.

In addition, in the above specific embodiment, the length of a predetermined number of instructions frequently used in the central processing unit has been described. However, the present invention may reduce the length of all instructions used in the central processing unit if necessary. .

As described above, according to an embodiment of the present invention, the code density is remarkably defined by storing frequently used instructions in the internal memory of the central processing unit and defining pointers (that is, addresses) to select the stored instructions as instructions. It can be improved.

That is, for example, four instructions can be defined at one time as a 32-bit field, and eight instructions can be defined at one time as a 32-bit field when 16 instructions are defined. The code density can be improved by two or four times as compared to the processing unit and the bonus central processing unit.

In addition, according to the present invention, since the instruction fetch frequency can be similarly reduced in addition to the above code density improvement, the performance can be considerably improved in terms of effectively utilizing the advantages of the central processing unit structure.

In addition, according to the present invention, superior performance can be achieved with a very simple configuration compared to the ARM type central processing unit.

Claims (24)

In the central processing unit for fetching the N-bit instruction stored in the external storage means in M-bit unit and executing the instruction, A plurality of N-bit instructions used when executing the central processing unit therein, and instructions executable by reading the instructions stored therein using (N / K) bit compression instructions fetched from the external storage means Instruction reduction apparatus of the central processing unit, characterized in that it comprises a command reduction means for decoding and outputting the code. 2. The apparatus of claim 1, wherein the instruction reducing means comprises: storing means for temporarily storing the fetched N-bit instruction; Internal storage means for storing the N-bit instructions corresponding to the compression instruction, receiving K-compression instructions stored in the storing means as address signals, and sequentially reading corresponding N-bit instructions; And an instruction decoding means for sequentially decoding the N-bit instructions read out from the storage means. The method of claim 2, wherein the external storage means is a memory having an 8-bit memory width, the internal storage means is a memory having a 32-bit width, Wherein N is 32 and K is 4. The method of claim 2, wherein the external storage means is a memory having a 16-bit memory width, the internal storage means is a memory having a 32-bit width, Wherein N is 32 and K is 4; The apparatus according to any one of claims 1 to 4, wherein the external storage means and the internal storage means are nonvolatile semiconductor memories. The method according to any one of claims 1 to 4, wherein the internal storage means is a volatile semiconductor memory, Command length reduction device of the central processing unit, characterized in that the instructions stored in the internal storage means is loaded from an external system memory at system boot 3. The apparatus of claim 1 or 2, wherein N is a multiple of 8 and K is a multiple of four. In the central processing unit for fetching the N-bit instruction stored in the external storage means in M-bit unit and executing the instruction, The external storage means stores a plurality of N-bit instructions and compressed (N / K) bit compression instructions for a plurality of N-bit instructions frequently used in the central processing unit. And storing the frequently used N-bit instructions therein and directly decoding the N-bit instructions input from the external storage means according to the instruction sequence into executable command codes when the normal instructions are not compressed instructions. In the case where the input N-bit instruction is K compression instructions, the apparatus comprises a command reduction means for reading out the corresponding N-bit instructions stored therein using the compression instructions, and then decoding and outputting them into an executable instruction code. A command length reduction device of a central processing unit. 9. The apparatus of claim 8, wherein the instruction reduction means comprises: storage means for temporarily storing the fetched N-bit instruction; Demultiplexing means for switching and outputting N-bit instructions stored in the storing means to either one of a first output terminal and a second output terminal in accordance with a control signal; Internally storing the frequently used N-bit instructions, and sequentially reading K N-bit instructions stored at the corresponding addresses by using K compression instructions applied through the first output terminal of the multiplexing means as address signals. Storage Equipment, Multiplexing means for selectively outputting any one of a second output terminal of the multiplexing means and a read command of the internal storage means according to a control signal; And an instruction decoding means for decoding the output N-bit instruction of the multiplexing means. 10. The apparatus of claim 9, wherein the control signal is generated by a programmer by a mode setting instruction that defines the normal instruction and the compression instruction in the instruction sequence. 11. The apparatus of claim 9 or 10, wherein the external storage means is a memory having an 8-bit memory width, and the internal storage means is a memory having a 32-bit width, Wherein N is 32 and K is 4; 11. The method of claim 9 or 10, wherein the external storage means is a memory having a 16-bit memory width, the internal storage means is a memory having a 32-bit width, Wherein N is 32 and K is 4; 11. The apparatus of claim 9 or 10, wherein the external storage means and the internal storage means are nonvolatile semiconductor memories. The method of claim 9 or 10, wherein the internal storage means is a volatile semiconductor memory, And an instruction stored in the internal storage means is loaded from an external system memory upon system booting. 11. The apparatus according to any one of claims 8 to 10, wherein N is a multiple of 8 and K is a multiple of four. In the instruction processing method of the central processing unit for fetching the N-bit instruction stored in the external storage means in M-bit units and executing the instruction, Storing a plurality of N-bit instructions inside the central processing unit; An input step for programmatically entering commands by a programmer, A reading step of reading the internally stored instructions using K (N / K) bit compression instructions fetched from the external storage means according to the program; And a decoding step of decoding the instructions read in the reading step into an executable command code. 17. The method of claim 16, wherein the reading step comprises a step of temporarily storing the fetched N-bit instructions, wherein the storing step comprises the stored K (N / K) bit compression instructions as address signals, respectively. And sequentially reading the corresponding N-bit instructions stored in the CPU. 18. The method of claim 16 or 17, wherein N is a multiple of 8 and K is a multiple of four. In the instruction processing method of the central processing unit for fetching the N-bit instruction stored in the external storage means in M-bit units and executing the instruction, A first storage step of storing a plurality of N-bit instructions and compressed (N / K) bit compression instructions for a plurality of N-bit instructions frequently used in the central processing unit in the external storage means; A second storing step of storing the frequently used plurality of N-bit instructions in a central processing unit; An input step for programmatically entering commands by a programmer, Determining whether N-bit instructions input from the external storage means are normal instructions or compressed instructions according to the instruction sequence of the instruction program; A first decoding step of decoding the input N-bit instructions into an executable command code in case of the normal instruction; Reading the corresponding N-bit instructions stored therein by using the compression instructions when the N-bit instructions are K compression instructions, and And a second decoding step of decoding the read N-bit instructions into sequentially executable command codes. 20. The method of claim 19, further comprising: storing the fetched N bits of instructions temporarily; And a transferring step of transferring the N-bit instruction stored in the storing step to either the first decoding step or the reading step according to the determination result of the determining step. The reading step sequentially reads K N-bit instructions stored at the corresponding addresses by using the K (N / K) bit compression instructions transmitted in the transferring step as address signals. How to reduce length. 21. The central processing unit instruction of claim 19 or 20, wherein the determination of the determining step is determined by the programmer by a mode setting instruction that defines the normal instruction and the compression instruction in the instruction sequence. How to reduce length. 22. The method of claim 21, wherein the external storage means and the internal storage means are nonvolatile semiconductor memories. The method of claim 21, wherein the internal storage means is a volatile semiconductor memory, And said second storing step loads said N-bit instructions from an external system memory at system boot time. 21. A method according to claim 19 or 20, wherein N is a multiple of 8 and K is a multiple of four.