KR19990058819A - Router and memory management method of full-duplex architecture using flash memory - Google Patents

Abstract

The present invention relates to a router and a memory management method of a full-duplex structure using flash memory. In particular, in an electronic communication system using a packet communication and a microprocessor, high-level data link control (HDLC) packet data flowing at high speed is 1 It is about routers and memory management that can be routed to: N and N: 1.

According to the present invention, a digital signal processing processor (DSP), which duplicates a routing path connected to a gateway communication interface network and controls routing of two paths, always shares data of two paths, so that even if one path fails, Allow for immediate transfer to another path without loss.

In addition, the present invention is to store the basic program data for the operation of the central processing unit (CPU) and digital signal processing processor (DSP) used for analysis and routing of data in the flash memory, and to download the program data from the upper network manager This makes it easy to change the program without changing the memory.

Description

Full-duplex Router and Memory Management Method Using Flash Memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a router and a memory management method of a full duplex structure using a flash memory, and in particular, in an electronic communication system using a packet communication and a microprocessor, a high speed introduced at high speed. High-level Data Link Control (HDLC) The present invention relates to a router and a memory management method capable of routing packet data in 1: N and N: 1.

Transmission of signals over a transmission link requires data link control and a data link protocol. HDLC is a representative protocol for controlling data links and is defined by the International Organization for Standardization (ISO). HDLC uses synchronous transmission and is used for all kinds of data and control exchanges in a single frame format.

The data to be transmitted is combined with some overhead to form one frame for use in HDLC. Frames used in HDLC include an 8-bit Start Flag field, an Address field consisting of one or more octets (8 bits), an 8- or 16-bit Control field, It consists of an information field of arbitrary size that is data, a frame check sequence (FCS) field of 16 or 32 bits, and an end flag field of 8 bits. The frame configured as described above is packetized and transmitted through the data link.

Packet data transmitted through the data link is converted into data through a router and analyzed for use in other networks that may use different protocols. A router that performs the above role has an N: N structure for connecting N links and N links, and connects a call, transmits data and interrupts, removes a call, resets, restarts a system, and the like. Will perform the operation of.

In addition, a router for transmitting packet data according to the prior art stores a basic program for driving a processor in an erasable programmable read only memory (EPROM).

As the number of subscribers increases and the complexity of the circuits increases, there is a need to connect a single link to multiple links, or conversely, to connect data transmitted through multiple links to a single link. Therefore, there is a need to implement a router that can analyze HDLC data packets transmitted through a single data link path in real time without waiting time and transmit them to multiple transmission links.

N: N routers output packet data transmitted from N nodes to N nodes. Therefore, packet data input from N nodes cannot be transmitted to one node in real time. In addition, the basic program of the processor board among the boards configuring the router is stored in the EPROM. On systems using EPROM, you cannot electrically erase a program when you change or improve it. Therefore, there is a problem that the desired program should be replaced with the EPROM that is being programmed externally.

Therefore, in order to solve the above problems, the present invention has a first object of configuring a 1: N and N: 1 bidirectional router that analyzes N packet data in real time with a full duplex structure, and processes data. It is a second object of the present invention to provide a router and a memory management method capable of changing a program by loading data from an upper system without replacing an operation related memory.

1 is a structural diagram of a full-duplex router according to the present invention.

2 is a detailed structural diagram of an RMCA module of a router according to the present invention;

3 is a block diagram of a flash memory according to the present invention;

<Description of the symbols for the main parts of the drawings>

100: Gateway communication interface network (GCIN)

110,130: GCIN Node

120,125,140,145: buffer

200: router main control unit

210,215,240,245: buffer

220,225,250,255: Central Processing Unit

230,260: Digital Signal Processing Processor

221,226: Bidirectional Port RAM (DPRAM)

222,232,227: static RAM

223,233,228: flash memory

One preferred embodiment of the present invention devised to achieve the first object,

A GCIN comprising a buffer and a Gateway Communication Interface Network (GCIN) node for transmitting HDLC packet data; Analyzes the buffer to temporarily store HDLC packet data from GCIN, the central processing unit (CPU) to store the extracted pure data in memory by deformatting the HDLC packet data from the buffer, and the pure data stored in memory A first path comprising a digital signal processing processor (DSP) for routing and matching to a channel card, and a memory for storing pure data; A channel card that analyzes and routes a buffer that temporarily stores HDLC packet data imported from GCIN, a CPU that stores extracted pure data in memory by deformatting HDLC packet data imported from buffer, and pure data stored in memory. And a second path including a DSP to match the memory, and a memory to store the pure data.

In one embodiment of the present invention, it is preferable that the first path and the second path always share data,

Preferably, the first path and the second path are switched to another path when one path fails.

Preferably, the central processing unit stores the pure data extracted by analyzing HDLC packet data in a memory using direct memory access.

The memory for storing the pure data is preferably a bidirectional port RAM (DPRAM),

When one packet data is completely transferred to the memory, the DSP moves data of the memory to the memory of the DSP area using the direct memory access of COMMPORT1, and analyzes and routes the corresponding data to match the channel card. The memory in the DSP area is preferably static RAM (SRAM).

In addition, a second preferred embodiment of the present invention for achieving the second object,

A router comprising: a GCIN for transmitting HDLC packet data; and a plurality of processors for analyzing pure HDLC packet data transmitted through GCIN, extracting pure data, and analyzing and routing pure data to match a channel card. The data for Booter and Application Program used by is downloaded from upper network administrator.

In addition, a third preferred embodiment of the present invention for achieving the second object,

A router comprising: a GCIN for transmitting HDLC packet data; and a plurality of processors for analyzing pure HDLC packet data transmitted through GCIN, extracting pure data, and analyzing and routing pure data to match a channel card. From and used in the application is loaded in flash memory.

In a third embodiment of the present invention, the flash memory includes: a debug area for storing a minimum program for the plurality of processors to operate; It is preferable to include the area from and to the application,

Preferably, the flash memory further includes a spare area for the application program.

Preferably, the spare area for the above and the application program exists separately from the original area for the and the application program.

It is preferable that data of the spare area and the original area be downloaded from an upper network manager.

In addition, a fourth preferred embodiment of the present invention for achieving the second object,

14. A processor for downloading and operating application program data from a higher network manager, the processor comprising: a first step of checking data downloaded from a higher network manager and attaching a version to the end of the data if there is no error; A second step of initializing a conventional version memory area by finding a conventional version memory area among the duplicated memory areas; Moving the downloaded data to the initialized conventional memory area; And a fourth step of booting the processor when the movement of data is normally completed, and then executing the loaded application.

According to a fourth embodiment of the present invention, the memory management method of the router may be redundant after performing a debug program when a cold start or reset occurs due to an abnormality in the system during data movement. It is preferable to further include the step of booting by selecting the most recent version of the memory area.

The present invention analyzes high-speed HDLC packet data flowing into one node in real time and outputs it to N nodes, and processes 1: N and N: 1 bidirectional processes N packet data in real time and transmits it to one node. It's about routers. The router according to the present invention is designed to prevent packet data loss due to switching even when a failure occurs in one node or buffer in a full-duplex structure. In addition, when a program is changed using a flash memory, the program is loaded and executed from a higher system.

1 shows a structural diagram of a full-duplex router according to the present invention. As shown, a gateway communication interface network (GCIN) 100 for converting data flowing in the form of high-speed HDLC packets into pure data for analysis and transmission in real time; A router main control assembly (RMCA) module 200 of a router connected to the GCIN interface is included.

The GCIN 100 is composed of two GCIN nodes 110 and 130 for transmitting and receiving signals to each other, and four buffers 120, 125, 140, and 145 attached two to each GCIN node. do.

The RMCA module 200 is composed of two RMCA blocks that are duplicated with each other. Each RMCA block has a redundant structure that operates in either an active or standby state. Each RMCA block has two buffers 210, 215, 240, and 245 for transmitting and receiving data to and from the buffers 120, 125, 140, and 145 of the GCIN interface. 210, 215, 240 and 245 are connected to central processing unit 220, 225, 250 and 255, respectively.

The RMCA blocks are each controlled by digital signal processing processors 230 and 235. The digital signal processing processors 230 and 235 which control each RMCA block diagnose the normal state with each other, so that the active and standby states can be switched. The digital signal processing processors 230 and 235 always share data so that there is no loss of packet data due to switching even if the RMCA module changes the path.

2 shows a detailed structural diagram of an RMCA module of a router according to the present invention. As shown, the central processing unit (220) (225) (225) that is redundant with each other and controls the buffer (210) (215) connected to the GCIN; And a digital signal processor 230 for controlling the central processing unit 220, 225.

Hereinafter, the operation of the activated RMCA module of the main control board of the router will be described. HDLC packet data coming from the GCIN is deformatted through the Serial Communication Controller 1 (SCC1) port of the central processing unit 220 (225). The pure data extracted from the HDLC packet data is a dual port random access memory (DPRAM) 1 (221) (226) using a direct memory access (DMA) of the central processing unit 220 (225). Is sent).

When one packet data is completely transferred to DPRAM1, direct memory access of COMMPORT1 of digital signal processing processor 230 moves data of DPRAM1 to static RAM (SRAM) 232 in the digital signal processing processor area. The digital signal processing processor 230 analyzes and routes this data to four channel card interfaces via four COMMPORTs.

Through such a structure, even if one of the two central processing units 220 and 225 fails, the digital signal processing processor can always process accurate data in real time.

The central processing unit 220, 225 and the digital signal processing processor 230 are loaded from the upper network manager (Booter) and the application program (Application Program). The loaded data is loaded into the flash memory of the central processing unit 220, 225 and the digital signal processor 230. 3 shows a configuration diagram of a flash memory according to the present invention. As shown, it consists of a debug area and two parts from and to the application area.

The debug area is an area where a minimum program for the CPU 220 and 225 to operate is present. Areas A and B are areas from and loaded by the network manager. Areas A and B are divided into a new version and an old version according to the version of the data loaded by the network manager and the loading time. If you load a program from a network administrator and move the data from RAM to a certain area, suddenly there is a problem with the system (power off), or two areas for backup in case of a cold reset. Separate and store data in.

The program data downloaded from the network manager resides in the RAM area controlled by the central processing unit. The central processing unit checks the downloaded data and appends a version to the end of the loaded data if it is downloaded completely without errors. After retrieving the conventional version of the two areas of the flash memory and initializing the conventional area, the data loaded in the RAM is moved to the flash memory. When the movement is complete, the central processing unit performs a warm start, and then executes a program from the most recently loaded.

If a problem occurs while moving data loaded in RAM to flash memory and the system starts cold or the system has been reset completely, the central processing unit executes a debug program. Compare versions attached to the end of the zone and boot with the latest version data.

The present invention operating as described above,

High speed HDLC packet data flowing into one node is analyzed in real time and output to N nodes, and packet data flowing into N paths can be processed in real time and transmitted to one node. In order to stabilize the system, a full redundancy structure is adopted, and the design using flash memory allows the application to be downloaded from the network manager without replacing the memory.

Claims (15)

A GCIN comprising a buffer and a Gateway Communication Interface Network (GCIN) node for transmitting HDLC packet data; Analyzes the buffer to temporarily store HDLC packet data from GCIN, the central processing unit (CPU) to store the extracted pure data in memory by deformatting the HDLC packet data from the buffer, and the pure data stored in memory And a first path comprising a digital signal processing processor (DSP) for routing to a channel card and a memory for storing pure data; A channel card that analyzes and routes a buffer that temporarily stores HDLC packet data imported from GCIN, a CPU that stores extracted pure data in memory by deformatting HDLC packet data imported from buffer, and pure data stored in memory. And a second path comprising a DSP to match with a memory and a memory for storing pure data. The router of claim 1, wherein the first path and the second path always share data. The router of claim 1, wherein the first path and the second path are switched to another path when a failure occurs in one path. The router of claim 1, wherein the CPU analyzes the HDLC packet data and stores the extracted pure data in a memory using direct memory access. 2. The router of claim 1, wherein the memory for storing pure data is a bidirectional port RAM (DPRAM). The method of claim 1, wherein when one packet data is completely transferred to the memory, the DSP moves data of the memory to the memory of the DSP area using direct memory access of COMMPORT1, and analyzes and routes the corresponding data to the channel card. Router of full-duplex structure using flash memory. 7. The router of claim 6, wherein the memory of the DSP region is a static RAM. A router comprising a GCIN for transmitting HDLC packet data and a plurality of processors for analyzing pure HDLC packet data transmitted through GCIN, extracting pure data, and analyzing and routing the pure data to a channel card. The router of the full-duplex structure using flash memory, the data for the booter and the application program used in the plurality of processors are downloaded from the upper network manager. A router comprising a GCIN for transmitting HDLC packet data and a plurality of processors for analyzing pure HDLC packet data transmitted through GCIN, extracting pure data, and analyzing and routing the pure data to a channel card. The application of the plurality of processors and the application program is loaded in the flash memory, the router of the full-duplex structure using the flash memory. 10. The system of claim 9, wherein the flash memory comprises: a debug area for storing a minimum program for the plurality of processors to operate; Router with full-duplex architecture using flash memory, containing domains for application. 11. The router of claim 10, wherein the flash memory further comprises a spare area for the application program. 12. The router of claim 11, wherein the spare area for and from the application program exists separately from the original area for and from the application program. The router of claim 12, wherein data of the spare area and the original area is downloaded from a higher network manager. In the processor that operates by downloading the application data from the upper network administrator, Checking the data downloaded from the upper network manager and attaching a version to the end of the data if there is no error; A second step of initializing a conventional version memory area by finding a conventional version memory area among the duplicated memory areas; Moving the downloaded data to the initialized conventional memory area; And And a fourth step of booting the processor when the data movement is completed normally and then executing the loaded application and executing the application program. 15. The method of claim 14, wherein the memory management method of the router, In the event of an abnormality in the system during a data movement and a cold start or reset of the system, the method may further include executing a debug program and then booting by selecting the latest version among the redundant memory areas. Memory management method of full-duplex router using flash memory.