KR19990057811A - High Speed Sense Amplifiers - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention has been made in accordance with the above-described requirements, and it is an object of the present invention to provide a sensing amplifier for high-speed operation that is usefully applicable to a product requiring high-speed operation. A sensing amplifier unit enabled and disabled by the sensing amplifier and configured to sense and amplify the positive input signal and the sub-input signal, respectively, and output first and second signals complementary to each other; Enabled and disabled by a second sense enable signal, and having a first pull-up device and a first pull-down device to invert and amplify the first signal, wherein the size of the first pull-up device is larger than that of the first pull-down device. A relatively large first inversion and buffering portion; The second sense enable signal is enabled and disabled by the second sense enable signal, and includes a second pull-up device and a second pull-down device to invert and amplify the second signal, wherein the size of the second pull-down device is the second pull-up device. A relatively larger second inversion and buffering portion; A signal transfer unit configured to transfer a logic 'high' signal from the first inverting and buffering unit and a logic 'low' signal from the second inverting and buffering unit, respectively; And an output unit configured to buffer and output the signal transmitted from the signal transmission unit to the outside.

Description

High Speed Sense Amplifiers

The present invention relates to a sensing amplifier of a semiconductor memory device, and more particularly to a sensing amplifier for high speed operation.

As is well known, the sensing amplifier of a semiconductor memory device receives and amplifies data from a memory cell through a bit line and a data bus during write driving of the memory device, and then outputs the amplified data to the outside through an output buffer.

1 is a circuit diagram of a sensing amplifier according to the prior art, and it can be seen that the first, second, and third current mirror type sensing amplifiers 10, 20, and 30 are composed of an output unit 40. FIG.

Referring to FIG. 1, the first current mirror type sensing amplifier 10 includes first and second NMOS transistors 11 and 11 for sensing amplification, in which a positive input signal sai and a negative input signal saib are applied to a gate, respectively. 12), first and second PMOS transistors 13 and 14 for current mirrors connected between the drains of the first and second NMOS transistors 11 and 12 and a power supply voltage, and a first sense enable signal to a gate thereof. pse1i is applied, and includes a third NMOS transistor 15 connected between the common connected source of the first and second NMOS transistors 11 and 12 and ground to serve as a current source. The output signal sa1o-old of the first current mirror type sensing amplifier 10 is output from the common drain terminal of the second NMOS transistor 12 and the second PMOS transistor 14.

Similarly, the second current mirror type sensing amplifier 20 may include the fourth and fifth NMOS transistors 21 and 22 for sensing amplification in which the sub input signal saib and the positive input signal sai are applied to the gate, respectively. And the third and fourth PMOS transistors 21 and 22 for current mirrors connected between the drains of the fourth and fifth NMOS transistors 21 and 22 and a power supply voltage, and a gate of the first sense enable signal pse1i. ) Is applied, and includes a sixth NMOS transistor 25 connected between the common connected source of the fourth and fifth NMOS transistors 21 and 22 and ground to serve as a current source. The output signal sa1ob-old of the second current mirror type sensing amplifier 20 is output from the common drain terminal of the fifth NMOS transistor 22 and the fourth PMOS transistor 24.

Similarly, the third current mirror type sensing amplifier 20 may output an output signal sa1ob-old of the second current mirror type sensing amplifier 20 and an output signal of the first current mirror type sensing amplifier 10. a current mirror connected between the seventh and eighth NMOS transistors 31 and 32 for sensing amplification to which sa1o-old is applied to a gate, respectively, and the drain and power voltage of the seventh and eighth NMOS transistors 31 and 32, respectively. A fifth sense enable signal pse2i is applied to the fifth and sixth PMOS transistors 33 and 34 and a gate, and is connected between a common connected source and the ground of the seventh and eighth NMOS transistors 33 and 34. And a ninth NMOS transistor 35 connected to and serving as a current source. The output signal sa2ob-old of the third current mirror type sensing amplifier 30 is output from the common drain terminal of the eighth NMOS transistor 32 and the sixth PMOS transistor 34.

The output unit 40 non-inverts and buffers the output signal sa2ob-old of the third current mirror type sensing amplifier 30 to output the final output signal sa3ob-old. 42 and the third to fifth inverters 43 and 44 for inverting and buffering the output signal sa2ob-old of the third current mirror type sensing amplifier 30 and outputting the final output signal sa3o-old. 45). The first and fifth inverters are enabled or disabled controlled by the control signals psoi and psoib.

Referring to the operation of the conventional current mirror type sensing amplifier having the above structure, first, the first and second current mirror type sensing amplifiers 10 and 20 are enabled by the first sense enable signal pse1i. The primary and secondary input signals sai and saib are first sensed and then the third current mirror type sense amplifier 30 is enabled by the second sense enable signal pse2i to enable the first and second input signals. Secondary sensing amplification of the output signals sa1o-old and sa1ob-old of the current mirror type sensing amplifiers 10 and 20, and then final output signals sa3o-old and sa3ob-old through the output unit 40 Outputs

However, such a conventional sensing amplifier does not have a sensing speed as necessary in a product requiring high speed, and thus, a sensing amplifier requiring a higher speed operation is required.

Accordingly, an object of the present invention is to provide a sensing amplifier for high-speed operation usefully applicable to a product requiring high-speed operation, which is devised by the above-described requirements.

1 is a circuit diagram of a sense amplifier of a conventional semiconductor memory device.

2 is a circuit diagram of a sensing amplifier of a semiconductor memory device according to an embodiment of the present invention.

3 is a waveform diagram illustrating output results of FIGS. 1 and 2 for each input and control signal;

4 is a waveform diagram illustrating the output results of FIGS. 1 and 2 at the point “A” of FIG. 3.

Explanation of symbols on the main parts of the drawings

100: detection amplifier 200: first inversion and buffering unit

300: first inversion and buffering unit 400: signal transmission unit

500: output unit

In order to achieve the above object, the present invention is enabled and disabled by the first sense enable signal, and detects and amplifies the positive input signal and the sub-input signal, respectively, and outputs complementary first and second signals. Sensing amplification unit; Enabled and disabled by a second sense enable signal, and having a first pull-up device and a first pull-down device to invert and amplify the first signal, wherein the size of the first pull-up device is larger than that of the first pull-down device. A relatively large first inversion and buffering portion; The second sense enable signal is enabled and disabled by the second sense enable signal, and includes a second pull-up device and a second pull-down device to invert and amplify the second signal, wherein the size of the second pull-down device is the second pull-up device. A relatively larger second inversion and buffering portion; A signal transfer unit configured to transfer a logic 'high' signal from the first inverting and buffering unit and a logic 'low' signal from the second inverting and buffering unit, respectively; And an output unit configured to buffer and output the signal transmitted from the signal transmission unit to the outside.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 illustrates a sensing amplifier according to an embodiment of the present invention. As shown in FIG. 2, the sensing amplifier according to an embodiment of the present invention includes a sensing amplifier 100, first and second inverting and buffering units 200 and 300, a signal transmitting unit 400, and It consists of an output unit 500.

The sensing amplifier 100 is a current mirror type sensing amplifier, and is enabled and disabled by the first sense enable signal pse1i, and senses and amplifies the positive input signal sai and the negative input signal saib, respectively. The first signal saio and the second signal saiob, which are complementary to each other, are output.

The first inverting and buffering unit 200 receives a second sense enable signal pse2i as a gate, a NMOS transistor 201 having a source connected to a ground terminal, and a first signal sa1o as a gate. A pull-down device NMOS transistor 203 whose source is connected to the drain of the NMOS transistor 201, and the first signal sa1o are input to the gate, a source is connected to a power supply voltage terminal, and a drain thereof is the NMOS transistor 203. A PMOS transistor 202 for a pull-up element connected to the drain of the C1, and is enabled and disabled by the second sense enable signal pse2i, and inverted and amplified by the first signal sa1o, The size of the pull-up device 202 is larger than that of the pull-down device 201 and outputs a 'high' signal that is relatively larger than the second inversion and buffering unit 300.

The second sense enable signal is a delayed signal delayed by a predetermined time from the first sense enable signal.

The second inverting and buffering unit 300 receives the second sense enable signal pse2i as a gate, and a NMOS transistor 301 having a source connected to a ground terminal, and a second signal sa1ob as a gate. A pull-down device NMOS transistor 303 whose source is connected to the drain of the NMOS transistor 301, and the second signal sa1ob are input to the gate, a source is connected to a power supply voltage terminal, and a drain is connected to the second NMOS. A PMOS transistor 302 for a pull-up element connected to the drain of the transistor, the enable and disable by the second sense enable signal pse2i, and inverted and amplified the second signal sa1ob, The size of the pull-down element 301 is larger than that of the pull-up element 302 and outputs a 'low' signal that is relatively larger than the first inversion and buffering unit 200.

The signal call transfer unit 400 inverts the output signal from the second inversion and buffering unit 300 by the inverter 403 and inputs it to a gate, thereby providing a logic 'high' from the first inversion and buffering unit 200. The PMOS transistor 401 for transmitting a signal to the output unit 500 and the output signal from the first inverting and buffering unit 200 are inputted to the gate, and the logic from the second inverting and buffering unit 300 is' And a NMOS transistor 402 that delivers a low 'signal to the output.

The output unit 500 includes first and second inverters 501 and 502 for non-inverting and buffering the output signal sa2o from the signal transfer unit 400 to output the final output signal sa3o, and also the signal transfer unit. And third to fifth inverters 501, 502, and 503 for inverting and buffering the output signal sa2o from 400 to output the final output signal sa3ob. The second and fifth inverters are enabled or disabled which are controlled by control signals psoi and psoib.

3 is a timing diagram showing the response time in the conventional circuit when the sense amplifier circuit of the present invention is implemented. The sense amplifier final output signals sa3o and sa3ob of the present invention can be compared with the conventional sense amplifier final output signals sa3o_old and sa3ob_old. In FIG. 3, it can be seen that the response time of each output signal is differentiated, but when it is enlarged further, it will be clear.

FIG. 4 is an enlarged view of a portion (A) in which the output signal of each sense amplifier appears in the timing diagram of FIG. 3. As can be seen in the figure, it can be seen that the conventional sense amplifier circuit takes 173.5 ns to sense the final output signal. However, since the sense amplifier of the present invention is implemented, it can be seen that it takes 167.7 ns to 167.8 ns to sense the final output signal. Therefore, since the present invention is implemented, the delay time can be improved by about 30% compared with the conventional technology, thereby improving the detection speed and reducing the power consumption.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.

As described above, the sensing amplifier of the semiconductor memory device according to the present invention differentially amplifies the positive data and the secondary data of the data bus line by using a current mirror type sensing amplifier, and then amplifies the second through the inverter amplifier. By doing so, it provides an effect that can improve the sensing speed.

Claims (6)

A sensing amplifier unit that is enabled and disabled by the first sense enable signal and senses and amplifies the positive input signal and the sub-input signal, respectively, and outputs first and second signals complementary to each other; Enabled and disabled by a second sense enable signal, and having a first pull-up device and a first pull-down device to invert and amplify the first signal, wherein the size of the first pull-up device is larger than that of the first pull-down device. A relatively large first inversion and buffering portion; The second sense enable signal is enabled and disabled by the second sense enable signal, and includes a second pull-up device and a second pull-down device to invert and amplify the second signal, wherein the size of the second pull-down device is the second pull-up device. A relatively larger second inversion and buffering portion; A signal transfer unit configured to transfer a logic 'high' signal from the first inverting and buffering unit and a logic 'low' signal from the second inverting and buffering unit, respectively; And An output unit for buffering the signal transmitted from the signal transmission unit to output to the outside Sensing amplifier of a semiconductor memory device comprising a. The method of claim 1, And the second sense enable signal is a delay signal delayed by a predetermined time than the first sense enable signal. The method of claim 1, And the first sensing amplifier includes a current mirror type sensing amplifier. The method of claim 1, The first inversion and buffering unit, A first NMOS transistor receiving the second sense enable signal as a gate and having a source connected to a ground terminal; A second NMOS transistor for the first pull-down element that receives the first signal as a gate and whose source is connected to a drain of the first NMOS transistor; And a PMOS transistor for the first pull-up element receiving the first signal as a gate, a source connected to a power supply voltage terminal, and a drain connected to a drain of the second NMOS transistor. The method of claim 1, The second inversion and buffering unit, A first NMOS transistor receiving the second sense enable signal as a gate and having a source connected to a ground terminal; A second NMOS transistor for the second pull-down element, which receives the second signal as a gate and whose source is connected to a drain of the first NMOS transistor; And a PMOS transistor for the second pull-up element, wherein the second signal is input to the gate, a source is connected to a power supply voltage terminal, and a drain is connected to a drain of the second NMOS transistor. The method of claim 1, The signal transmission unit, A PMOS transistor receiving an inverted output signal from the second inverting and buffering unit as a gate and transferring a logic 'high' signal from the first inverting and buffering unit to the output unit; And And an NMOS transistor receiving an output signal from the first inverting and buffering unit as a gate and transferring a logic 'low' signal from the second inverting and buffering unit to the output unit.