KR19990054337A - Exponential computing device - Google Patents

Abstract

A. Description of the Related Art

To a digital circuit for performing an exponential operation.

B. Technical Problems to be Solved by the Invention

The present invention provides an exponential arithmetic unit having a simple circuit implementation and a high processing speed.

C. The point of the solution of the invention

An apparatus for performing an exponentiation operation, comprising: a register for storing an initial exponent value and a base value; a register for storing a binary bit value of the exponent; A shift register for shifting and outputting the leftmost bit value of the binary bit value, a first multiplier for receiving the base and exponent operation values as inputs and performing multiplication and output, And a multiplexer for selectively outputting output values of the first multiplier and the second multiplier according to a value output from the shift register, do.

D. Important Uses of the Invention

Used to perform exponentiation.

Description

Exponential computing device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital circuit, and more particularly, to a digital circuit performing an exponential operation.

Typically in digital circuits X ^Y The simplest method for constructing a circuit that performs an operation, that is, an exponential operation, is to use a multiplier, X Index Y Number of times.

However, although the above-described method is simple to implement the circuit, Y The number of clock cycles is required and the speed becomes slow.

In addition, a plurality of multipliers can be used to solve the above-mentioned delay in speed. In this case, although the speed of operation is improved, there is a problem that the circuit becomes complicated.

As described above, conventionally, when one multiplier is used in performing the exponential operation, the implementation of the circuit is simple but the operation speed is slow. In the case of using multiple multipliers, the operation speed increases but the circuit becomes complicated there was.

It is therefore an object of the present invention to provide a digital circuit which performs an exponential operation which can simplify the implementation of the circuit and increase the operation speed.

1 is a circuit diagram of an exponent computing apparatus according to an embodiment of the present invention;

FIG. 2 is a flow chart of operation control of an exponent operating apparatus according to an embodiment of the present invention,

3 is a diagram illustrating an example of an exponential operation result according to an embodiment of the present invention.

According to an aspect of the present invention, there is provided an apparatus for performing an exponentiation operation, the apparatus comprising: a register for storing an initial exponent value and a base value; A shift register for storing a binary bit value of the binary bit value and shifting leftward every cycle to output the leftmost bit value of the binary bit value and a multiplier for receiving the base value and the exponent value in two inputs, A second multiplier for receiving a base value and an exponent operation value output from the first multiplier, performing a multiplication and outputting a base value, and a second multiplier for outputting a result of the first multiplier according to a value output from the shift register, And a multiplexer for selectively outputting output values of the multiplier and the second multiplier.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Many specific details, such as the specific process flow in the following description and the accompanying drawings, are set forth in order to provide a more thorough understanding of the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And a detailed description of known functions and configurations that may unnecessarily obscure the gist of the present invention will be omitted

1 shows a circuit diagram of an exponent computing apparatus according to an embodiment of the present invention. Referring to FIG. 1, a base register is stored in a first register 100 and applied to a first multiplier 102. In the second register 104, "1" is stored as an initial value, and an exponent operation value that is increased as the exponent operation is performed is stored and applied to the second multiplier 106. The second multiplier 106 receives the exponent value stored in the second register 104 as two inputs, multiplies the two input values, and outputs the result. The first multiplier 102 receives the output value of the second multiplier 106 and the base value stored in the first register 100 as two inputs, performs multiplication, and outputs the result of the multiplication. The shift register 108 stores the exponent value as a binary bit value and outputs the leftmost bit value of the binary bit value one bit at a time in each clock cycle and is shifted to the left. The multiplexer 110 receives the output from the first multiplier 102 and the second multiplier 106 and selects one of the two values according to the output value of the shift register 108 and outputs the selected value to the second register 104 .

2 is a flowchart illustrating an operation of the exponentiation apparatus according to an embodiment of the present invention. An embodiment of the present invention will be described in detail with reference to FIG.

First, the theoretical background of FIG. 2 will be briefly described. Underground X Index Y And the exponent value E = X ^Y , The exponent value E If you want to save Y As a binary number.

Y = y _n-1 2 ^n-1 + y _n-2 2 ^n-2 + ⃛ + y ₁ 2 ¹ + y ₀ 2 ⁰

Y To nk When a shift-right Y ^(k) If you say Y Can be expressed as follows.

Y ⁽ⁿ⁾ = Y

= y _n-1 2 ^n-1 + y _n-2 2 ^n-2 + ⃛ + y ₁ 2 ¹ + y ₀ 2 ⁰

= 2 (y _n-1 2 ^n-2 + y _n-2 2 ^n-3 + ⃛ + y ₁ 2 ⁰ ) + y ₀

^{= 2Y (n-1) +} y 0

Here, the above equation can be expressed as a general expression.

Y ⁽ⁱ⁾ = 2Y ^(i-1) + y _ni , 1? ^I? N

In the above equation, Y ⁽⁰⁾ = 0 . Therefore, E Can be expressed as follows.

E ⁽ⁱ⁾ = X ^{Y (i)} = X ^{2Y (i-1) + y n-1} = [X ^{Y (i-1)} ] ² X ^{y ni}

In the above equation y _ni Is either 0 or 1 E ⁽ⁱ⁾ Can be represented by the following general term.

E ⁽ⁱ⁾ = [E ^(i-1) ] ² , (y _ni = 0 )

E ⁽ⁱ⁾ = [E ^(i-1) ] ² X, (y _ni = 1 )

Therefore, E Exponent value Y Lt; RTI ID = 0.0 > number of bits. ≪ / RTI > FIG. 2 is a graph showing an exponent value E = X ^Y The operation of the exponent calculation apparatus of FIG. 1 is shown. For convenience of explanation, in the embodiment of the present invention X Quot; 3 "," Y Quot; is " 5 ".

first X ^Y In order to obtain the value, the first register (100) X Value " 3 " is stored and the shift register 108 stores an exponent Y ≪ / RTI > that is, 101 ₍₂₎ Is stored. If the exponent calculation operation is performed, the exponent value E 1 is stored in step 202, and in step 202, i Quot; 1 " is stored as an initial value. remind i Is stored in the shift register 108 Y Represents the number of shifts to the left of the binary bit value, i.e., one cycle, and is greater than or equal to " 1 " as shown in the above- Y The number of bits in binary n That is, less than or equal to "3". In step 204, i end n Is checked. In the above, n An index Y Quot; 3 ". At this time, i end n (206), the exponent value E There E × E I.e., 1 x 1 Is stored. Then, in step (208) i The old i Quot; 1 " is stored. In step 210, Y ≪ / RTI > that is, 111 ₍₂₎ Quot; 1 " is checked. At this time, Y Quot; 1 ", the exponent value E There E × X That is, 1 x 3 That is, 3 is stored, and in step 214, Y Are shifted left by one bit. That is, one bit shifted left Y The binary bit value of 110 ₍₂₎ .

Alternatively, in step 210 Y Quot; 1 " is not " 1 ", the exponent value E The process proceeds directly to step (214), and as described above Y Is shifted left by one bit. Then, the process returns to step (204) i The value is n (204) to (214) are repeated until the value becomes larger than the predetermined value. And i The value is n If it is greater than the value, i When the value becomes " 4 ", it exits the exponentiation loop. Through the process of FIG. 2, X Is " 3 " Y Quot; 5 ", the exponent value E The result obtained is shown in Fig.

Therefore, Y When the above loop is performed only for the number of cycles corresponding to the number of binary bits of the exponentiation value E .

As described above, according to the present invention, since the exponent calculation value can be obtained by performing only the number of cycles corresponding to the number of binary bits of the exponent using two multipliers in performing the exponent operation, the configuration of the circuit is simplified, Is advantageous.

Claims (1)

An apparatus for performing exponentiation, A first register for storing an initial exponentiation value, A second register for storing a value of a base, A shift register which is composed of registers corresponding to the number of binary bits of the exponent, stores a binary bit value of the exponent, shifts every cycle, and outputs a bit value of the binary bit value; A first multiplier for receiving the exponential operation value stored in the first register as two inputs, performing multiplication and outputting the result, A second multiplier for receiving a base value output from the second register and an exponential operation value output from the first multiplier, And a multiplexer for selectively outputting output values of the first multiplier and the second multiplier according to a value output from the shift register.