KR19990054226A - Relay printed circuit board of test equipment - Google Patents

Abstract

The present invention relates to a test facility, by installing a relay PCB in the test facility, connecting only a predetermined number of input / output pins among the plurality of input / output pins formed in one IC to the relay PCB and testing them in a time-division manner to test a large number of ICs at once. Testing can reduce test costs and increase productivity.

Description

Relay printed circuit board of test equipment

The present invention relates to a test facility, and more particularly, by installing a relay printed circuit board for testing in a time-division manner by connecting only a predetermined number of input / output pins among a plurality of input / output pins of an IC to improve reliability of a large number of ICs at one time. A relay printed circuit board of a test facility.

In general, a test is a computer program that is executed on a tester device to quickly inspect the electrical characteristics, functional characteristics, and speed of a packaged semiconductor product. To distinguish.

The test facility consists of a tester device and a handler device. The tester device is programmed with electrical characteristics and functions of semiconductor products to control the handler device. In addition, the handler device is an device that is electrically connected to the tester device and creates a condition for inspecting the semiconductor product and classifies the semiconductor package according to the test result according to the test result.

Here, the types of handler devices are largely divided into memory handlers and logic handlers. In the case of the memory handler device, more than 32 ICs can be measured simultaneously according to the increase in test time of the memory device (DRAM, SRAM, graphics, etc.) and the variety of package types, and the flexibility of the device is required to cope with various packages. It is true.

However, for example, in the case of graphic memory in which the input / output pin of the memory device is 16 pins or more and two cells are mounted in one semiconductor package, the specification of the equipment of the test facility, that is, the input / output test pin of the IC connected to the input / output pin of the IC Because of the limited number, there is a problem in that a large number of ICs are tested at a time, which reduces productivity and increases test costs.

For example, with test facility T5365, one of the graphics memory products, Sam, which reads and reads and writes RAM, tests Window Random Access Memory mounted in a single semiconductor package. Only Windows RAM can be tested.

Here, the RAM embedded in the window RAM has 32 input / output pins, and the spring has 16 input / output. On the other hand, the T5365 test facility has 288 input / output test pins connected to the input / output pins of the window RAM, and 144 driver test pins connected to the driver pins including control pins, ground pins, Vcc pins, etc. except the input / output pins.

Therefore, the T5365 test fixture can be equipped with six window rams with 48 I / O pins, but in practice, as there are 2 ⁿ window rams for testing, 94 redundant I / Os are proposed, as suggested in Application Nos. 95-37824. Only eight Windows RAMs are tested at a time by using connection and driver connection pins.

Accordingly, an object of the present invention has been devised in view of the above problems, and tests a relay printed circuit board for testing in a time division manner by connecting only a predetermined number of input / output pins among a plurality of input / output pins formed in one IC. It is located on a relay printed circuit board in a test facility that can be installed on a board to test more than eight ICs at a time, reducing test costs and improving productivity.

1 is a conceptual diagram schematically showing the structure of a test facility according to the present invention;

2 is a conceptual diagram illustrating a relay circuit configuration and an IC test method according to the present invention.

In order to achieve the above object, the present invention provides a tester unit in which electrical characteristics and functions of an IC to be tested are programmed, a handler electrically connected to the tester unit, and a tester for creating an inspection condition of the IC, and installed inside the handler. And a test board having a main printed circuit board, a test board having a plurality of sockets mounted on an upper surface of the main printed circuit board, and equipped with the IC on one surface thereof, and electrically connected to the main printed circuit board and the socket on one surface thereof. It includes a test head composed of a relay printed circuit board on which a relay circuit is formed for time-divisionally testing the IC.

Preferably, the socket is electrically connected to an input / output connection pin to which only a predetermined number of input / output pins of the plurality of input / output pins formed in the IC are connected, a driver input / output connection pin to which the driver pin of the IC is connected, and the relay printed circuit board are electrically connected. Relay printed circuit board connection pins are formed.

Preferably, the remaining input / output pins other than a predetermined number of input / output pins connected to the input / output connecting pins are connected to a relay printed circuit board and tested in time division.

Hereinafter, a test facility structure and a test method according to the present invention will be described with reference to FIGS. 1 and 2.

1 is a conceptual diagram schematically showing a structure of a test facility according to the present invention, and FIG. 2 is a conceptual diagram for explaining a relay circuit configuration and an IC test method according to the present invention. For convenience of description, the above-described window RAM will be described as an example.

As shown in FIG. 1, the test facility 100 is electrically connected to the tester unit 110 and the tester unit 110 in which electrical characteristics and functions of an IC (eg, window RAM) to be tested are programmed. The handler 120 is configured to create a RAM condition and a test head 130 installed in the handler 120 to test a plurality of window RAMs according to a test program transmitted from the tester unit 110.

Here, the test head 130 is mounted on the upper surface of the main printed circuit board 131 electrically connected to the tester unit 110 and the main printed circuit board 131 and electrically connected to the window RAM on the upper surface. The test board 133 having the socket 135 to be mounted thereon, and a relay circuit as shown in FIG. 2 on one surface of the test board 133 electrically connected to each socket 135 are connected to the spring of the window RAM. 16 input / output pins 150 are configured as a relay printed circuit board 140 (hereinafter referred to as a relay PCB) to which one-to-one connection is made.

Preferably, the reason for electrically connecting the input / output pins 150 of the sam to the relay PCB 140 is that the sam has only a read function, so that the test response speed is fast and the number of the input / output pins 150 is small so that the input / output pins ( 150 test takes less test time.

Each of the sockets 135 includes a plurality of connection pins (not illustrated) for electrically connecting driver pins including control pins, ground pins, Vcc pins, and relay PCBs 140, etc. O) is formed. Preferably, 32 of the plurality of connection pins are input / output test pins (not shown) connected one-to-one with input / output pins connected to the ram, and four relay PCB connection pins 136 electrically connected to the relay PCB 140. And the rest are driver test pins (not shown).

Meanwhile, a conceptual diagram of a relay circuit configured on one surface of the relay PCB 140 will be described with reference to FIG. 2.

One end of the relay PCB 140 has 16 output terminals 141 connected to the input / output pins 150 of the SAM in a one-to-one manner and transmitting a test signal to the input / output pins 150, and each output terminal 141 is formed. ) Is connected to a relay 143 for delaying an electrical signal for a predetermined time. In addition, two input wires 145 and 146 are connected to the relay 143, and one of the relay PCB connection pins 136 formed on the socket 135 is connected to the relay via a coaxial cable 147. The test signal input wiring 145 receives the test signal from the PCB connection pin 136, and the other is connected to the main printed circuit board 131 to control signals of the relay 143, for example, a system interface control command CW8, Control signal input wiring 146 for receiving CW4, CW2, CW1.

Here, one relay PCB connection pin 136 is sequentially connected to four test signal input wirings 145, so that four test groups, that is, the first test group 149a and the second test group 149b, and the first test group 149b are connected. The third test group 149c and the fourth test group 149d are formed. In addition, each of the control signal input wires 146 has four control signal input wires 145 formed at the same position among the test groups 149a, 149b, 149c, and 149d connected in parallel, and in parallel. The same control signal is input to the four control signal input wires 146 connected to each other. For example, the control signal input wiring 146 connected to the relay A1 formed at the first of the first test group 149a and the control signal input wiring 146 connected to the relay A2 located at the first of the second test group 149b. ), The control signal input wiring connected to the relay A3 located in the first of the third test group 149c, and the test input wiring 146 connected to the relay A4 located in the first of the fourth test group 149d in parallel. It is connected to deliver a CW8 control signal to each relay (143).

A process of testing the window RAM using the test facility configured as described above (eg, the T5365 test facility) will be described below.

First, the window RAM to be tested is mounted in the socket 135 of the test board 133. 32 of the two cells included in the window RAM are connected to the RAM 32 input / output pins one-to-one to the input / output test pins and 16 Input / output pins 150 are electrically connected to the output terminal 141 of the relay PCB 140. Here, the number of window RAMs mounted in one handler 120 is sixteen.

When the window RAM is mounted on the test board 133, the test unit 110 applies an electrical signal such as a test signal and a control signal to the main printed circuit board 131 according to the input test program. In this case, some of the electrical signals applied to the main printed circuit board 131 are transmitted to the relay PCB 140 along the metal wiring formed on the main printed circuit board 131, and some of them are applied to the test board 133. Here, the electrical signals applied to the relay PCB 140 are control signals CW8, CW4, CW2, and CW1 for sequentially controlling the relays 143, and the electrical signals applied to the test board 133 are window RAMs. Test signal for testing.

As such, when an electrical signal is applied to the test board 133 and the relay PCB 140, the window RAM is tested. In the case of the RAM, since the input / output pins are connected to the input / output test pins one-to-one, a test signal is simultaneously applied to 32 input / output pins. In the case of the sam, the input / output pin 150 is connected to the output terminal 141 formed on the relay PCB 140 in one-to-one manner and sequentially receives the test signal according to the control signal.

Here, the test process of the Sam is electrically connected to the input and output pins 150 to the relay PCB 140 will be described in more detail with reference to FIG.

A test signal is transmitted from each relay PCB connection pin 136, and control signals CW8, CW4, CW2, and CW1 are applied to the relay PCB 140 in the main printed circuit board 131.

First, the control signal CW8 turns on the relay A1 included in the first test group 149a, applies a test signal to the SDQ 0 connected to the output terminal 141, and then tests the SDQ 0. The relay A1 is turned off to cut off the test signal. Thereafter, the relay A2 included in the second test group 149b is turned on to test the SDQ 4, and when the test is completed, the relay A2 is turned off to block the test signal. Subsequently, the relay A3 included in the third test group 149c is turned on to test the SDQ 8, and when the test is completed, the relay A3 is turned off to block the test signal. When the SDQ 8 is tested, the relay A4 included in the fourth test group 149c is turned on to test the SDQ 12, and when the test is completed, the relay A4 is turned off to block the test signal.

Second, when the control signal CW4 is tested by applying a test signal to the SDQ 1 connected to the output terminal 141 by turning on the relay B1 included in the first test group 149a and then testing it. The relay B1 is turned off to cut off the test signal. Thereafter, the relay B2 included in the second test group 149b is turned on to test the SDQ 5, and when the test is completed, the relay B2 is turned off. Subsequently, the relay B3 included in the third test group 149c is turned on to test the SDQ 9, and when the test is completed, the relay B3 is turned off. When the SDQ 9 is tested, the relay B4 included in the fourth test group 149d is turned on to test the SDQ 13, and when the test is completed, the relay B4 is turned off.

Third, when the control signal CW2 is tested by applying a test signal to the SDQ 2 connected to the output terminal 141 by turning on the relay C1 included in the first test group 149a, and then testing the SDQ 2. The relay C1 is turned off to cut off the test signal. Thereafter, the relay C2 included in the second test group 149b is turned on to test the SDQ 6, and when the test is completed, the relay C2 is turned off. Subsequently, the relay C3 included in the third test group 149c is turned on to test the SDQ 10, and when the test is completed, the relay C3 is turned off. When the SDQ 10 is tested, the relay C4 included in the fourth test group 149d is turned on to test the SDQ 14, and when the test is completed, the relay C4 is turned off.

Fourth, if the control signal CW1 is tested by applying a test signal to the SDQ 3 connected to the output terminal 141 by turning on the relay D1 included in the first test group 149a, the SDQ 3 is tested. The relay D1 is turned off to cut off the test signal. Thereafter, the relay D2 included in the second test group 149b is turned on to test the SDQ 7, and when the test is completed, the relay D2 is turned off. Subsequently, the relay D3 included in the third test group 149c is turned on to test the SDQ 11, and when the test is completed, the relay D3 is turned off. When the SDQ 11 is tested, the relay D4 included in the fourth test group 149c is turned on to test the SDQ 15, and when the test is completed, the relay D4 is turned off.

Here, the control signals CW8, CW4, CW2, CW1 are signals applied simultaneously.

In this way, when testing the IC by mounting the relay PCB on the test board, the 48 input / output pins formed in the window RAM can be tested using 36 connection pins, thus increasing the number of ICs tested at once from 16 to 16. .

As described above, in the present invention, a large number of IC tests are performed by forming a relay PCB in a test facility and testing a time division method by connecting only a predetermined number of input / output pins of a plurality of input / output pins formed in one IC to the relay PCB. This reduces test costs and increases productivity.

Claims (5)

A tester unit in which electrical characteristics and functions of the IC to be tested are programmed; A handler electrically connected to the tester to create an inspection condition of the IC; A test board installed in the handler and having a main printed circuit board, a test board having a plurality of sockets mounted on an upper surface of the main printed circuit board and equipped with the IC on one surface thereof, and electrically connected to the main printed circuit board and the socket. And a test head comprising a relay PCB connected to the circuit board and having a relay circuit formed thereon for time-divisionally testing the IC on one surface thereof. The relay PCB of claim 1, wherein the IC is a dual port in which two cells are embedded in one IC. 2. The apparatus of claim 1, further comprising: an input / output connecting pin connected to the socket, wherein only a predetermined number of input / output pins of a plurality of input / output pins formed in the IC are connected; A driver input / output connection pin to which the driver pin of the IC is connected; The relay PCB of the test fixture, characterized in that the relay PCB connecting pin is electrically connected to the relay PCB is formed. The relay PCB of claim 3, wherein the remaining input / output pins other than a predetermined number of input / output pins connected to the input / output connecting pins are connected to the relay PCB and tested in time division. The relay PCB of claim 4, wherein the number of the input / output pins connected to the relay PCB is smaller than the number of the input / output pins connected to the input / output connection pins.