KR19990052693A - Manufacturing Method of Flash Memory Cell - Google Patents
Manufacturing Method of Flash Memory Cell Download PDFInfo
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- KR19990052693A KR19990052693A KR1019970072224A KR19970072224A KR19990052693A KR 19990052693 A KR19990052693 A KR 19990052693A KR 1019970072224 A KR1019970072224 A KR 1019970072224A KR 19970072224 A KR19970072224 A KR 19970072224A KR 19990052693 A KR19990052693 A KR 19990052693A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000012535 impurity Substances 0.000 claims abstract description 25
- 238000009792 diffusion process Methods 0.000 claims abstract description 7
- 239000011229 interlayer Substances 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 5
- 239000000969 carrier Substances 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229920003026 Acene Polymers 0.000 description 1
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- MWPLVEDNUUSJAV-UHFFFAOYSA-N anthracene Chemical compound C1=CC=CC2=CC3=CC=CC=C3C=C21 MWPLVEDNUUSJAV-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
본 발명은 플래쉬 메모리 셀의 제조방법에 관한 것으로서 제 1 도전형의 반도체기판 상의 소정 부분에 게이트산화막을 개재시켜 부유게이트를 형성하는 공정과, 상기 부유게이트 및 반도체기판 상의 소정 부분에 층간절연막을 개재시켜 채널 방향과 수직하는 방향으로 길게 패터닝되어 워드라인으로 사용되는 제어게이트를 형성하는 공정과, 상기 반도체기판의 소정 부분에 제 2 도전형의 불순물을 고농도와 저농도로 각각 이온주입하여 2중 확산(double diffusion) 구조를 이루는 제 1 및 제 2 소오스영역을 형성하는 공정과, 상기 반도체기판의 소정 부분에 제 2 도전형의 불순물을 저농도로 이온 주입하여 LDD영역을 형성하는 공정과, 상기 부유게이트 및 상기 제어게이트의 측면에 측벽을 형성하고 상기 반도체기판에 상기 LDD영역과 중첩하도록 제 2 도전형의 불순물을 고농도로 이온 주입하여 드레인영역을 형성하는 공정을 구비한다. 따라서, LDD영역에 의해 단 채널 효과를 방지하며, 또한, 포켓영역에 의해 LDD영역과 접합에 의해 프로그램시 핫 캐리어(hot carrier)의 발생을 용이하게하여 프로그램 효율을 증가시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory cell, comprising: forming a floating gate by interposing a gate oxide film in a predetermined portion on a semiconductor substrate of a first conductivity type; Forming a control gate which is patterned in a direction perpendicular to the channel direction to be used as a word line, and double-diffusion by ion implanting impurities of a second conductivity type into predetermined portions of the semiconductor substrate at high and low concentrations, respectively. forming a first diffusion region and a second source region having a double diffusion structure; forming a LDD region by ion implanting impurities of a second conductivity type into a predetermined portion of the semiconductor substrate at low concentration; Forming a sidewall on the side of the control gate and overlapping the LDD region on the semiconductor substrate; By ion implanting impurities at a high concentration and a step of forming a drain region. Therefore, the short channel effect can be prevented by the LDD region, and the programming efficiency can be increased by facilitating generation of hot carriers during programming by bonding with the LDD region by the pocket region.
Description
본 발명은 플래쉬 메모리 셀의 제조방법에 관한 것으로서, 특히, 드레인영역을 LDD(Lightly Doped Drain) 구조로 형성할 수 있는 플래쉬 메모리 셀의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory cell, and more particularly, to a method of manufacturing a flash memory cell capable of forming a drain region in a lightly doped drain (LDD) structure.
플래쉬 메모리 셀은 메모리 어레이 셀들을 동시에 소거(erase)시킬 수 있으므로 소거 속도가 빠른 비활성 메모리 소자이다. 플래쉬 메모리 셀은 채널에서 발생되는 핫-전자를 제어게이트에 인가되는 전압에 의해 부유게이트(floating gate)에 주입되므로써 쓰기(write)가 되고, 또한, 부유게이트의 전자가 소오스영역이나 드레인영역, 또는, 반도체기판으로 Fowler-Nordheim 터널링되므로써 소거(erase)된다.A flash memory cell is an inactive memory device having a high erase speed because it can erase memory array cells at the same time. Flash memory cells are written by injecting hot-electrons generated in a channel into a floating gate by a voltage applied to a control gate, and the electrons of the floating gate are source or drain regions, or It is erased by the Fowler-Nordheim tunneling into the semiconductor substrate.
도 1a 내지 도 1d는 종래 기술에 따른 플래쉬 메모리 셀의 제조 공정도이다.1A to 1D are manufacturing process diagrams of a flash memory cell according to the prior art.
도 1a를 참조하면, P형의 반도체기판(11) 상의 소정 부분에 열산화에 의해 게이트산화막(15)을 형성하고, 이 게이트산화막(15) 상에 불순물이 도핑된 다결정실리콘을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착한 후 포토리쏘그래피(photolithography) 방법으로 패터닝하여 부유게이트(17)를 형성한다.Referring to FIG. 1A, a gate oxide film 15 is formed on a predetermined portion on a P-type semiconductor substrate 11 by thermal oxidation, and polycrystalline silicon doped with impurities on the gate oxide film 15 is subjected to chemical vapor deposition ( Chemical Vapor Deposition: Hereinafter, the floating gate 17 is formed by depositing by a CVD method and patterning by a photolithography method.
도 1b를 참조하면, 부유게이트(17)의 표면을 열산화하여 층간절연막(19)을 형성하다. 이 때, 반도체기판(11)의 노출된 부분에도 층간절연막(19)이 형성된다. 층간절연막(19) 상에 CVD 방법으로 불순물이 도핑된 다결정실리콘을 증착하고 채널과 수직하는 방향으로 길게 패터닝하여 워드라인으로 사용되는 제어게이트(21)를 형성한다. 이 때, 제어게이트(21)는 부유게이트(17)와 중첩되게 패터닝한다. 또한, 제어게이트(21)를 패터닝할 때 층간절연막(19)도 패터닝되어 반도체기판(11)이 노출되도록 한다.Referring to FIG. 1B, an interlayer insulating film 19 is formed by thermally oxidizing the surface of the floating gate 17. At this time, the interlayer insulating film 19 is formed on the exposed portion of the semiconductor substrate 11. A polysilicon doped with an impurity is deposited on the interlayer insulating film 19 by a CVD method, and is patterned in a direction perpendicular to the channel to form a control gate 21 used as a word line. At this time, the control gate 21 is patterned to overlap with the floating gate (17). In addition, when the control gate 21 is patterned, the interlayer insulating film 19 is also patterned so that the semiconductor substrate 11 is exposed.
도 1c를 참조하면, 반도체기판(11)의 소오스 부분에 2중 확산(double diffusion) 구조를 이루는 제 1 및 제 2 소오스영역(23)(25)을 형성한다. 상기에서 제 1 및 제 2 소오스영역(23)(25)은 소오스 부분을 노출시키는 포토레지스트(22)를 형성하고, 이 포토레지스(22)를 마스크로 사용하여 N형의 불순물을 고농도와 저농도로 2번 이온 주입하므로써 제어게이트(21)와 평행하도록 채널과 수직하는 방향으로 길게 형성된다. 이 때, 저농도의 제 2 소오스영역(25)을 고농도의 제 1 소오스영역(23)을 에워싸도록 형성한다.Referring to FIG. 1C, first and second source regions 23 and 25 having a double diffusion structure are formed in the source portion of the semiconductor substrate 11. In the above, the first and second source regions 23 and 25 form a photoresist 22 exposing the source portion, and the photoresist 22 is used as a mask to form N-type impurities at high and low concentrations. By ion implantation twice, it is formed long in the direction perpendicular to the channel so as to be parallel to the control gate 21. At this time, the low concentration second source region 25 is formed so as to surround the high concentration first source region 23.
도 1d를 참조하면, 반도체기판(11)의 드레인 부분에 N형의 불순물을 고농도로 이온 주입하여 드레인영역(29)을 형성한다. 상기에서 드레인영역(29)은 드레인 부분을 노출시키는 포토레지스트(27)를 형성하고, 이 포토레지스(27)를 마스크로 사용하여 N형의 불순물을 고농도로 이온 주입하므로써 형성된다.Referring to FIG. 1D, a drain region 29 is formed by ion implanting N-type impurities at a high concentration into the drain portion of the semiconductor substrate 11. The drain region 29 is formed by forming a photoresist 27 exposing the drain portion and implanting N-type impurities at a high concentration using the photoresist 27 as a mask.
그러나, 종래 기술에 따른 플래쉬 메모리 셀은 집적도가 향상되어 소자의 크기가 감소되면 채널의 길이가 짧아져 단채널효과(short channel effect)가 발생되는 문제점이 있었다.However, the flash memory cell according to the related art has a problem in that short channel effects occur due to shortening of the channel length when the size of the device is reduced due to the increased degree of integration.
따라서, 본 발명의 목적은 단채널효과를 방지할 수 있는 플래쉬 메모리 셀의 제조 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a flash memory cell that can prevent a short channel effect.
상기 목적을 달성하기 위한 본 발명에 따른 플래쉬 메모리 셀의 제조 방법은 제 1 도전형의 반도체기판 상의 소정 부분에 게이트산화막을 개재시켜 부유게이트를 형성하는 공정과, 상기 부유게이트 및 반도체기판 상의 소정 부분에 층간절연막을 개재시켜 채널 방향과 수직하는 방향으로 길게 패터닝되어 워드라인으로 사용되는 제어게이트를 형성하는 공정과, 상기 반도체기판의 소정 부분에 제 2 도전형의 불순물을 고농도와 저농도로 각각 이온주입하여 2중 확산(double diffusion) 구조를 이루는 제 1 및 제 2 소오스영역을 형성하는 공정과, 상기 반도체기판의 소정 부분에 제 2 도전형의 불순물을 저농도로 이온 주입하여 LDD영역을 형성하는 공정과, 상기 부유게이트 및 상기 제어게이트의 측면에 측벽을 형성하고 상기 반도체기판에 상기 LDD영역과 중첩하도록 제 2 도전형의 불순물을 고농도로 이온 주입하여 드레인영역을 형성하는 공정을 구비한다.A method of manufacturing a flash memory cell according to the present invention for achieving the above object comprises the steps of forming a floating gate by interposing a gate oxide film on a predetermined portion on a first conductive semiconductor substrate, and a predetermined portion on the floating gate and the semiconductor substrate. Forming a control gate to be used as a word line by patterning it in a direction perpendicular to the channel direction with an interlayer insulating film interposed therebetween; and ion implanting impurities of a second conductivity type in a predetermined portion of the semiconductor substrate at high and low concentrations, respectively. Forming first and second source regions having a double diffusion structure by forming a LDD region by ion implanting impurities of a second conductivity type into a predetermined portion of the semiconductor substrate at low concentration; And sidewalls formed on side surfaces of the floating gate and the control gate and overlapping the LDD region on the semiconductor substrate. And a second ion implanting impurities of the conductivity type at a high concentration so as to includes a step of forming a drain region.
도 1a 내지 도 1d는 종래 기술에 따른 플래쉬 메모리 셀의 제조 공정도1A to 1D are manufacturing process diagrams of a flash memory cell according to the prior art.
도 2a 내지 도 2e는 본 발명에 따른 플래쉬 메모리 셀의 제조 공정도2A through 2E are manufacturing process diagrams of a flash memory cell according to the present invention.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 플래쉬 메모리 셀의 제조 공정도이다.2A through 2E are manufacturing process diagrams of a flash memory cell according to the present invention.
도 2a를 참조하면, 반도체기판(31) 상의 소정 부분에 열산화에 의해 게이트산화막(35)을 형성하고, 이 게이트산화막(35) 상에 불순물이 도핑된 다결정실리콘을 CVD 방법으로 증착한 후 포토리쏘그래피(photolithography) 방법으로 패터닝하여 부유게이트(37)를 형성한다.Referring to FIG. 2A, a gate oxide film 35 is formed on a predetermined portion on a semiconductor substrate 31 by thermal oxidation, and polycrystalline silicon doped with impurities on the gate oxide film 35 is deposited by CVD. The floating gate 37 is formed by patterning by photolithography.
도 2b를 참조하면, 부유게이트(37)의 표면을 열산화하여 50∼500Å 정도 두께의 층간절연막(39)을 형성하다. 이 때, 반도체기판(31)의 노출된 부분에도 층간절연막(39)이 형성된다. 층간절연막(39) 상에 CVD 방법으로 불순물이 도핑된 다결정실리콘을 증착하고 채널과 수직하는 방향으로 길게 패터닝하여 워드라인으로 사용되는 제어게이트(41)를 형성한다. 이 때, 제어게이트(41)는 부유게이트(37)와 중첩되게 패터닝한다. 또한, 제어게이트(41)를 패터닝할 때 층간절연막(39)도 패터닝되어 반도체기판(31)이 노출되도록 한다.Referring to FIG. 2B, the surface of the floating gate 37 is thermally oxidized to form an interlayer insulating film 39 having a thickness of about 50 to 500 kV. At this time, the interlayer insulating film 39 is also formed in the exposed portion of the semiconductor substrate 31. A polysilicon doped with impurities is deposited on the interlayer insulating film 39 by a CVD method, and is patterned in a direction perpendicular to the channel to form a control gate 41 used as a word line. At this time, the control gate 41 is patterned to overlap with the floating gate 37. In addition, when the control gate 41 is patterned, the interlayer insulating film 39 is also patterned to expose the semiconductor substrate 31.
도 2c를 참조하면, 반도체기판(31)의 소오스 부분에 2중 확산(double diffusion) 구조를 이루는 제 1 및 제 2 소오스영역(45)(47)을 형성한다. 상기에서 제 1 및 제 2 소오스영역(45)(47)은 소오스 부분을 노출시키는 포토레지스트(43)를 형성하고, 이 포토레지스(43)를 마스크로 사용하여 N형의 불순물을 고농도와 저농도로 2번 이온 주입하므로써 제어게이트(21)와 평행하도록 채널과 수직하는 방향으로 길게 형성된다. 즉, 제 1 소오스영역(45)은 아세닉(As)을 1 × 1012∼ 1 × 1014／㎠ 정도의 도우즈로 주입하여 형성하고, 제 2 소오스영역(47)은 인(P)을 1 × 1014∼ 5 × 1015／㎠ 정도의 도우즈로 주입하므로써 형성된다. 이 때, 제 1 소오스영역(45)을 소거시 효율을 증가시키기 위해 부유게이트(37)와 중첩되도록 30 ∼ 60°정도의 경사각도로 이온 주입하여 형성한다. 또한, 저농도의 제 2 소오스영역(47)을 고농도의 제 1 소오스영역(45)을 에워싸도록 형성한다.Referring to FIG. 2C, first and second source regions 45 and 47 having a double diffusion structure are formed in the source portion of the semiconductor substrate 31. In the above, the first and second source regions 45 and 47 form a photoresist 43 exposing the source portion. The photoresist 43 is used as a mask to form N-type impurities at high and low concentrations. By ion implantation twice, it is formed long in the direction perpendicular to the channel so as to be parallel to the control gate 21. That is, the first source region 45 is formed by injecting an asce (As) with a dose of about 1 × 10 12 to 1 × 10 14 / cm 2, and the second source region 47 forms phosphorus (P). It is formed by injecting with a dose of about 1 × 10 14 to 5 × 10 15 / cm 2. At this time, the first source region 45 is formed by ion implantation at an inclination angle of about 30 to 60 ° so as to overlap with the floating gate 37 in order to increase the efficiency during erasing. In addition, the low concentration second source region 47 is formed so as to surround the high concentration first source region 45.
도 2d를 참조하면, 포토레지스트(43)를 제거한다. 상술한 구조의 전 표면에 포토레지스트(49)를 도포한 후 노광 및 현상하여 드레인 부분을 노출시킨다. 그리고, 포토레지스트(49)를 마스크로 사용하여 아세닉(As) 또는 인(P) 등의 N형의 불순물을 저농도로 도핑하여 LDD영역(51)과 보론(B) 또는 BF2등의 P형 불순물을 저농도로 부유게이트(37) 하부에 소정 부분 중첩되게 도핑하여 포켓영역(53)을 형성한다. 상기에서 LDD영역(51)은 아세닉(As) 또는 인(P) 등의 N형의 불순물을 1 × 1012∼ 1 × 1014／㎠ 정도의 도우즈로 이온 주입하여 형성하고, 포켓영역(53)은 보론(B) 또는 BF2등의 P형 불순물을 1 × 1012∼ 1 × 1014／㎠ 정도의 도우즈로 30 ∼ 60°정도의 경사각도로 이온 주입하여 형성한다. 상기에서 LDD영역(51)은 단 채널 효과를 방지하고, 포켓영역(53)은 LDD영역(51)과의 도핑 농도 차이를 증가시켜 프로그램시 핫 캐리어(hot carrier)의 발생을 용이하게하여 프로그램 효율을 증가시킨다.Referring to FIG. 2D, the photoresist 43 is removed. The photoresist 49 is applied to the entire surface of the structure described above, followed by exposure and development to expose the drain portion. Then, the photoresist 49 is used as a mask and doped with N-type impurities such as an asic (As) or phosphorus (P) at a low concentration to form a P-type such as an LDD region 51 and boron (B) or BF 2 . The dopant is doped at a low concentration to partially overlap the lower portion of the floating gate 37 to form the pocket region 53. In the above, the LDD region 51 is formed by ion implanting N-type impurities such as acene (As) or phosphorus (P) with a dose of about 1 × 10 12 to 1 × 10 14 / cm 2 and forming a pocket region ( 53) is formed by ion implantation of P-type impurities such as boron (B) or BF 2 with a dose of about 1 × 10 12 to 1 × 10 14 / cm 2 at an inclination angle of about 30 to 60 °. The LDD region 51 prevents short channel effects, and the pocket region 53 increases the doping concentration difference with the LDD region 51 to facilitate the generation of hot carriers during programming, thereby increasing program efficiency. To increase.
도 2e를 참조하면, 부유게이트(37) 및 제어게이트(41)의 측면에 산화실리콘 또는 질화실리콘으로 이루어진 측벽(55)을 형성한다. 상기에서 측벽(55)은 상술한 구조의 전 표면에 산화실리콘 또는 질화실리콘을 CVD 방법으로 1000∼3000Å 정도 두께로 증착한 후 반도체기판(31)이 노출되도록 반응성이온식각(Reactive Ion Etching) 방법 또는 플라즈마식각 방법으로 에치백하므로써 형성된다.Referring to FIG. 2E, sidewalls 55 made of silicon oxide or silicon nitride are formed on the side surfaces of the floating gate 37 and the control gate 41. In the above-described sidewall 55, the silicon oxide or silicon nitride is deposited on the entire surface of the structure described above by a CVD method at a thickness of about 1000 to 3000Å, and then the reactive ion etching method is performed so that the semiconductor substrate 31 is exposed. It is formed by etching back by plasma etching method.
반도체기판(31)의 드레인 부분을 노출시키는 포토레지스트(57)을 형성하고, 이 포토레지스트(57)를 마스크로 사용하여 아세닉(As) 또는 인(P) 등의 N형의 불순물을 1 × 1014∼ 5 × 1015／㎠ 정도의 도우즈로 이온 주입하므로써 형성된다.A photoresist 57 is formed to expose the drain portion of the semiconductor substrate 31. The photoresist 57 is used as a mask to form an N-type impurity such as an asic (As) or phosphorus (P). It is formed by ion implantation with a dose of about 10 14 to 5 x 10 15 / cm 2.
상술한 바와 같이 본 발명에 따른 반도체기판의 드레인에 아세닉(As) 또는 인(P) 등의 N형의 불순물을 저농도로 이온 주입하여 LDD영역를 형성하고 보론(B) 또는 BF2등의 P형 불순물을 저농도로 30 ∼ 60°정도의 경사각도로 이온 주입하여 부유게이트 하부에 소정 부분 중첩되게 포켓영역을 형성한다.As described above, the LDD region is formed by ion implantation of N-type impurities such as asic (As) or phosphorus (P) at low concentration into the drain of the semiconductor substrate according to the present invention, and the P-type such as boron (B) or BF 2 Impurities are implanted at low concentrations at an inclination angle of about 30 to 60 degrees to form pocket regions overlapping a predetermined portion under the floating gate.
따라서, 본 발명은 LDD영역에 의해 단 채널 효과를 방지하며, 또한, 포켓영역에 의해 LDD영역과 접합에 의해 프로그램시 핫 캐리어(hot carrier)의 발생을 용이하게하여 프로그램 효율을 증가시킬 수 있는 잇점이 있다.Accordingly, the present invention prevents short channel effects by the LDD region, and also facilitates generation of hot carriers during programming by bonding with the LDD region by the pocket region, thereby increasing program efficiency. There is this.
Claims (5)
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| KR1019970072224A KR19990052693A (en) | 1997-12-23 | 1997-12-23 | Manufacturing Method of Flash Memory Cell |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100547050B1 (en) * | 2000-08-15 | 2006-02-01 | 가부시키가이샤 히타치세이사쿠쇼 | A semiconductor integrated circuit device and a method of manufacturing the same |
| KR100668752B1 (en) * | 2005-09-21 | 2007-01-29 | 주식회사 하이닉스반도체 | Method of manufacturing the semiconductor memory device using asymmetric junction ion implantation |
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1997
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100547050B1 (en) * | 2000-08-15 | 2006-02-01 | 가부시키가이샤 히타치세이사쿠쇼 | A semiconductor integrated circuit device and a method of manufacturing the same |
| KR100668752B1 (en) * | 2005-09-21 | 2007-01-29 | 주식회사 하이닉스반도체 | Method of manufacturing the semiconductor memory device using asymmetric junction ion implantation |
| US7687350B2 (en) | 2005-09-21 | 2010-03-30 | Hynix Semiconductor Inc. | Method for manufacturing semiconductor memory device using asymmetric junction ion implantation |
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