KR19990051741A - Metal wiring formation method of semiconductor device using copper thin film - Google Patents
Metal wiring formation method of semiconductor device using copper thin film Download PDFInfo
- Publication number
- KR19990051741A KR19990051741A KR1019970071109A KR19970071109A KR19990051741A KR 19990051741 A KR19990051741 A KR 19990051741A KR 1019970071109 A KR1019970071109 A KR 1019970071109A KR 19970071109 A KR19970071109 A KR 19970071109A KR 19990051741 A KR19990051741 A KR 19990051741A
- Authority
- KR
- South Korea
- Prior art keywords
- thin film
- copper thin
- semiconductor device
- forming
- diffusion
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 구리 박막을 이용한 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 급속열변환에 의한 확산방지막의 형성에 의해 젖음 특성을 확보하고, 금속 배선용 구리 증착 및 급속열처리에 의한 흐름 공정으로 표면의 산화막 형성을 최소화하여 표면 확산과 체 확산 특성을 개선시켜 구리 박막의 미세 홀 특성을 개선하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device using a copper thin film. In particular, the wettability is ensured by the formation of a diffusion barrier film by rapid thermal conversion. The present invention relates to a method of improving fine hole characteristics of a copper thin film by minimizing oxide formation to improve surface diffusion and body diffusion characteristics.
본 발명에서는 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판 상부에 층간절연막을 형성한 후, 선택된 영역에 콘택 홀 또는 비아 홀을 형성하고 표면의 산화물 및 불순물 제거하여 내화금속층을 얇은 두께로 증착한다. 이어 암모니아 분위기에서의 급속열변환 공정으로 내화금속의 질화물을 형성하거나, 실리콘의 외향확산에 의해 삼원계화합물을 형성하여 확산방지막을 형성한다. 이후 공정으로 유기화학 증착법 또는 스퍼터에 의해 확산방지막의 상부에 구리 박막을 증착하고, 미세 홀의 상부에 증착된 구리 박막을 급속열처리하여 표면확산과 체 확산을 촉진시켜 미세 홀 내부로 구리를 채워 넣어 금속 배선을 형성한다.In the present invention, after forming an interlayer insulating film on the substrate on which various elements for forming a semiconductor device are formed, a contact hole or a via hole is formed in a selected region, and oxides and impurities on the surface are removed to deposit a refractory metal layer in a thin thickness. Next, a nitride of refractory metal is formed by a rapid thermal conversion process in an ammonia atmosphere, or a ternary compound is formed by outward diffusion of silicon to form a diffusion barrier. Subsequently, a copper thin film is deposited on the diffusion barrier by organic chemical vapor deposition or sputtering, and the copper thin film deposited on the upper surface of the micro holes is rapidly thermally treated to promote surface diffusion and sieve diffusion to fill copper into the micro holes. Form the wiring.
Description
본 발명은 구리(Cu) 박막을 이용한 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 급속열변환에 의한 확산방지막의 형성에 의해 젖음 특성을 확보하고, 금속 배선용 구리 증착 및 급속열처리에 의한 흐름(reflow) 공정으로 표면의 산화막 형성을 최소화하여 표면 확산과 체 확산 특성을 개선시켜 구리 박막의 미세 홀 특성을 개선하는 방법에 관한 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device using a copper (Cu) thin film, in particular to ensure the wettability by forming a diffusion barrier film by rapid thermal conversion, and to the flow of copper wiring and rapid heat treatment for metal wiring ( The present invention relates to a method of improving the fine hole characteristics of a copper thin film by minimizing the formation of an oxide film on the surface by improving the surface diffusion and the body diffusion characteristics.
반도체 소자의 집적도 증가와 미세화에 따라 알루미늄(Al) 배선의 높은 비저항에 의한 신호 전달 지연 및 전자 이주 특성 열화 등에 의해 구리 박막이 그 대체 물질로 대두되고 있다. 구리의 증착 기술로는 유기금속증착법(MOCVD), 스퍼터 (sputter) 및 전착법(electroplating) 등이 제시되고 있으나, 구리 배선 공정의 실용화를 위해서는 비저항의 감소와 더불어 결정립 크기(grain size)의 조절에 의하여 높은 종횡비(aspect ratio)의 콘택 홀(contact hole) 및 비아 홀(via hole)을 매립할 수 있어야 한다. 이를 위해 현재 거론되고 있는 기술로는 유기금속증착법에 의한 구리 박막의 증착 또는 스퍼터를 이용하여 증착된 구리 박막을 흐름(reflow) 처리 시키는 방법 등이 있다.As the integration density of semiconductor devices increases and becomes smaller, copper thin films are emerging as substitute materials due to signal transmission delay and deterioration of electron migration characteristics due to high resistivity of aluminum (Al) wiring. As the deposition technique for copper, organic metal deposition (MOCVD), sputtering, and electroplating have been proposed, but for the practical use of the copper wiring process, it is necessary to control grain size and control grain size. It should be possible to fill in high aspect ratio contact holes and via holes. To this end, technologies currently being discussed include a method of depositing a copper thin film by an organometallic deposition method or a method of reflowing a deposited copper thin film using a sputter.
그러나, 실제 공정 수행에서 전구체(precursor)를 사용하는 유기금속증착법에 의한 증착의 경우 열화학 공정의 장점인 우수한 스텝커버리지(step-coverage) 특성을 나타내지 못하고 있는데, 이는 결정립 크기의 제어를 위한 공정 조건의 설정이 매우 어렵기 때문이다. 종래의 구리 증착 공정의 경우, 홀 내부에 증착된 구리는 미세 홀 직경의 1/2 내지 1/3 크기 정도인 매우 큰 알갱이 형태로 이루어져 초기에 안정된 구조를 형성한다. 따라서 후 열처리 공정을 진행하여도 표면 확산(surface diffusion) 및 체 확산(bulk diffusion)에 의한 매립이 거의 불가능하다. 유기금속증착법에 의한 경우, 박막의 밀도와 비저항 등의 개선을 위해서는 후 열처리가 필수적으로 요구된다. 스퍼터에 의한 증착의 경우는, 근본적으로 미세 홀 매립 특성이 유기금속증착법에 비해 뒤지고 있어, 후 열처리에 의한 홀 매움 공정이 필수적이다. 이를 위해서 하부의 확산방지막(barrier metal)은 고유한 특성인 확산방지 특성과 더불어 구리의 흐름(flow)을 양호하게 하기 위한 젖음 특성이 우수하여야 하고, 젖음층의 종류와 두께에 따라 홀매립 특성이 크게 변하는 등의 단점이 있다.However, the deposition by the organometallic deposition method using the precursor in the actual process performance does not show the excellent step-coverage characteristics, which is an advantage of the thermochemical process, which is a process condition for controlling the grain size. This is because the setting is very difficult. In the conventional copper deposition process, the copper deposited inside the hole is in the form of very large grains that are about 1/2 to 1/3 the size of the fine hole diameter to form an initially stable structure. Therefore, even after the post-heat treatment process, it is almost impossible to bury the surface by surface diffusion and bulk diffusion. In the case of the organometallic deposition method, post-heat treatment is essentially required to improve the density and specific resistance of the thin film. In the case of vapor deposition by sputtering, the fundamental hole filling property is inferior to that of the organometallic deposition method, and thus the hole filling process by post-heat treatment is essential. To this end, the lower barrier metal must have excellent wetting characteristics to improve the flow of copper, as well as unique diffusion prevention characteristics, and hole-filling characteristics depending on the type and thickness of the wet layer. There are disadvantages such as large changes.
일반적으로 내화금속 계열의 젖음 특성은 순수한 내화금속이 가장 우수하고, 그 다음이 내화금속의 질화물, 그리고 내화금속의 산화물이 가장 나쁜 특성을 갖는 것으로 보고되고 있다. 따라서, 흐름(reflow) 특성을 좋게 하기 위해서는 표면에서의 확산방지막의 산화물 형성을 최대한 억제하여야 한다.In general, the wettability characteristics of the refractory metal series are reported to have the best properties of pure refractory metals, followed by nitrides of refractory metals and oxides of refractory metals. Therefore, in order to improve the reflow characteristic, the oxide formation of the diffusion barrier film on the surface should be suppressed as much as possible.
본 발명은 위와 같은 문제점을 해결하여 금속 배선층으로 구리 박막을 사용할 수 있도록 하는데 그 목적이 있다.The present invention has been made to solve the above problems and to use a copper thin film as the metal wiring layer.
상술한 목적을 달성하기 위한 본 발명에 따른 구리 박막을 이용한 반도체 소자의 금속 배선 형성 방법은, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판 상부에 층간절연막을 형성한 후, 선택된 영역에 콘택 홀을 형성하는 단계와, 상기 콘택 홀이 형성된 전체 구조 표면의 산화물 및 불순물 세정 공정으로 제거하고 내화금속층을 증착하는 단계와, 암모니아 가스 분위기에서의 급속열변환 공정으로 상기 내화금속층을 질화처리 하여 확산 방지막을 형성하는 단계와, 상기 확산방지막의 상부에 금속 배선용 구리 박막을 증착하고, 급속열처리에 의한 흐름 공정을 진행하여 상기 콘택 홀 내부에 양호한 층덮힘으로 상기 구리 박막이 채워지도록 하는 단계를 포함하여 이루어 지는 것을 특징으로 한다.In the method of forming a metal wiring of a semiconductor device using a copper thin film according to the present invention for achieving the above object, after forming an interlayer insulating film on the substrate formed with a number of elements for forming a semiconductor device, a contact hole is formed in a selected region Forming a layer, removing the oxide and impurity on the entire structure surface of the contact hole, and depositing a refractory metal layer; and nitriding the refractory metal layer by a rapid thermal conversion process in an ammonia gas atmosphere to form a diffusion barrier layer. And forming a copper thin film for metal wiring on top of the diffusion barrier layer and performing a flow process by rapid heat treatment to fill the copper thin film with a good layer covering in the contact hole. It is characterized by.
도 1은 본 발명에 따른 구리 박막을 이용한 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 도시한 단면도.1 is a cross-sectional view for explaining a metal wiring forming method of a semiconductor device using a copper thin film according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 층간 절연막11 semiconductor substrate 12 interlayer insulating film
13A : 내화 금속층 13B : 내화 금속의 질화물13A: refractory metal layer 13B: nitride of refractory metal
14 : 구리 박막14: copper thin film
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1은 본 발명에 따른 구리 박막을 이용한 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 도시한 단면도이다.1 is a cross-sectional view illustrating a metal wiring forming method of a semiconductor device using a copper thin film according to the present invention.
도 1(a)는 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(11) 상부에 층간 절연막(12)을 형성하고, 선택된 영역에 형성된 콘택 홀 또는 비아 홀에 내화 금속층(13A)을 증착한 단면도이다. 내화금속층(13A)은 타이타늄(Ti), 탄탈륨(Ta) 또는 텅스텐(W) 등을 이용하여 200 Å 이하의 얇은 두께로 증착한다. 이 때 내화금속층 증착 전에 플라즈마 소프트 세정(plasma soft clean) 공정을 수 Torr 수준의 압력에서 수행하여 반도체 기판(11)의 불순물 및 산화물을 제거한다.FIG. 1A is a cross-sectional view of forming an interlayer insulating film 12 on a substrate 11 having various elements for forming a semiconductor device and depositing a refractory metal layer 13A in a contact hole or a via hole formed in a selected region. to be. The refractory metal layer 13A is deposited with a thin thickness of 200 mW or less using titanium (Ti), tantalum (Ta), or tungsten (W). At this time, before the refractory metal layer is deposited, a plasma soft clean process is performed at a pressure of several Torr to remove impurities and oxides from the semiconductor substrate 11.
도 1(b)는 급속열변환에 의해 내화금속층을 질화 처리한 단면도이다. 따라서 내화금속층(13A)은 내화금속의 질화물(13B), 즉 타이타늄나이트라이드(TiN), 탄탈륨나이트라이드(TaN) 또는 텅스텐나이트라이드(WN) 등으로 형성된다. 경우에 따라 반도체 기판(11)에 포함된 실리콘(Si)의 외향 확산에 의해 삼원계 화합물 즉, Ti-Si-N, Ta-Si-N 또는 W-Si-N 등으로 형성될 수도 있다. 이 때 질화 공정은 400 ℃ 내지 700 ℃ 온도 범위의 순수한 암모니아 가스 분위기에서 60초 내지 90초 정도인 매우 짧은 시간 동안 수행하여 산화막 형성이 최소화되도록 한다. 이렇게 함으로써 확산방지 특성의 열화와 더불어 젖음 특성을 완벽하게 확보 할 수 있다.1B is a cross-sectional view of nitriding a refractory metal layer by rapid thermal conversion. Accordingly, the refractory metal layer 13A is formed of a nitride metal 13B, that is, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or the like. In some cases, it may be formed of a ternary compound, that is, Ti-Si-N, Ta-Si-N, W-Si-N, or the like by outward diffusion of silicon (Si) included in the semiconductor substrate 11. In this case, the nitriding process is performed in a pure ammonia gas atmosphere in a temperature range of 400 ° C. to 700 ° C. for a very short time of about 60 seconds to 90 seconds to minimize oxide film formation. By doing so, it is possible to fully secure the wettability with deterioration of the diffusion prevention property.
도 1(c)는 금속 배선 구리 박막(14)을 증착한 단면도로써 층덮힘이 열악한 것을 알 수 있다.FIG. 1 (c) is a cross-sectional view of the metal wiring copper thin film 14 deposited with poor layer covering.
이후 공정으로 도 1(d)에 도시된 것과 같이, 미세 홀의 상부에 증착된 구리 박막(14)을 급속 열처리하여 표면확산 및 체 확산을 유발시켜 미세 홀 내부로 구리가 채워지도록 한다. 이 공정은 아르곤(Ar) 가스 분위기 진행되며, 표면 반응의 촉진을 위해 수소 가스를 사용하거나, 일부 산소가 혼합된 산화성 가스 및 불활성 가스를 사용한다. 열처리 온도와 시간은 하부 확산방지막의 파괴가 일어나지 않고, 증착된 구리 박막(14)의 특성을 개선 시킬 수 있는 범위 내에서 결정되어야 하는데, 불필요한 표면산화를 막기 위해 가능한 짧은 시간 수행 한다. 구리의 확산계수는 온도에 따라 지수함수적으로 증가하고, 불순물의 유입에 의해서는 급격히 감소하기 때문에, 흐름의 재현성과 균일도는 확산방지막에의 불순물 흡착과 기판(11) 온도의 균일도에 의해 결정된다. 특히 기판(11) 및 반응로로 부터의 탈가스(outgassing)는 구리박막(14) 표면을 오염시키고, 이러한 불순물들이 표면에서의 구리 원자의 자기확산을 방해하여 구리 박막의 홀 매립을 방해하게 된다. 또한, 진공의 파괴(break)에 의하여 대기에 한번 노출된 구리의 경우, 표면에 구리 산화막이 형성되므로 흐름를 일으키지 못하여 홀 매립을 이룰 수 없다. 따라서 구리 표면층의 불순물 흡착 (impurity adsorption)을 최소화하기 위해 500 ℃ 내지 700 ℃ 온도 범위에서 30초 내지 60초 동안 급속 열처리를 수행하여 도 1(e)에 도시된 것과 같이 구리 박막을 이용한 금속 배선을 형성할 수 있게 된다.Subsequently, as shown in FIG. 1 (d), the copper thin film 14 deposited on the upper portion of the fine hole is rapidly heat treated to cause surface diffusion and sieve diffusion so that the copper is filled into the fine hole. This process is carried out in an argon (Ar) gas atmosphere, using hydrogen gas to promote the surface reaction, or using an oxidizing gas and an inert gas mixed with some oxygen. The heat treatment temperature and time should be determined within a range that can improve the properties of the deposited copper thin film 14 without destroying the lower diffusion barrier, and is performed in the shortest possible time to prevent unnecessary surface oxidation. Since the diffusion coefficient of copper increases exponentially with temperature and decreases rapidly due to the inflow of impurities, the reproducibility and uniformity of the flow is determined by the adsorption of impurities to the diffusion barrier and the uniformity of the temperature of the substrate 11. . In particular, outgassing from the substrate 11 and the reactor contaminates the surface of the copper thin film 14, and these impurities interfere with the self-diffusion of copper atoms on the surface, thereby preventing the hole filling of the copper thin film. . In addition, in the case of copper exposed to the atmosphere once by the break of vacuum, a copper oxide film is formed on the surface, so that flow cannot be generated and hole filling cannot be achieved. Therefore, in order to minimize impurity adsorption of the copper surface layer, a rapid heat treatment is performed for 30 seconds to 60 seconds at a temperature range of 500 ° C. to 700 ° C. to form a metal wiring using a copper thin film as shown in FIG. 1 (e). It can be formed.
이와 같이 표면의 산화막 형성을 근본적으로 방지 할 수 있는 열변환 확산방지막의 형성, 진공이 계속 유지되는 일관 공정에 의한 구리 박막(14)의 증착 및 짧은 시간의 급속열처리 흐름에 의해 홀 매립을 효율적으로 구현할 수 있다.In this way, the hole filling is efficiently performed by the formation of the thermal conversion diffusion barrier film which can fundamentally prevent the formation of the oxide film on the surface, the deposition of the copper thin film 14 by the consistent process of maintaining the vacuum, and the rapid heat treatment flow in a short time. Can be implemented.
상술한 바와 같이 본 발명에 의하면, 상부에 산화막의 형성을 완벽하게 막을 수 있는 열변환 확산방지막을 형성하여, 젖음 특성을 확보하고 구리 박막을 증착한 후, 측면을 통한 흐름(flow)을 유발시켜, 안정된 구조의 큰 알갱이 형태로 미세 홀을 매립한다. 따라서, 종래 기술의 문제점인, 후 열처리에 의해서도 입자들의 결합이나 확산에 의한 매립이 불가능한 점 및 상부 입구에서의 오버행(overhang)에 의해 미세홀이 전혀 채워지지 않는 현상 등을 극복 할 수 있다. 또한 구리 박막의 증착과 흐름 공정을 다중반응로의 일관 공정으로 수행하여 구리 산화막의 형성을 근원적으로 막아 표면확산을 극대화 하고, 내부에 기공(void)을 형성하지 않으면서 미세 홀의 바닥에까지 구리를 완벽하게 채울 수 있다. 그러므로 표면확산 효과의 증대에 의해 젖음 특성의 부족을 상쇄시킬 수 있고, 젖음층의 종류와 두께에 따른 구리의 젖음 특성 변화에 무관하게 홀 매립을 효율적으로 수행할 수 있는 탁월한 효과가 있다.As described above, according to the present invention, by forming a thermal conversion diffusion barrier that can completely prevent the formation of the oxide film on the top, to ensure the wettability and to deposit a copper thin film, to cause the flow (flow) through the side The fine holes are buried in the form of large grains of stable structure. Therefore, it is possible to overcome the problems of the prior art, which is impossible to bury by bonding or diffusion of particles even after the post-heat treatment, and the phenomenon that the microholes are not filled at all due to overhang at the upper inlet. In addition, the deposition and flow process of the copper thin film is carried out in a consistent process of multiple reactors to fundamentally prevent the formation of a copper oxide film to maximize surface diffusion and perfect copper to the bottom of the fine holes without forming voids therein. Can be filled. Therefore, it is possible to offset the lack of the wettability by increasing the surface diffusion effect, and there is an excellent effect that can effectively fill the hole irrespective of the change in the wettability characteristics of copper according to the type and thickness of the wetted layer.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970071109A KR100250455B1 (en) | 1997-12-19 | 1997-12-19 | Method of manufacturing metal line of semiconductor device using copper thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970071109A KR100250455B1 (en) | 1997-12-19 | 1997-12-19 | Method of manufacturing metal line of semiconductor device using copper thin film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990051741A true KR19990051741A (en) | 1999-07-05 |
| KR100250455B1 KR100250455B1 (en) | 2000-05-01 |
Family
ID=19527958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970071109A KR100250455B1 (en) | 1997-12-19 | 1997-12-19 | Method of manufacturing metal line of semiconductor device using copper thin film |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100250455B1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100407682B1 (en) * | 2000-06-26 | 2003-12-01 | 주식회사 하이닉스반도체 | A method of forming a metal line in a semiconductor device |
| KR100454257B1 (en) * | 2001-06-30 | 2004-10-26 | 주식회사 하이닉스반도체 | A method for forming damascene metal wire using copper |
| KR100587054B1 (en) * | 2002-07-19 | 2006-06-07 | 주식회사 하이닉스반도체 | Method for via filling in semiconductor device |
-
1997
- 1997-12-19 KR KR1019970071109A patent/KR100250455B1/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100407682B1 (en) * | 2000-06-26 | 2003-12-01 | 주식회사 하이닉스반도체 | A method of forming a metal line in a semiconductor device |
| KR100454257B1 (en) * | 2001-06-30 | 2004-10-26 | 주식회사 하이닉스반도체 | A method for forming damascene metal wire using copper |
| KR100587054B1 (en) * | 2002-07-19 | 2006-06-07 | 주식회사 하이닉스반도체 | Method for via filling in semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100250455B1 (en) | 2000-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5527739A (en) | Process for fabricating a semiconductor device having an improved metal interconnect structure | |
| US6955983B2 (en) | Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer | |
| US6541374B1 (en) | Method of depositing a diffusion barrier for copper interconnection applications | |
| JP4180145B2 (en) | Semiconductor device formation method | |
| US6391769B1 (en) | Method for forming metal interconnection in semiconductor device and interconnection structure fabricated thereby | |
| US6150270A (en) | Method for forming barrier layer for copper metallization | |
| US9343402B2 (en) | Semiconductor device having Ti- and N-containing layer, and manufacturing method of same | |
| US6602782B2 (en) | Methods for forming metal wiring layers and metal interconnects and metal interconnects formed thereby | |
| KR100455382B1 (en) | Method for forming metal interconnections of semiconductor device having dual damascene structure | |
| KR100396891B1 (en) | Method for forming metal wiring layer | |
| KR100489920B1 (en) | In-situ capped aluminum plug (cap) process using selective cvd al for integrated plug/interconnect metallization | |
| KR20020072875A (en) | Method for forming metal wiring layer | |
| US6069072A (en) | CVD tin barrier layer for reduced electromigration of aluminum plugs | |
| KR20010001543A (en) | Method of Fabricating Semiconductor Device Employing Copper Interconnect Structure | |
| KR100543458B1 (en) | Method Of Forming Conductive Structure of Semiconductor Device | |
| US7846839B2 (en) | Film forming method, semiconductor device manufacturing method, semiconductor device, program and recording medium | |
| KR100250455B1 (en) | Method of manufacturing metal line of semiconductor device using copper thin film | |
| US6852624B2 (en) | Electroless plating process, and embedded wire and forming process thereof | |
| KR101628843B1 (en) | Method for forming ruthenium containing thin film by atomic layer deposition | |
| KR100289515B1 (en) | Barrier emtal layer and method of forming the same | |
| US20030214039A1 (en) | Method for fabricating semiconductor device having tertiary diffusion barrier layer for copper line | |
| KR100753120B1 (en) | Method for forming teneray diffusion barrier in copper itnerconnection | |
| KR100215540B1 (en) | Method for forming metal film in semiconductor device | |
| KR100352661B1 (en) | A precleaning method for the enhancement of the deposition rate of the copper film for wiring of elemental semiconductor devices | |
| KR20000045863A (en) | Method for forming multilayer copper interconnect of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20080103 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |