KR19990049365A - Semiconductor memory device for direct access mode test and its test method - Google Patents

Abstract

The semiconductor memory device for direct access mode test according to the present invention inputs N bits of data applied from an external tester through a data input / output terminal, and converts the input N bits of data into M (> N) bits of data. Data expansion means for extending and outputting, data selection means for selectively outputting M-bit data output from the data expansion means in response to the test mode signal and M-bit data output from a predetermined input pipeline, from an external tester A write data storage means for latching the input N-bit data, a memory core for storing M-bit data output from the data expansion means or M-bit data output from the input pipeline, or outputting the stored data; Converts M-bit data stored to serial data and outputs the converted data N-bit data latched in the output pipeline, the comparison means for comparing the multiple bits of data output from the multiple output pipelines, and outputting the compared result as the first comparison signal and the second comparison signal, and the write data latching means. Is converted to serial data in response to the test read enable signal, and a latch output pipeline for outputting the converted data as serial latch data, and a logical combination of the first and second comparison signals and the serial latch data, and a logical combination. And error discriminating means for outputting the result as an error discriminating signal.

Description

Semiconductor memory device for direct access mode test and its test method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device for a direct access (DA) mode test in which direct data is written and read from a semiconductor memory in an external test equipment.

In general, the devices used to test semiconductor memory devices such as DRAMs all have a limit on the number of input / output pins regardless of the test state. Therefore, reducing the number of pins used in the test not only reduces the test time spent on the test, but also becomes an important factor in determining whether the test is possible. For the reasons mentioned above, it is possible to use a limited input / output pin such as a parallel bit test (PBT) or a merged DQ (Merged DQ) method in which a plurality of output data are merged into a small group and compared. Efforts have been made to perform the test. The same applies to the case of high speed RAMBUS DRAM (RDRAM).

FIG. 1 is a schematic block diagram illustrating a data write block of a semiconductor memory device for a conventional DA mode test, and includes a multiplexer 110, input pipelines 120, and a data expander 130. .

The semiconductor memory device shown in FIG. 1 inputs four bits of data through four data input / output terminals DQ1, DQ2, DQ3, and DQ4, respectively, and the input data is repeated and expanded by the data expansion unit 130. Generated as bits of data. That is, the generated 8-bit data is applied to the second input of the multiplexers 110, and the 8-bit data output from the input pipeline 120 is applied to the first input of the multiplexer 120. Therefore, the multiplexer 110 selectively outputs 8-bit data of the input pipeline 120 or 8-bit data of the data extension 130 in response to the test mode signal TEST_MODE which is a selection signal. That is, when the test mode signal TEST_MODE is enabled, a second input of two inputs of the multiplexer 110 is selected and applied as the write data WDA0 to WDA7 and WDB0 to WDB7 of the RAM core 15. Therefore, the same data is written to all the RAM core cells of the address.

FIG. 2 is a schematic block diagram illustrating a data reading block of a semiconductor memory device for a conventional DA mode test, and includes 16 output pipelines 140 and comparison units 220a to 220d.

The data written to the DRAM in the block shown in FIG. 1 is read from the data read block of FIG. 2 and compared with each other to test for an error. That is, each parallel 8-bit read data RDA0 to RDA7 and RDB0 to RDB7 stored in the RAM core 15 are converted into serial data in the output pipelines 140. The converted serial data is applied in combination with four or five comparison units 150a to 150d, and it is assumed that four comparison units are shown in the block diagram shown in FIG. That is, the first to fourth comparison units 150a to 150d compare the input data, and compare the result with the pass / fail information P / F and the high / low information through the data input / output terminals DQ1 to DQ8. Output as (H / L). Here, if the data inputted to the comparator 150a to 150d are all logic '1', the high / low information (H / L) is at a high level, and if the data of each 1 bit input is the same, pass / fail information. (P / F) becomes the high level. Therefore, by simultaneously determining such pass / fail information (P / F) and high / low information (H / L), it is possible to determine whether there is a defect in a cell of the semiconductor memory device.

However, in the conventional semiconductor memory device, four output pins are additionally required to obtain high / low level information (H / L) during the DA mode test, which may cause problems in terms of efficient use of test equipment. have. However, if this is ignored, the pass / fail information (P / F) is not reliable, so there is a problem in that an accurate test cannot be performed.

An object of the present invention is to provide a semiconductor memory device for a DA mode test that can reduce the number of pins required in the direct access mode test of a semiconductor memory using the merge DQ method.

Another object of the present invention is to provide a DA mode test method performed in the semiconductor memory device.

1 is a schematic block diagram illustrating a data write block of a semiconductor memory device for a conventional direct access mode test.

2 is a schematic block diagram illustrating a data read block of a semiconductor memory device for a conventional direct access mode test.

3 is a block diagram of a preferred embodiment for explaining a data write block of a semiconductor memory device for a direct access mode test according to the present invention.

4 is a block diagram of a preferred embodiment for explaining a data read block of a semiconductor memory test apparatus for a direct access mode test according to the present invention.

5A to 5K are waveform diagrams for explaining respective signals of the semiconductor memory device shown in FIGS. 3 and 4.

FIG. 6 is a flowchart for describing a direct access mode test method performed in the semiconductor memory device illustrated in FIGS. 3 and 4.

In order to achieve the above object, in the semiconductor memory device for direct access mode test according to the present invention, the N-bit data applied from the external tester is input through the data input / output terminal, and the input N-bit data is M (> Data expansion means for extending and outputting N) bits of data, Selecting data for selectively outputting M bits of data output from the data expansion means and M bits of data output in a predetermined input pipeline in response to the test mode signal Means, for storing write data for latching N bits of data input from an external tester, for storing M bits of data output from the data expansion means or M bits of data output from the input pipeline, or for outputting stored data. Memory core, M-bit data stored in the memory core is converted into serial data, and A plurality of output pipelines for outputting data, a comparison means for comparing a plurality of bits of data output from the plurality of output pipelines, and outputting the compared result as a first comparison signal and a second comparison signal, and a write data latching means. A latch output pipeline for converting the latched N bits of data into serial data in response to the test read enable signal, and outputting the converted data as serial latch data, and logic first and second comparison signals and serial latch data. And error discriminating means for outputting the logically combined result as an error discriminating signal.

According to another aspect of the present invention, a method of testing a semiconductor memory device for a direct access mode test may include determining whether a test write enable signal is activated, and when the test write enable signal is activated, an external tester Latching N bits of data applied from the memory core and writing the data into a cell at the corresponding address of the memory core; (a) determining whether the test read enable signal is activated; and if the test read enable signal is activated, Outputting the written data and the latched data, precharging if the test read enable signal is not active, (b) determining whether the data written to the memory core and the latched data are the same; If the latched data and the latched data are the same, it is determined that there is no defect. Step, and the written data and the latched data are different, and are preferably composed of a step of determining as defective.

Hereinafter, a configuration and an operation of a semiconductor memory device for a direct access mode test according to the present invention will be described with reference to the accompanying drawings.

3 is a schematic block diagram illustrating a data write block of a semiconductor memory device for a DA mode test according to the present invention.

Referring to FIG. 3, the semiconductor memory device 30 for the DA mode test may include a RAM core 35, multiplexers 310, input pipelines 320, a write data storage unit 330, and a data expansion unit ( 380, where the write data storage 330 consists of a latch 332 and a multiplexer 334.

The semiconductor memory device for the direct access mode test illustrated in FIG. 3 may have N input / output terminals, that is, DQ pins. In the example illustrated in FIG. 3, four DQ pins among the N DQ terminals may be used as input / output terminals of the test. I use it. In the embodiment shown in Fig. 3, 4-bit data is input through each of the data input / output terminals DQ1, DQ2, DQ3, and DQ4. However, according to the design method of the semiconductor memory device, the DQ pin and the input data bit may be variously implemented. The 4-bit data input through the input / output terminals DQ1 to DQ4 are repeated and extended by the data mixing unit 380 to generate 8-bit data, and the generated 8-bit data are respectively input to the second inputs of the multiplexers 310. Is applied. As the first input of the multiplexer 310, 8-bit data output from the input pipeline 320 used in the normal operation mode is applied, and the first input and the second input are in response to the test mode signal TEST_MODE, which is a selection signal. Data of two inputs is output selectively. When the 8-bit data output at this time are called WDA0 to WDA7 and WDB0 to WDB7, the parallel data of each 8-bit is written to the corresponding address of the RAM core 35. At this time, each cell of the RAM core 35 of the corresponding AD writes the same data. In addition, the write data storage unit 330 responds to the test write enable signal TESTWRITE and the test column address strobe signal TESTCABS for four bits of data input through the four data input / output terminals DQ1, DQ2, DQ3, and DQ4. To latch. The latched data is output during the read data test of the RAM core 35 to detect whether a defect FAULT, that is, an error occurs.

That is, the multiplexer 334 of the write data storage unit 330 is connected to the output of the latch 332 for inputting the output of the multiplexer 330 as the first input and the 4-bit test data applied from the outside. It has two inputs and selectively outputs first and second inputs in response to the test write enable signal TWRITE, which is a selection signal. The output data is applied to the input of the latch 332 and latched in response to the clock column address strobe signal TESTCASB that is clocked in. At this time, the latched data is compared with the data stored in the RAM core 35 and used when detecting the presence of a defect.

4 is a block diagram of a preferred embodiment for explaining a data reading block of a semiconductor memory device for a DA mode test according to the present invention.

Referring to FIG. 4, the data read block of the semiconductor memory device for the DA mode test includes a plurality of output pipelines 340, comparison units 350a to 350d, error discriminating units 360a to 360d, and write data storage units. 330 and latch output pipeline 370. Here, the error determining unit 360 includes an exclusive NOR gate 362 and an AND gate 364.

The data read block shown in FIG. 4 is implemented in one semiconductor memory device such as the data write block shown in FIG. 3, and is shown separately from the data write block of FIG. 3 for simplicity. The semiconductor memory device having the DA mode test function according to the present invention reads the data written in the RAM core 35 shown in FIG. 3 with an external tester (not shown), and compares the read data with each other. It is detected whether an error exists in the cell of 35), and the detected result is output through the data input / output terminals DQ1, DQ2, DQ3, and DQ4.

That is, the output pipeline 340 shown in FIG. 4 inputs the 8-bit data RDA0 to RDA7 and RDB0 to RB7 outputted through 16 paths from the corresponding address of the RAM core 35 and receives serial data. Then, the converted 1-bit data is formed into a small number of groups and divided into first to fourth comparison units 350a to 350d. That is, the comparison units 350a to 350d compare the input data of each of four bits, and output the comparison result as the first comparison signal S / D and the second comparison signal H / L. The first to fourth error determination units 360 logically combine the first and second comparison signals output from the comparator 350 and the one-bit data output from the latch output pipeline 370, and perform a logical combination. The result is output as an error discrimination result (P / F). The latch output pipeline 370 converts the 4-bit parallel data stored in the write data storage unit 330 in series in response to the second test clock signal TESTCLK2 and converts the converted 1-bit signal. Output is as serial latch data WD_S. As described above, the error discrimination unit 360 includes an exclusive OR gate 362 and an AND gate 364 to exclusively store the serial latch data WD_S and the high / low information H / L which is the second comparison signal. The result is OR and the result is logically multiplied by the first comparison signal S / D and output as pass / fail information P / F which is an error discrimination result.

5A to 5K are waveform diagrams for explaining signals of respective parts of the semiconductor memory device for the DA mode test shown in FIGS. 3 and 4.

Referring to FIG. 5, 5 (a) represents a test row address strobe signal TESTRASB applied from an external tester, 5 (b) represents a test column address strobe signal TESTCASB applied from an external tester, and 5 ( c) indicates a test write enable signal, 5 (d) indicates write data, 5 (e) indicates latched write data, 5 (f) indicates read data, and 5 (g) indicates test read The enable signal TESTREADLOAD is shown, 5 (h) represents the test clock signal TESTCLK, 5 (i) represents the output of the output pipeline 340, and 5 (j) is input through the DQ pin. The write data 52 and the read data 54 output through the DQ pin are shown, and 5 (k) represents a test row address 56 and a column address 58 applied from an external tester. FIG. 6 is a flowchart for describing a DA mode test method performed in the semiconductor memory device illustrated in FIGS. 3 and 4.

Referring to FIG. 6, it is determined whether the test write enable signal is activated, and if the test write enable signal is activated, latching N-bit data applied from the outside, and storing the N-bit data in the memory core (steps 62 to 64), and testing after step 64. Determining whether the read enable signal is activated, reading the data written to the memory core and the latched data if the read enable signal is activated, and maintaining the precharge state if the read enable signal is not activated (steps 65 to 67); Determining whether the core data and the latched data are the same, and if it is the same, it is determined that there is no defect, and if it is different from each other (steps 68 to 70).

3, 4, 5 and 6 will be described in more detail with respect to the operation of the semiconductor memory device for the DA mode test and its test method according to the present invention.

That is, when four bits of data are inputted through four data input / output terminals DQ1, DQ2, DQ3, and DQ4 from an external tester (not shown), the input four bits of data are 8-bit data in the data expansion unit 380. Expands to more data In addition, 4-bit data is applied to the input of the multiplexer 334 of the write data storage unit 330. As described above, 8-bit data of the input pipeline 320 is applied to the first input of the multiplexer 310, and the input pipeline 320 is not used in the test mode but is used in the normal operation mode. That is, the test mode signal TEST_MODE applied from the external tester is input as the selection signal of the multiplexer 310, and when the test mode signal TEST_MODE is enabled at the high level, the semiconductor memory device may enter the DA in the normal operation mode. The mode test state is entered. That is, the multiplexer 310 selectively outputs 8-bit data of the input pipeline 320 or 8-bit data applied from the data extension 380 in response to the enabled selection signal TEST_MODE. In this case, it is determined whether the test write enable signal TESTWRITE is activated in the state in which the test row address strobe signal TESTRASB shown in FIG. 5A is enabled (step 62). The 8-bit data output at 380 is written to the RAM core 35, and the 4-bit data is latched to the write data storage unit 330 (step 64). That is, when the test column address strobe signal TESTCASB is enabled at the low level while the test write enable signal TESTWRITE is active at the high level, the data output from the multiplexer 310 is shown in FIG. 5 (d). As such, it is written in the cell corresponding to the corresponding address of the ram core 35.

Also, in the DA mode test state, the multiplexer 334 of the write data storage unit 330 outputs 4-bit data input to the latch 332 using the test write enable signal TESTWRITE as the selection signal. That is, the latch 332 clocks the test column address strobe signal TESTCASB shown in FIG. 5B, and the input column address strobe signal TESTCASB is enabled at a low level and then rises to a high level. At the rising edge, they are latched as shown in Fig. 5E.

At this time, it is determined whether the test read enable signal TESTREADLOAD shown in FIG. 5G is activated (step 65). If the test read enable signal TESTREADLOAD is activated, data written to the RAM core 35 and data stored in the write data storage unit 330 are read through the above process (step 67). If the test read enable signal TESTREAD is not activated in operation 65, the word line inside the memory device maintains a precharge state (operation 66). That is, the data RDA0 to RDA7 and RDB0 to RDB7 read from the RAM core 35 are applied to the output pipeline 340, and in response to the clock signal TESTCLK shown in FIG. Converted to serial data. The signal converted into serial data is shown in Fig. 5 (i). Data input to each output pipeline 340 is applied to four or five comparison units 350a to 350d as described above. In the embodiment illustrated in FIG. 4, four comparison units 350a to 350d may be implemented, and other numbers may be implemented. The 4-bit data for each 1-bit output from the output pipeline 340 is compared with each other in the comparison unit (350a ~ 350d). On the other hand, 4-bit data stored in the write data storage unit 330 is applied to the latch output pipeline 370, and is applied to the second test clock signal TESTCLK2, which is a two-divided signal of the test clock signal TESTCLK. In response, it is converted into 1-bit serial latch data WD_S. The converted 1-bit serial data WD_S is logically combined with the first and second comparison signals by the first to fourth error discriminating units 360a to 360d. That is, since the serial data output from the output pipeline 340 are the same, it is possible to determine whether or not there is no abnormality in the RAM core cell by comparing the data. Each comparator 350a to 350d compares the input data and outputs the compared result as a first comparison signal S / D and a second comparison signal H / L. Here, the first comparison signal S / D is a signal indicating whether the input data are the same or different. If the four bits of data are the same, the first comparison signal S / D outputs a high level signal, and if the data is different, a low level signal is output. . Similarly, if the data input to the comparator 350 is data having a logic '1', the second comparison signal H / L of high level is output, and if the data has a logic '0', the low level zero is output. Outputs two comparison signals (H / L). In this process, the first comparison signal S / D and the second comparison signal H / L output from the comparators 350a to 350d are connected to the serial latch data WD_S output from the latch output pipeline 370. Logical combinations.

As a result, it is determined whether the 8-bit data output from the output pipeline 340, that is, the data written in the ram core 35 and the serial latch data WD_S of the data stored in the write data storage unit 330 are the same. If it is the same (step 70), it is determined that there is no defect (step 70), and if it is not the same, it can be determined that there is a defect (step 69). That is, the second comparison signal H / L and the serial latch data WD_S of the comparator 350 are exclusive inverted-OR in the exclusive NOR gate 362. Here, since the level of the data output from the comparator 350 and the serial latch data WD_S are the same level, when the RAM core 35 is normal, the exclusive logic sum gate 362 outputs a high level signal. However, if the output of the serial latch data WD_S and the comparator 350 are different from each other, the cells of the RAM core 35 may be defective, and thus the output of the exclusive NOR gate 362 is at a low level. .

Thus, the output of exclusive NOR gate 362 is ANDed at AND gate 364 with the first comparison signal S / D. That is, when all data are normally output, the output of the first comparison signal S / D and the exclusive Noah Geat 362 are both at high level, and the end gate 364 is connected to the high level through the input / output terminals DQ1 to DQ4. Pass / fail signal is output. However, if the first comparison signal S / D is at a low level or the output of the exclusive NOR gate 362 is at a low level, the cell of the ram core 35 is defective, and thus the pass / fail signal P / F) That means that it is a fail. Data 52 inputted through the data input / output terminals DQ1 to DQ4 and data 54 outputted are shown in FIG. 5 (j).

That is, as shown in FIG. 5 (j), the test using the structure in which the number of pins used in the test shown in FIGS. 3 and 4 is reduced is the test row address strobe signal TESTRASB shown in FIG. 5 (a). The test column address strobe signal TESTCASB and the test write enable signal TESTWRITE shown in FIG. 5 (b) are toggled while the low level is set, and the write and read operations are repeatedly performed.

According to the present invention, by detecting whether a defect exists by using the latched data in the direct access mode test, the error of the pass / fail information can be eliminated without outputting the high / low information, as well as the direct access of the semiconductor memory. By reducing the number of pins used in mode tests, the test equipment can be used efficiently.

Claims (6)

Data expansion means for inputting N bits of data applied from an external tester through a data input / output terminal, and expanding the input N bits of data into M (> N) bits of data; Data selection means for selectively outputting the M-bit data output from the data expansion means and the M-bit data output from a predetermined input pipeline in response to a test mode signal; Write data storage means for latching N bits of data input from the external tester; A memory core for storing M-bit data output from the data expansion means or M-bit data output from the input pipeline or outputting the stored data; A plurality of output pipelines for converting the M-bit data stored in the memory core into serial data and outputting the converted data; Comparing means for comparing a plurality of bits of data output from the plurality of output pipelines and outputting the compared result as a first comparison signal and a second comparison signal; A latch output pipeline for converting the N bits of data latched by the write data latching means into serial data in response to a test read enable signal, and outputting the converted data as serial latch data; And And error discriminating means for logically combining the first and second comparison signals and the serial latch data, and outputting the result of the logical combination as an error discrimination signal. The writing data storage means of claim 1, A multiplexer for making N bits of data applied from the external tester as a first input and outputting the N bits of data in response to a test write enable signal; And And a latch configured to input data to the output of the multiplexer and apply the input N-bit data to the second input of the multiplexer in response to a test column address strobe signal. The method of claim 2, wherein the error determination means, Exclusive inversion-OR means for exclusive inverting OR of the serial latch data and the second comparison signal output from the latch output pipeline; And And logical AND means for outputting the output of the exclusive inversion logical sum means to the first comparison signal and outputting the result of the AND as a error discrimination signal and outputting the result through the input / output terminal. The method of claim 3, wherein the first comparison signal output from the comparison means is a signal indicating whether the data input to the comparison means is the same or different from each other, and the second comparison signal is a data input to the comparison means. And a signal indicating whether the level is high or low. Determining whether the test write enable signal is active; If the test write enable signal is activated, latching N bits of data applied from an external tester and writing the data into a cell of a corresponding address of a memory core; (a) determining whether the test read enable signal is activated; Outputting the data written to the memory core and the latched data when the test read enable signal is activated; Precharging if the test read enable signal is not active; determining whether the data written in the memory core and the latched data are the same; Determining that there is no defect if the written data and the latched data are the same; And If the written data and the latched data are different, determining that there is a defect. The method of claim 5, wherein step (b) comprises: Comparing the latched data with the level of the written data; And And if the level of the latched data and the written data is the same, determining whether the written data are equal to each other.