KR19990047053A - Flash memory device and its cell program method - Google Patents

Abstract

The present invention provides a method of programming a flash memory device capable of realizing a low potential and a low power device with a reduced cell size compared to a conventional memory cell without changing the structure of a conventional split gate type memory cell. A program method of a flash memory device comprising a memory cell having a drain, a floating gate, and a control gate, the method comprising: designating a specific memory cell for programming data using an address; Raising a potential of a control gate to a high potential higher than the power supply potential while applying a power supply voltage to a drain of the designated memory cell and applying a ground potential to a source; And plotting the source in response to the potential of the control gate reaching the high potential.

Description

Flash memory device and its cell program method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for programming a flash memory device, and more particularly, to a method for programming a flash memory device for efficiently programming memory cells even under low power supply potential.

In general, a flash memory device has an erase function for electrically erasing stored data and a program function for electrically storing new information. In order to implement such a function, the flash memory device includes a memory cell 10 having a structure in which the floating gate 102 and the control gate 104 are stacked on the semiconductor substrate 100 as illustrated in FIG. 1.

The program operation for storing data in the memory cell 10 having the above-described structure is performed by changing the threshold voltage of the memory cell transistor by storing charge in the floating gate 102 of the memory cell 10. In addition, an erase operation for deleting stored data is performed by releasing charge stored in the floating gate 102 by the program operation to reduce the threshold voltage of the memory cell transistor to its original state.

The memory cells included in the flash memory device are classified into a stack gate type and a split gate type according to their structure, and thus, there are differences in the program and erase methods. However, in the stack gate type flash memory device, an excessive erasure phenomenon is likely to occur in which the floating gate of some cells does not recover to an electrical equilibrium state due to a change in the manufacturing process of the insulating film. If an over-erasing condition of some of these cells occurs, normal operation is impossible.

In order to make up for such drawbacks of a stacked gate type flash memory device, as shown in FIG. 1, an additional transistor 106 in series with the stack gate structure (hereinafter referred to as a "select transistor"). A split gate type memory cell having a structure in which) is inserted is used. In order to read the stored information, the split gate type memory cell 10 must first turn on the selection transistor 106 to solve the problem of malfunction due to over erase.

A program operation for storing data in the split gate type memory cell 10 may form a channel between the drain 110 and the source 112 of the memory cell 10 and apply a high potential to the control gate 104. In addition, it is common to use a channel hot electron injection mechanism, and a FN tunneling mechanism is generally used to erase data.

However, the split gate type memory cell 10 solves the over erase problem in the stack gate type memory cell. However, in order to prevent leakage current that may occur in the channel of the select transistor 106, the select transistor ( Since the channel length of 106) must be kept above a certain value, the size of the memory cell becomes large, resulting in problems of high integration.

In addition, in order to realize low potential and low power devices such as 3.3 V or 2.5 V, efficient program characteristics should be ensured even under a low drain potential (generally the same as a power supply potential). To this end, a method of adding a charge pumping circuit to raise the potential of the drain 110 to a power supply potential or higher (for example, 5 V) during programming may be considered. However, according to a conventional program method using channel hot electrons, the drain ( Since a large drain current flows from 110 to the source 112, it is impossible to increase the potential of the drain node by charge pumping.

Accordingly, the present invention is to solve the above problems, the cell size is reduced compared to the conventional memory cell without changing the structure of the conventional split gate type memory cell, it is possible to implement a low potential and low power device An object of the present invention is to provide a flash memory device and a cell program method thereof.

1 is a cross-sectional view of a memory cell of a typical flash memory device.

2 is a timing diagram illustrating a program process of a flash memory device according to an exemplary embodiment of the present invention.

3 is a block diagram of a flash memory device according to an embodiment of the present invention.

* Explanation of the symbols of the main parts of the drawings

10. Memory cell 100. Semiconductor substrate

102. Floating Gate 104. Control Gate

106. Select Transistor 108. Select Gate

110. Drain 112. Source

In order to achieve the above object, a program method of a flash memory device of the present invention is a program method of a flash memory device including a memory cell having a source, a drain, a floating gate, and a control gate. Designating a particular memory cell to perform; Raising a potential of a control gate to a high potential higher than the power supply potential while applying a power supply voltage to a drain of the designated memory cell and applying a ground potential to a source; And plotting the source in response to the potential of the control gate reaching the high potential.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a timing diagram illustrating a bias condition when programming a memory cell of the present invention, and the embodiment of the present invention will be described with reference to FIGS. 1 and 2.

First, when a program operation is started by a predetermined control signal (for example, / WE, etc.), the memory cell 10 to be programmed is designated by a general address decoding process. In order to program the memory cell 10 specified above, the present invention applies a power supply potential to the drain 110 of the memory cell 10, the source 112 is grounded, and the select transistor 106 is closed. In the state where a potential (for example, 1.8V) between the ground potential and the power supply potential is applied to the gate 108 (hereinafter, referred to as a "selection gate"), the control gate 104 has a potential by charge pumping. Is gradually raised to apply a high potential (eg, 12V) above the supply potential. At this time, before the start of the program operation, the source 112 is in a Don't Care state.

Next, when the potential of the control gate 104 reaches the predetermined high potential, the grounded source 112 is floated.

According to the bias condition, electrons of the semiconductor substrate 100 are generated from a high electric field formed between the substrate under the selection gate 108 and the substrate under the floating gate 102 by the potential of the drain 110. It gets energy and becomes hot electrons. The hot electrons are injected into the floating gate 102 by passing through the gate insulating film between the floating gate 102 and the substrate 100 by a vertical electric field formed by the high potential of the control gate 104. The program operation for data storage is completed.

According to the present invention, the source 112 is temporarily grounded and then maintained in a floating state, which is sufficiently supplied with electrons necessary for the program from the source 112 to increase the program efficiency.

In addition, in order to maximize overall program efficiency and characteristics thereof, it is desirable to increase the potential of the drain 110. In order to increase the potential of the drain 110, it can be solved by adding an additional charge pumping circuit. According to the present invention, since the current from the drain 110 does not flow while the source 112 is floated, the potential of the drain 110 is increased by charge pumping.

Accordingly, the flash memory device using a low potential power supply having a power supply voltage of 2.5 V or 3.3 V can be effectively programmed by the present invention without changing the memory cell structure.

2 is a configuration diagram of a flash memory device for implementing the source floating program method of the present invention described above.

Referring to FIG. 2, the flash memory device according to the present exemplary embodiment may latch in response to a chip enable signal / CE, a write enable signal / WE, an address signal ADRS, and a data signal DATA. The program signal generator 200 for controlling the execution of the program by generating the address signal LADD and the program signal PGM for executing the program, and the program signal outputted from the program signal generator 200. PGM), the program control signal generator 210 generates the high voltage enable signal HVEN, the drain ground signal DRNGND, the positive charge pump enable signal PCPEN, and the X-decoder enable signal XDECEN. And a program in the flash memory cell array 220 according to the address signal LADD latched through the program signal generator 200 and the X-decoder enable signal XDECEN output from the program signal generator 200. Want to An X-decoder 230 for selectively applying a predetermined voltage to the selection gate of the lash memory cell, and a Y-decoder outputting a predetermined voltage by the address signal LADD latched through the program signal generator 200. And a Z-decoder 250 for outputting a selection signal of the Z-multiplexer 270 by the address signal LADD latched through the program signal generator 200. In addition, a general flash memory device may include a positive charge pump 260 that outputs a predetermined voltage by a positive charge pump enable signal PCPEN output from the Z-decoder 250, and a Z-decoder 250. The Z-multiplexer 270 which selects a predetermined voltage output from the positive charge pump 260 by the output selection signal and transmits the predetermined voltage to the control gate of the flash memory cell array 220, and the program control signal generator 210. The ground signal is transmitted to the source of the flash memory cell array 220 by using the high voltage enable signal HVEN and the drain ground signal DRNGND output from the control circuit as a control signal, and the predetermined output output from the Y-decoder 240. A Y-multiplexer 280 is further provided to transfer the power supply voltage 5V to the drain of the flash memory cell array 270 using the voltage V as a control signal. The Y-multiplexer 280 is provided with a plurality of NMOS transistors proportional to the number of flash memory cells of the flash memory cell array 220.

The operation of a general flash memory device having the above structure will be described below.

The program signal generator 200 which receives the write enable signal / WE, the chip enable signal / CE, the address signal ADRS, and the data signal DATA may receive a program signal when a program command is input from the outside. The generator 200 outputs the PGM signal to the program control signal generator 210, and latches the input address signal ADRS to output the LADD signal to the X-decoder 230, the Y-decoder 240, and the Z-. Output to the decoder 250, respectively. Subsequently, the program control signal generator 210 outputs the X-decoder enable signal XDEN to the X-decoder 230, and outputs the high voltage enable signal HVEN and the drain ground signal DRNGND to the Y-multiplexer, respectively. It is applied to the gates of the NMOS transistors 281 and 284 of 280, and outputs a positive charge pump enable signal PCPEN to the positive charge pump 260.

In this way, by the signals LADD, PGM, XDECEN, HVEN, and PCPEN output from the program signal generator 200 and the program control signal generator 210, the X-decoder 230 may use the flash memory cell array 220. A voltage of about 1.8V is applied to the selection gate of the flash memory cell to execute the program, and the flash memory cell is selected, and the Z-multiplexer 270 selects the signal output from the Z-decoder 250. As a signal, a voltage of about 13V output from the positive charge pump 260 is selected, and a predetermined voltage (1.8V) is applied from the X-decoder 230 to the control gate of the applied flash memory cell.

As such, when the flash memory cell of the flash memory cell array 220 is selected through the X-decoder 230 and the Z-multiplexer 270, the Y-decoder 240 may apply a predetermined voltage to the Y-multiplexer 280. Turn on the NMOS transistors 282 and 2803 to apply a 5V power source to the drain of the selected flash memory cell, and also the high voltage enable signal HVEN and the drain ground signal DRNGND output from the program control signal generator 210. ) Turn on the NMOS transistors 281 and 2804 of the Y-multiplexer 280 to apply a ground voltage to the selected flash memory cell. Here, the ground voltage transferred to the source through the Y-multiplexer 280 is applied only in the initial state of the program, and after the initial state, the NMOS transistors 281 and 2804 are turned off so that the source becomes a floating state.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the programming method of the flash memory device of the present invention has the effect of reducing the cell size by reducing the length of the select gate lower channel, and from the drain 110 to the source 112 during programming. The current does not flow, thereby providing an effect of enabling charge pumping of the drain node for program efficiency when implementing low potential and low power devices.

Claims (5)

A cell program method of a flash memory device comprising a memory cell having a source, a drain, a floating gate, and a control gate, Designating a particular memory cell for programming data using the address; Raising a potential of a control gate to a high potential higher than the power supply potential while applying a power supply voltage to a drain of the designated memory cell and applying a ground potential to a source; And Plotting the source in response to the potential of the control gate reaching the high potential Cell program method of a flash memory device comprising a. The method of claim 1, And applying a potential higher than a power supply potential to the drain. The method of claim 2, And a potential higher than a power supply potential to the drain by charge pumping. A flash memory cell array in which cells having a source, a drain, a select gate, and a control gate are arrayed; A first switching unit connected between the source and a ground potential terminal; A second switching unit connected between the drain and a potential voltage terminal; A decoder unit for selecting a specific memory cell for programming data in response to an address data signal from the outside; Control signal generator for controlling the first switching unit Flash memory device comprising a. The method of claim 4, wherein The decoder unit, A Y-decoder controlling the second switching unit; An X-decoder for selecting a select gate of the specific cell; And Z-decoder for selecting the control gate of the specific cell Flash memory device comprising a.