KR19990043663A - Parallel bit test circuit of semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, comprising: a memory cell array, a parallel bit test circuit having four data signals input from the memory cell array and having a plurality of outputs, and the parallel bit test in response to a signal input from the outside. By providing a parallel bit control circuit that controls the control circuit to test the data signal in combination in many cases, all the defective memory cells in the memory cell array can be checked.

Description

Parallel bit test circuit of semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a parallel bit test circuit for controlling parallel bit tests.

In general, an operation of a semiconductor memory device may write or read one cell data per output pin in one cycle. However, as the memory density increases, a lot of test time is required for a full cell test. I have a problem. To overcome this, the test time is shortened by accessing a plurality of cells simultaneously in one cycle. This is generally called a parallel bit test mode. Parallel bit test mode also accesses multiple cells simultaneously in one cycle, but only one data is accessed through the output pins that interface with the tester. That is, a plurality of bit data are integrated into the semiconductor memory device through the comparator circuit and driven as one output data. For example, if a 1-megabyte semiconductor memory device driven by 10 row address and 10 column address inputs is driven in a parallel bit test mode capable of accessing 4 bits simultaneously, the full cell operates in the normal test mode. Hour (1024 × 1024) cycles, but in 4-bit parallel bit test mode Full cell testing is possible with the number of cycles. Four simultaneously accessed bits appear as one output through the first and second comparators of the two inputs.

1 is a circuit diagram of a parallel bit test circuit, a memory cell array, and an output terminal of a conventional semiconductor memory device. Referring to FIG. 1, the conventional parallel bit test circuit 103 includes two exclusive negative OR gates 111 and 112 constituting the first comparator 121 and one NAND gate constituting the second comparator 115 ( NAND Gate). The memory cell array 101 and the output driver 105 are connected to the input terminal and the output terminal of the parallel bit test control circuit 103, respectively, and the output pin 107 is connected to the output terminal of the output driver 105.

FIG. 1 is a diagram illustrating a data path configuration in a conventional parallel bit test. In FIG. 1, a memory cell array 101 including ten row addresses RA0 to RA9 and ten column addresses CA0 to CA9 is used to display four bits per cycle. Cell data can be read using one output pin. In the parallel bit test, CA8 and CA9 are don't care, and column select lines 0 through which adjacent 4-bit data separated by CA8 and CA9 are selected by a combination of CA0 and CA7. Four bits of data are selected by one of the column select lines. For example, when CSL0 is selected in one selected word line 131, data D0 to D3 related to CA8 and CA9, which are ignored during parallel bit test, are amplified by a bit line sense amplifier (not shown) to respectively input / output lines ( IO to the first to fourth input-output amplifiers (141, 142, 143, 144). Outputs of the first and second input / output amplifiers 141 and 142 are input to the first exclusive negative logic gate 111, and outputs of the third and fourth input / output amplifiers 143 and 144 are the second exclusive negative logic gate 112. Is entered. The outputs of the first and second negative logic gates 111 and 112 are input to the second comparator 115, and the output of the second comparator 115 is transmitted to the output pin 107 through the output driver 105. Thus, if the outputs of the first and second input / output sense amplifiers 141 and 142 are identical to each other and the outputs of the third and fourth input / output sense amplifiers 143 and 144 are identical to each other, then the outputs of the first and second exclusive negative OR gates. Since both 111 and 112 are high and the output of the second comparator 115 is low, the output of the output driver 105 becomes high and is transmitted to the output pin 107.

That is, if any one of the data inputted to the first and second exclusive negative OR gates 111 and 112 is different, the data generated at the output pin goes low to indicate a failure, but the data is stored in the logic state of the data of the memory cell array 101. Regardless, when the data input to the first and second exclusive negative OR gates 111 and 112 are the same, the data generated on the output pin 107 becomes high to indicate good quality. When data is written in all the cells of the memory cell array 101, the data output from the input / output sense amplifiers 141, 142, 143, and 144 are all high during the parallel bit test. In FIG. 1, even though the data output from the first and second input / output sense amplifiers 141 and 142 is low, the data appearing on the output pin 107 becomes high and the memory cell array 101 is processed as good. This is a problem that may occur in parallel bit testing of a conventional semiconductor memory device.

Accordingly, an aspect of the present invention is to provide a semiconductor memory device capable of accurately determining a defective cell of a memory cell array during a parallel bit test.

1 illustrates a parallel bit test circuit, a memory cell array, and an output driver of a conventional semiconductor memory device.

2 is a block diagram of a parallel bit test circuit and a parallel bit control circuit and a memory cell array of a semiconductor memory device according to the present invention.

3 is a circuit diagram of the parallel bit test circuit shown in FIG.

4 is a circuit diagram of the parallel bit control circuit shown in FIG.

In order to achieve the above technical problem, the present invention provides a memory cell array, a parallel bit test circuit for inputting four data signals from the memory cell array and having a plurality of outputs, and the parallel bit test in response to a signal input from the outside. There is provided a semiconductor memory device comprising a parallel bit control circuit for controlling and controlling a control circuit to combine and test the data signal in many cases.

According to the present invention, the defective cells of the memory cell array are accurately determined during the parallel bit test.

Hereinafter, the present invention will be described in detail through examples.

2 is a block diagram of a parallel bit test circuit, a parallel bit control circuit, and a memory cell array of a semiconductor memory device according to the present invention. 2, a semiconductor memory device according to the present invention includes a memory cell array 201, a parallel bit test circuit 211, and a parallel bit control circuit 221.

The parallel bit test circuit 211 inputs data signals Di; i = 0, 1, 2... From the memory cell array 201 and has a plurality of outputs A, B, and C.

The parallel bit control circuit 221 controls the parallel bit test circuit 211 in response to the signals A8 and A9 input from the outside to test the data signal Di by combining the data signal Di in many cases.

In FIG. 2, in contrast to the data signals Di of the memory cell array, the data signals D0 and D2 and the data signals D1 and D3 are always input to predetermined comparators. Any combination of data signals Di is possible using the CA8 and CA9 address inputs, which are ignored during testing. For example, the combination of the data signals D0 and D2 and the data signals D1 and D3 as well as the combination of the data signals D0 and D1 and the data signals D2 and D3 and the data signals D0 and D3. ) And data signals D1 and D2 may be combined.

In the parallel bit test, CA8 and CA9 are don't care, and column select lines 0 through which adjacent 4-bit data separated by CA8 and CA9 are selected by a combination of CA0 and CA7. Four bits of data are selected by one of the column select lines. For example, when CSL0 is selected from one word line data that is active, data D0 to D3 related to CA8 and CA9 which are ignored during the parallel bit test are input to the parallel bit test circuit 211.

3 is a circuit diagram of the parallel bit test circuit shown in FIG. 2. 3, the parallel bit test circuit 211 includes data selectors 311, 312, and 313, exclusive negative AND gates 321 to 326, and NAND gates 331 to 333. Parallel bit test circuit 211 inputs control signals DCA1, DCA2, DCA3 and data signals D1, D2, D3, and D4, and outputs output signals DQ1, DQ2, and DQ3. Each of the four transmission gates is configured to determine the operation of the data selectors 311, 312, and 313 according to the control signals DCA1, DCA2, and DCA3, that is, when the control signal DCA1 is activated, the data selector 311. Is activated to check the combination of the data signals D0, D2 and D1, D3. When the control signal DCA2 is activated, the data selector 312 is activated to activate the data signals D0, D1, D2, D3. ) Can be checked. When the control signal DCA3 is activated, the data selector 313 is activated to activate the data signals D0 and D. The combination of 3 and D1, D2) can be checked.

4 is a circuit diagram of the parallel bit control circuit shown in FIG. Referring to FIG. 4, the parallel bit control circuit 221 includes inverters 411 to 417 and NAND gates 421, 422, and 423. The parallel bit control circuit 221 determines an active state of the output signals DCA1, DCA2, and DCA3 according to signals A8 and A9 input from the outside. That is, in the Y-ADDRESS input period of the parallel bit test cycle, if the signals A8 and A9 are all low, the output signal DC3 is active high, and if the signal A8 is low and the signal A9 is high, the output is high. Signal DCA1 is active high.

When a bad memory cell exists among the memory cells of the memory cell array 201 by the semiconductor memory device of the present invention, all of these bad memory cells are checked.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

As described above, when there are defective memory cells among the memory cells of the memory cell array 201, all of these defective memory cells can be checked.

Claims (1)

Memory cell arrays; A parallel bit test circuit for inputting four data signals from the memory cell array and having a plurality of outputs; And And a parallel bit control circuit configured to control the parallel bit test control circuit in response to a signal input from an external source and to test the data signal by combining the data signal in a plurality of cases.