KR19990043438A - Manufacturing method of thin film type optical path control device - Google Patents

Abstract

The present invention relates to a method of manufacturing a thin film type optical path control apparatus which can prevent the deformation layer from being peeled off at a portion where a key box is formed in a heat treatment process after the deformation layer is formed.

In the conventional thin film type optical path control device, since the iso-cutting part is formed using a positive photoresist layer, the strained layer is separated from the membrane in the process of rapidly heat-treating the membrane inside the key box including the wafer key and the strained layer. There was a causal problem.

In the present invention, since the iso-cutting portion is formed using the negative photoresist layer, a separate key box is not required when aligning the mask, so that the strained layer is formed on the lower electrode at the portion where the wafer key is formed. This peeling can be prevented.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method for manufacturing a thin film type optical path control device, and more particularly, to a method for manufacturing a thin film type optical path control device which can prevent the deformation layer from being peeled off at a portion where a key box is formed in a heat treatment process after the deformation layer is formed. .

In general, a spatial light modulator, which is an apparatus for projecting optical energy onto a screen, may be variously applied to optical communication, image processing, and information display apparatus. Such devices are classified into a direct view type image display device and a projection type image display device according to a method of projecting a light beam incident from a light source onto a screen. The direct view image display device includes a CRT (Cathod Ray Tube), and the projection image display device includes a liquid crystal display (hereinafter referred to as an LCD), a DMD (deformable mirror device), or an AMA (Actuated). Mirror Arrays).

The above-described CRT apparatus is an excellent display apparatus which is guaranteed an average brightness of 100 ft-L (white display) or more, a contrast ratio of 30: 1 or more, a lifetime of 10,000 hours or more. However, since the CRT has a large weight and volume and maintains high mechanical strength, it is difficult to make the screen completely flat, which causes distortion of the peripheral part. In addition, since CRTs excite phosphors with an electron beam to emit light, there is a problem that a high voltage is required to produce an image.

Therefore, LCDs have been developed to solve the above-mentioned problems of CRT. The advantages of such LCDs are explained in comparison with CRTs. LCDs operate at low voltages, consume less power, and provide images without distortion.

However, despite the above-mentioned advantages, the LCD has a low light efficiency of 1 to 2% due to the polarization of the light beam, and there is a problem that the response speed of the liquid crystal material therein is slow.

Accordingly, in order to solve the problems of the LCD as described above, a device such as a DMD or an AMA has been developed. Currently, AMA can achieve a light efficiency of 10% or more, while DMD has a light efficiency of about 5%. In addition, the AMA is not only affected by the polarity of the incident luminous flux but also does not affect the polarity of the luminous flux.

Typically, the respective actuators formed inside the AMA cause deformation depending on the electric field generated by the applied image signal and bias voltage. When this actuator causes deformation, each of the mirrors mounted on top of the actuator is inclined in proportion to the magnitude of the electric field.

Thus, these inclined mirrors can reflect light incident from the light source at a predetermined angle. Piezoelectric ceramics such as PZT (Pb (Zr, Ti) O ₃ ), or PLZT ((Pb, La) (Zr, Ti) O ₃ ) are used as a constituent material of the actuator for driving the respective mirrors. As the constituent material of this actuator, electrodistorted ceramics such as PMN (Pb (Mg, Nb) O ₃ ) can be used.

The AMA is classified into a bulk type and a thin film type. Currently, AMA is the main trend of the thin-film optical path control device.

Figure 1 shows a plan view of a conventional thin film type optical path control device, Figure 2 is a cross-sectional view taken along the line A-A 'of the device of Figure 1, Figure 3 is a B-B' line of the device of Figure 1 It is a cross-sectional view cut into pieces.

1 and 2, the thin film type optical path control apparatus includes a driving substrate 10 and an actuator 140 formed thereon.

The driving substrate 10 includes M x N (M, where N is an integer) MOS (Metal Oxide Semiconductor) transistors (not shown). The driving substrate 10 may include a drain pad 20 formed on one surface of the driving substrate 10, a passivation layer 30 formed on the driving substrate 10, and a top of the drain pad 20. An etch stop layer 40 is formed on the upper portion.

The actuator 140 has one side contacted to a portion where the drain pad 20 is formed in the lower portion of the etch stop layer 40, and the other side of the actuator 140 is stacked in parallel with the etch stop layer 40 through an air gap 60. A membrane 70, a bottom electrode 80 stacked on top of the membrane 70, an active layer 90 stacked on top of the bottom electrode 80, and a deformation layer 90 The upper electrode (top electrode) 100 formed on one side and the strained layer 90, the lower electrode 80, the membrane 70, the etch stop layer 60, and the protective layer 40 are formed from the other side of the strained layer 90. A distribution hole 120 vertically formed to the drain pad 20, and a power distribution 130 formed to electrically connect the lower electrode 80 and the drain pad 20 to each other in the distribution hole 120. do. A stripe 110 is formed on one side of the upper electrode 100.

In addition, referring to FIG. 1, one side of the membrane 70 has a rectangular concave portion at a central portion thereof, and the rectangular concave portion has a shape widening stepwise toward both edges. The other side of the membrane 70 has a protrusion that narrows stepwise to correspond to the recessed portion where the membrane of the adjacent actuator is stepped wide. Thus, the protrusion of the membrane 70 is formed by fitting into the concave portion of the adjacent membrane, and the protrusion of the adjacent membrane is formed by inserting into the concave portion of the membrane 70.

Referring to FIG. 3, the protective layer 30 is formed on the driving substrate 10, and the etch stop layer 40 is formed on the protective layer 30. The membrane 70 is formed on the etch stop layer 40, and the lower electrode 80 is formed on the membrane 70. At this time, the iso-cutting part 170 is formed so that a predetermined portion of the lower electrode 80 is electrically separated from the lower electrode of the neighboring actuator. The strain layer 90 is formed on the upper portion of the lower electrode 80 and on the iso cut portion 170. Finally, the upper electrode 100 is formed on the strained layer 90.

Hereinafter, a manufacturing method of a thin film type optical path control device will be described with reference to the drawings.

4A to 4D are manufacturing process diagrams of the apparatus shown in FIG. 3. 4A to 4D, the same reference numerals are given to the same members as in FIG.

Referring to FIG. 4A, chemical vapor deposition (CVD) is performed on a protective layer 30 on an upper portion of a driving substrate 10 having M × N (M and N are integers) transistors (not shown). To form. The protective layer 40 is formed to have a thickness of about 0.1 to 1.0 μm. The protective layer 30 is made of Phospho-Silicate Glass (PSG) and prevents the driving substrate 10 from being damaged during the subsequent process.

Next, the etch stop layer 40 is formed of silicon nitride (Si ₃ N ₄ ) on the protective layer 30. The etch stop layer 40 is deposited to a thickness of about 1000 to 2000 kPa. The etch stop layer 40 is deposited using a low pressure chemical vapor deposition (LPCVD) process for depositing a thin film. That is, the etch stop layer 40 is formed by depositing nitride on the upper portion of the protective layer 40 using a chemical reaction by thermal energy in a low pressure reaction vessel. The etch stop layer 40 prevents the protective layer 30 and its lower portion from being damaged during the subsequent etching process.

Subsequently, the membrane 70 is formed of silicon nitride on the etch stop layer 40. The membrane 70 is formed to a thickness of about 0.1 to 1.0㎛. The membrane 70 is deposited by a low pressure chemical vapor deposition (LPCVD) process similarly to the method of forming the etch stop layer 40 made of silicon nitride. At this time, the stress in the membrane 70 is adjusted while changing the ratio of the reactive gas with time in the low pressure reaction vessel.

Subsequently, the lower electrode 80 is formed on the membrane 70 by using a sputtering process. The lower electrode 80 is made of platinum (Pt) or platinum / tantalum (Pt / Ta) to a thickness of about 0.1 to 1.0 μm.

As such, after the lower electrode 80 is formed, the iso-cutting part 50 shown in FIG. 1 is formed to separate the lower electrode 80 by each pixel.

In more detail, referring to FIG. 4A, the photoresist layer 160 is formed on the lower electrode 80. In this case, the photoresist layer 160 is formed to be positive in which the exposed portion is removed.

Then, the mask 150 is mounted in the upper direction of the photoresist layer 160. At this time, the mask 150 should be exactly aligned to the portion where the iso cut portion 170 will be formed. As such, in order to precisely align the position where the mask 150 and the iso cutting unit 170 are to be formed, a wafer key aligned with a mask key (not shown) formed in a predetermined portion of the mask 150 should be formed.

However, by using the photoresist layer 160 positively, the mask 150 is formed of a material that does not transmit light, for example, chromium (Cr), so that it is impossible to align the mask key and the wafer key. Thus, the mask 150 around the mask key must be transparent for alignment.

Subsequently, light is irradiated onto the mask 150 to demultiplex the photoresist layer 160 at the position where the iso cut portion 170 is to be formed. At this time, since the mask key portion of the mask 150 is transparent for alignment with the wafer key, the photoresist layer 160 around the wafer key is also the photoresist layer 160 at the position where the iso cutting portion 170 is to be formed. Are demultiplexed at the same time.

Referring to FIG. 4B, a portion of the lower electrode 80 is exposed by selectively removing a non-multiplexed portion of the photoresist layer 160. Accordingly, the position where the iso cut portion 170 is to be formed and the photoresist layer 160 around the wafer key are removed to expose the lower electrode 80.

Referring to FIG. 4C, the exposed lower electrode 80 is removed to expose a portion of the membrane 70 to form an iso cut unit 170. At the same time, the lower electrode 80 around the wafer key is also removed at the same time to form a key box 180 as shown in FIG. 5 in which a portion of the membrane 70 is exposed.

Referring to FIG. 4D, the strained layer 90 is formed on the iso cutting part 170 and the lower electrode 80. The strained layer 90 is formed of a piezoelectric ceramic or a total distortion ceramic using a sol-gel method. For example, BaTiO ₃ , PZT ((Pb) (Zr, Ti) O ₃ ), which is a piezoelectric ceramic, or PLZT ((Pb, La) (Zr, Ti) O ₃ ), is deposited, or PMN (Pb), which is a warp ceramic. (Mg, Nb) O ₃ ) is deposited. Preferably, the strained layer 90 laminates PZT to a thickness of about 0.1 to 1.0 mu m. At this time, the deformation layer 80 is formed on the key box 180. Next, the strained layer 80 is subjected to a phase change by heat treatment using a rapid thermal annealing (RTA) process.

Subsequently, aluminum (Al) or platinum (Pt) having good electrical conductivity and reflectivity are sputtered on the strained layer 80. As a result, the upper electrode 100 is formed to a thickness of about 0.1 to 1.0㎛.

However, in the conventional manufacturing method of the thin film type optical path control apparatus, since the iso cutting part is formed using the positive photoresist layer, the strained layer is peeled off from the membrane during the rapid heat treatment of the membrane and the strained layer inside the key box including the wafer key. There was a problem that causes particles.

The present invention has been made to solve the conventional problems as described above, the object of the present invention is a thin film type that can prevent the deformation layer is peeled off by forming a key box using a negative photoresist layer It is to provide a method of manufacturing an optical path control device.

In order to achieve the above object, the present invention provides an M x N transistor (not shown) corresponding to M x N (M, N is an integer) formed on the driving substrate in which the matrix is embedded. Sequentially forming a protective layer and an etch stop layer; Sequentially forming a membrane and a lower electrode on the etch stop layer; Forming an iso cutting portion and a wafer key (not shown) using a negative photoresist layer on the lower electrode; And sequentially forming a strained layer and an upper electrode on the lower electrode and the iso cutting part.

The above objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings by those skilled in the art.

1 is a plan view of a conventional thin film type optical path control device,

2 is a cross-sectional view taken along line AA ′ of the apparatus of FIG. 1;

3 is a cross-sectional view taken along line B-B 'of the apparatus of FIG.

4a to 4d are manufacturing process diagrams of the apparatus shown in FIG.

FIG. 5 is a plan view of the apparatus shown in FIG. 2 arranged in M × N (M and N are integers)

6 is a plan view of a thin film type optical path control apparatus according to the present invention,

FIG. 7 is a cross-sectional view of the device of FIG. 4 taken along line CC ′;

8 is a cross-sectional view taken along line D-D 'of the apparatus of FIG. 5;

9A to 9D are manufacturing process diagrams of the apparatus shown in FIG.

* Explanation of symbols for main parts of the drawings

510: driving substrate 520: drain pad

530: protective layer 540: etching prevention layer

560: air gap 570: membrane

580: lower electrode 590: strained layer

600: upper electrode 610: stripe

620: power distribution hall 630: power distribution

640: actuator 650: iso cutting part

660 photoresist layer 670 mask

Hereinafter, with reference to the accompanying drawings will be described in detail a thin film type optical path control apparatus according to the present invention.

Figure 6 shows a plan view of a thin film type optical path control apparatus according to the present invention, Figure 7 shows a cross-sectional view of the device of Figure 6 cut along the line C-C ', Figure 7 shows the device of Figure 6 D-D 'It's a cross section cut into lines.

6 and 7, the thin film type optical path control apparatus includes a driving substrate 510 and an actuator 640 formed thereon.

The driving substrate 510 includes M x N (M, N is an integer) MOS (Metal Oxide Semi-conductor) transistors (not shown). The driving substrate 510 may include a drain pad 520 formed on one surface of the driving substrate 510, a passivation layer 530 and a passivation layer 530 formed on the driving substrate 510 and the drain pad 520. An etch stop layer 540 is formed on the upper portion.

The actuator 640 contacts one side of a portion of the etch stop layer 540 where the drain pad 520 is formed, and the other side thereof is stacked in parallel with the etch stop layer 540 through an air gap 560. A membrane 570, a bottom electrode 580 stacked on top of the membrane 570, an active layer 590 stacked on top of the bottom electrode 580, and a modified layer 590 The strained layer 590, the lower electrode 580, the membrane 570, the etch stop layer 560, and the protective layer 540 are formed from the other side of the upper electrode 600 and the strained layer 590 formed on one side. A distribution hole 620 vertically formed to the drain pad 520, and a power distribution 630 formed in the distribution hole 620 to electrically connect the lower electrode 580 and the drain pad 520 to each other. do. A stripe 610 is formed at one side of the upper electrode 600.

In addition, referring to FIG. 6, one side of the membrane 570 has a rectangular concave portion at the center thereof, and the rectangular concave portion has a shape that is stepped wider toward both edges. The other side of the membrane 570 has a protrusion that narrows stepwise to correspond to the recessed portion where the membrane of the adjacent actuator widens stepwise. Thus, protrusions of the membrane 570 are formed by fitting into concave portions of the adjacent membrane, and protrusions of adjacent membranes are formed by inserting into the concave portions of the membrane 570.

Referring to FIG. 8, a protective layer 530 is formed on the driving substrate 510, and an etch stop layer 540 is formed on the protective layer 530. The membrane 570 is formed on the etch stop layer 540, and the lower electrode 580 is formed on the membrane 570. In this case, an iso cut part 650 is formed in a predetermined portion of the lower electrode 580 to be electrically separated from the lower electrode of the neighboring actuator. The strain layer 590 is formed on the upper portion of the lower electrode 580 and on the iso cut portion 650. Finally, the upper electrode 600 is formed on the strained layer 590.

Hereinafter, a manufacturing method of a thin film type optical path control device according to the present invention will be described with reference to the drawings.

9A to 9D are manufacturing process diagrams of the apparatus shown in FIG. 8. 9A to 9D, the same reference numerals are given to the same members as in FIG. 8.

Referring to FIG. 8A, chemical vapor deposition (CVD) is performed on a protective layer 530 on an upper portion of a driving substrate 510 having M × N (M and N are integers) transistors (not shown). To form. The protective layer 530 is formed to have a thickness of about 0.1 to 1.0 μm. The protective layer 530 is made of Phospho-Silicate Glass (PSG) and prevents the driving substrate 510 from being damaged during the subsequent process.

Next, an etch stop layer 540 is formed of silicon nitride (Si ₃ N ₄ ) on the protective layer 530. The etch stop layer 540 is deposited to a thickness of about 1000 to 2000 kPa. The etch stop layer 540 is deposited using a low pressure chemical vapor deposition (LPCVD) process for depositing a thin film. That is, the etch stop layer 540 is formed by depositing nitride on the protective layer 530 using a chemical reaction by thermal energy in a low pressure reaction vessel. The etch stop layer 540 prevents the protective layer 530 and its lower portion from being damaged during the subsequent etching process.

Subsequently, a membrane 570 is formed of silicon nitride on the etch stop layer 540. The membrane 570 is formed to a thickness of about 0.1 to 1.0㎛. The membrane 570 is deposited by a low pressure chemical vapor deposition (LPCVD) process similarly to the method of forming the etch stop layer 540 made of silicon nitride. At this time, the stress inside the membrane 570 is adjusted while changing the ratio of the reactive gas with time in the low pressure reaction vessel.

Subsequently, the lower electrode 580 is formed on the membrane 570 by using a sputtering process. The lower electrode 580 is formed of platinum (Pt) or platinum / tantalum (Pt / Ta) to a thickness of about 0.1 μm to 1.0 μm.

As described above, after the lower electrode 580 is formed, an iso-cutting part 650 shown in FIG. 6 is formed to separate the lower electrode 580 for each pixel.

In more detail, the photoresist layer 660 is formed on the lower electrode 580. At this time, the photoresist layer 660 is formed negative, and the unexposed portions are removed. The mask 670 is mounted in the upper direction of the photoresist layer 660. In this case, the mask 670 should be exactly aligned with the portion where the iso cut portion 650 is to be formed. As such, in order to accurately align the mask 670 to the portion where the iso cutting part 650 is to be formed, a mask key (not shown) and a wafer key (not shown) are shown in the key box 180 shown in FIG. 5. Must be set. Accordingly, in order to align the mask key and the wafer key, the mask 670 of the upper direction of the key box 180 is transparent in the related art, but in the present invention, since the negative photoresist layer 660 is used, the iso cutting part 650 The mask 670 of the remaining portion is transparent except for the portion where the is to be formed. Therefore, the wafer key and the mask key can be easily aligned without the need for a separate key box. Subsequently, light is irradiated onto the mask 670. At this time, the photoresist layer 660 in the portion where the iso cut portion 650 is to be formed is not affected by light and is thus non-multiplexed.

Referring to FIG. 9B, an unmultiplexed portion of the photoresist layer 660 is selectively removed. Accordingly, the photoresist layer 660 formed on the portion where the iso cut portion 650 is to be formed is removed to expose the lower electrode 580. At this time, since the negative photoresist layer 660 is formed in the portion where the wafer key is formed, the photoresist layer 660 is not removed because the photoresist layer 660 is not demultiplexed even when light is irradiated.

Referring to FIG. 9C, the exposed lower electrode 580 is removed to form the iso cut part 650. Subsequently, the photoresist layer 660 formed on the lower electrode 580 is removed. At this time, the photoresist layer 660 on which the wafer key is formed is also removed to expose the lower electrode 580.

Referring to FIG. 9D, the strain layer 590 is formed on the iso cutting part 650 and the lower electrode 580. The strained layer 590 is formed of a piezoelectric ceramic or a total distortion ceramic using a sol-gel method. For example, BaTiO ₃ , PZT ((Pb, La) (Zr, Ti) O ₃ ), which is a piezoelectric ceramic, or PLZT ((Pb, La) (Zr, Ti) O ₃ ), is deposited or PMN, which is an all-ceramic ceramic. (Pb (Mg, Nb) O ₃ ) is deposited. Preferably, the strained layer 590 laminates PZT to a thickness of about 0.1 to 1.0 mu m. Next, the strained layer 590 is subjected to heat treatment using a rapid thermal annealing (RTA) process to phase change.

As described above, the method for manufacturing the thin film type optical path control apparatus according to the present invention forms an iso cutting part using a negative photoresist layer, so that a separate key box is not required when aligning the mask, so that the deformation layer is formed at the portion where the wafer key is formed. Since it is formed on the lower electrode, there is an effect that can prevent the strained layer is peeled off in a subsequent process.

As described above, although the present invention has been described with reference to the drawings, those skilled in the art may variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. I can understand that you can.

Claims (3)

A protective layer 530 and an etch stop layer 540 formed on the driving substrate 510 in which M × N transistors (not shown) corresponding to M × N (M and N are integers) pixels are formed in a matrix form. ) Sequentially forming; Sequentially forming a membrane 570 and a lower electrode 580 on the etch stop layer 540; Forming an iso cutting part (650) and a wafer key (not shown) using a negative photoresist layer (660) on the lower electrode (580); And forming a strained layer (590) and an upper electrode (600) on top of the lower electrode (580) and the iso cut part (650). The method of claim 1, wherein the forming of the iso cut part 650 comprises: i) forming a photoresist layer 660 on the lower electrode 580, ii) forming the photoresist layer 660. Aligning the mask 670 in an upper direction of the substrate; iii) demultiplexing a portion of the photoresist layer 660 in which the iso cut portion 650 is to be formed; iv) the non-multiplexed photoresist layer ( Selectively removing 660 to expose the lower electrode 580, v) removing the exposed lower electrode 580, vi) a photoresist layer remaining on top of the lower electrode 580 ( Method of manufacturing a thin film type optical path control device comprising the step of removing (660). The method of claim 2, wherein the mask 670 is opaquely formed with a pattern of the iso cutting part 650 and a pattern of a mask key (not shown) on the transparent substrate. .