KR19990043386A - Data Buffer Integrated Circuits in Communication Processing System Processor Boards - Google Patents

Abstract

The present invention relates to an apparatus for simplifying the configuration of a board by integrating a buffer in a processor board implemented using a microprocessor.

The present invention includes a local data buffer 320 for transferring write data in a write operation from a main processor to a local device; A VME data buffer 330 for transferring write data in the write operation from the main processor to the VME device; a DRAM data buffer 340 for transferring write data in the write operation from the main processor to the DRAM; A dual port RAM data buffer 350 for transferring write data in a write operation from the main processor to the dual port RAM; A processor data buffer 310 for transferring read data from any one of the local device, the VME device, the DRAM, and the dual port RAM to the main processor according to a selection signal, the data buffers being on the same chip. It is implemented and compact. Therefore, the structure of the processor board can be simplified, and the manufacturing cost can be reduced.

Description

A device for integrating data buffers in processor board of information communication processing system

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor board implemented using a microprocessor, and more particularly, to a processor board in an information communication processing system (ICPS) that integrates a buffer to simplify the configuration of the board. will be.

In general, microprocessors are divided into CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer). CISC includes many kinds of instructions in the instruction set, and each instruction can perform a complex task. It is a form of computer. This CISC aims to minimize the number of instructions required to perform a given task, and to minimize the semantic differences between the high-level programming language and the machine language as the use of the high-level programming language becomes common. Thus, CISC is easy to program in assembly language and easily copes with high-level language programming, making compiler design easier. In addition, since one command performs a complicated function, the size of the target program is reduced.

RISC fits the compiler to implement complex tasks using multiple simple instructions, supports only a few simple instructions, reduces the area the controller occupies on the processor chip, and provides large registers or cache memory in this space. It is a computer with a structure that reduces program execution time. In other words, CPU time, which is generally accepted as a performance measurer of a microprocessor, is defined as the product of the number of instructions in the target program and the average clock cycle (CPI) for executing the instructions. CISC focuses on reducing the size of the target program. RISC, on the other hand, focuses on reducing the clock cycle time of the CPI.

Intel's 80x86 series and Motorola's MC680x0 series are widely known as CISC-type microprocessors. The MC680x0 series is widely used in processor boards that control the entire system in communication systems. For example, the processor board using the MC68030 used in the communication processing system, as shown in Figure 1, the main processor 110, the reset circuit 112, the first to fourth data buffers (114, 124, 128, 130), SRAM (116), A ROM 118, a first communication chip (MFP1: 120), a second communication chip (MFP2: 122), a DRAM 126, and a dual port RAM (DPRAM: 132). The processor board is mounted on a back board (TNBB) 108 and connected to other boards.

Referring to FIG. 1, the MC68030 is used as the main processor 110. The MC68030 is connected to external devices through a 32-bit data bus, a 32-bit address bus, and various signal lines. The SRAM 116, the ROM 118, and the first and second communication chips 120 and 122 are connected to the data bus MP_D [31..0] of the main processor 110 through the first data buffer 114. The DRAM 126 is connected to the data bus MP_D [31..0] through the second data buffer 124, and the dual port RAM DPRAM 132 receives data through the fourth data buffer 130. It is connected to the bus MP_D [31..0]. And the third data buffer 128 is used for connection with the VME device.

As such, the conventional processor board employs the MC68030 to provide all data buses through individual buffers. Therefore, in the conventional processor board, the number of individual components increases, so that the buffer occupies about two thirds of the entire space of the processor board. In addition, a large number of individual components can easily cause board failures and make board assembly difficult.

Accordingly, an object of the present invention is to provide a data buffer integrated circuit in a processor board of a communication processing system capable of compactly configuring a processor board by integrating data buffers to solve the above problems.

In order to achieve the above object, the apparatus of the present invention is a processor board of a communication processing system for controlling other boards mounted on the same shelf by mounting a main processor providing an address bus, a data bus and a control signal line, A local data buffer for transferring write data during a write operation from the main processor to a local device; A VME data buffer for transferring write data during a write operation from the main processor to a VME device; A DRAM data buffer for transferring write data during a write operation from the main processor to the DRAM; A dual port RAM data buffer for transferring write data in the write operation from the main processor to the dual port RAM; A processor data buffer for transferring read data from one of the local device, a VME device, a DRAM, and a dual port RAM to a main processor according to a selection signal, wherein the data buffers are implemented on the same chip. It is characterized by being compact.

1 is a block diagram showing the configuration of a conventional processor board;

2 is a block diagram showing a configuration of a processor board to which the present invention is applied;

3 is a block diagram illustrating a data buffer integrated circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

202: address bus 204: control signal line

206: data bus 210: main processor

212: reset circuit 214: data buffer integrated circuit

216: SRAM 218: ROM

220,222: communication chip (MFP) 224: VME device

226: DRAM 228: dual port RAM (DPRAM)

310: processor data buffer 320: local data buffer

330: VME data buffer 340: DRAM data buffer

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing a configuration of a processor board to which the present invention is applied, and FIG. 3 is a block diagram showing a data buffer integrated circuit according to the present invention.

As shown in FIG. 2, a processor board to which the present invention is applied includes a main processor 210, a reset circuit 212, a data buffer integrated circuit 214, an SRAM (SRAM: 216), and a ROM (ROM: 218). And a first communication chip (MFP1: 220), a second communication chip (MFP2: 222), a VME device 224, a DRAM (DRAM: 226), and a dual port RAM (DPRAM: 228).

Referring to FIG. 2, the main processor 210 may be an MC68040 or higher processor, which provides an address bus, a data bus, and a control signal line. As illustrated in FIG. 3, the data buffer integrated circuit 214 may include a processor data buffer 310, a local data buffer 320, a VME data buffer 330, a DRAM data buffer 340, and a dual port RAM data buffer ( 350 to provide a data bus to local devices such as SRAM 216, ROM 218, MFP1 220, MFP2 222, and VME devices 224, DRAM 226, DPRAM 228. .

2 and 3, the data buffer integrated circuit includes a local data bus MP_LD [31..0], a VME data bus VME_D [31..0], and a DRAM data bus DR_D [31..0]. ]), The dual port RAM data bus DP_D [31..0] is connected to the processor data bus MP_D [31..0]. The local data bus MP_LD [31..0] has a 32-bit wide SRAM 216, a 16-bit wide ROM 218, an 8-bit wide first MFP 220, and an 8-bit wide second MFP ( 222 is connected, the VME device 224 is connected to the VME data bus VME_D [31..0], the DRAM 226 is connected to the DRAM data bus DR_D [31..0], and the dual port RAM data bus ( DPRAMs 228 are connected to DP_D [31..0], respectively. That is, SRAM 216 is connected to bus MP_LD [31..0], ROM 218 is connected to bus MP_LD [31..16], and MFP1 220 is connected to bus MP_LD [31..24]. MFP2 222 is connected to bus MP_LD [31..24].

The reset circuit 212 resets the main processor 210 at power-on, and various control programs are stored in the ROM 218, and the first MFP 220 provides a connection with the console and the second MFP 222. ) Provides serial communication.

Referring to FIG. 3, write data from the main processor 210 to the local device is transferred through the local data buffer 320, and read data from the local device to the main processor are transferred through the processor data buffer 310. . The write data from the main processor to the VME device is transferred through the VME data buffer 330, and the read data from the VME device to the main processor is transferred through the processor data buffer 310. Write data from the main processor to the DRAM is transferred through the DRAM data buffer 340, and read data from the DRAM to the main processor is transferred through the processor data buffer 310. Write data from the main processor to the dual port RAM is transferred through the dual port RAM data buffer 350, and read data from the dual port RAM to the main processor is transferred through the processor data buffer 310. The VME device can also directly access the DRAM. The write data from the VME device to the DRAM is transferred through the DRAM data buffer 340 and the read data from the DRAM to the VME device. Is passed through the VME data buffer 330.

The processor data buffer 310 selects one of four buses according to the selection signal mp_d_sel [0,1] to be connected to the processor data bus MP_D [31..0], and the VME data buffer 330 According to the selection signal vme_d_sel, one of the processor data bus MP_D31..0] or the DRAM data bus DR_D [31..0] is selected and connected to the VME data bus VME_D [31..0]. The DRAM data buffer 340 selects one of the processor data bus MP_D [31..0] and the VME data bus VME_D [31..0] according to the selection signal dr_d_sel, thereby selecting the DRAM data bus DR_D. [31..0]). Each buffer is enabled by a corresponding output enable signal (mp_d_oe, mp_ld_oe, vme_d_sel, dr_d_oe, dp_d_oe), and a selection signal and an enable signal are input from a controller (not shown), and the corresponding buffer is changed according to an operation cycle of the main processor. Enable and select specific buses.

For example, when the main processor 210 writes data to the SRAM 216, after outputting a specific address of the SRAM allocated by the address map, the data is output on the processor data bus MP_D [31..0]. do. Then, the controller (not shown) outputs a signal (mp_ld_oe) for enabling the local data buffer 320 by decoding the address, and also outputs an SRAM chip select signal. It is delivered to SRAM 216 via 320. On the contrary, when the main processor 210 reads data stored at a specific address of the SRAM 216, when the main processor 210 outputs a specific address of the SRAM 216, a controller (not shown) decodes the address and then the SRAM. The chip select signal is output to select the SRAM 216 and provide data stored at the address on the local data bus MP_LD [31..0]. At this time, the controller provides the selection signal mp_d_sel [0,1] so that the processor data buffer 310 selects the local data bus MP_LD [31..0], and also enables the processor data buffer 310. This allows data on the local data bus to enter the main processor via the processor data bus. In the embodiment of the present invention, the selection signal is implemented as shown in Table 1 below.

mp_d_sel [0] mp_d_sel [1] Selected bus 0 0 Local data bus One 0 VME data bus 0 One DRAM data bus One One Dual Port RAM Data Bus

As shown in Table 1, when the selection signal mp_d_sel [0,1] is '00', the local data bus MP_LD [31..0] is selected.

On the other hand, when the main processor 210 writes to the VME device 224, the controller decodes the address output from the processor and outputs the selection signal vme_d_sel to the VME data buffer 330 to select the processor data bus. In addition, a signal (vme_d_oe) for enabling the VME data buffer 330 is output. Accordingly, the processor data bus MP_D [31..0] is connected to the VME data bus VME_D [31..0] through the VME data buffer 330 to transfer the write data to the VME device 224. Conversely, when the main processor 210 reads data from the VME device 224, the controller decodes the address and read control signals so that the processor data buffer 310 clears the VME data bus (VME_D [31..0]). Outputs the selection signal mp_d_sel [0,1] to '10' to select and enables the processor data buffer 310 to transfer the VME device bus VME_D [31..0] to the processor data bus MP_D [. 31..0]).

When the VME device 224 writes directly to the DRAM (DRAM) 226, the controller provides a selection signal dr_d_sel for the DRAM data buffer 340 to select the VME data bus (VME_D [31..0]). In addition, the DRAM data buffer 340 is enabled to connect the VME data bus and the DRAM data bus. When the VME device 224 reads the DRAM 226, the controller enables the DRAM 340 and then outputs data of the corresponding address to the DRAM data bus, and the VME data buffer 330 causes the DRAM data bus ( Outputs the selection signal vme_d_sel to select DR_D [31..0] and outputs the VME buffer enable signal vme_d_oe to convert the DRAM data bus DR_D [31..0] to the VME data bus VME_D. [31..0]).

On the other hand, when the main processor 210 writes to the DRAM (DRAM) 226, the controller decodes the address outputted by the main processor 210 so that the DRAM data buffer 340 can read the processor data bus MP_D [. 0]) to output the selection signal dr_d_sel and to output the signal dr_d_oe that enables the DRAM data buffer 340. Accordingly, the processor data bus is connected to the DRAM data bus through the DRAM data buffer 340 to transfer write data to the DRAM 226. Conversely, when the main processor 210 reads data from the DRAM 226, the controller decodes the address and read control signals so that the processor data buffer 310 selects the DRAM data bus DR_D [31..0]. The select signal mp_d_sel [0,1] is output as '10' and the processor data buffer 310 is enabled to connect the DRAM data bus to the processor data bus.

When the main processor 210 writes to the dual port RAM 228, the controller decodes an address output from the main processor and outputs a signal dp_d_oe that enables the dual port RAM data buffer 350. Therefore, the processor data bus MP_D [31..0] is connected to the dual port RAM data bus DP_D [31..0] through the dual port RAM data buffer 350 so that the write data may be written to the dual port RAM 228. Will be delivered to On the contrary, when the main processor 210 reads data from the dual port RAM 228, the controller decodes the address and read control signal, so that the processor data buffer 310 causes the dual port RAM data bus DP_D [31..0]. Outputs the selection signal mp_d_sel [0,1] to '10' and enables the processor data buffer 310 to convert the dual port RAM data bus DP_D [31..0] to processor data. Connect to the bus MP_D [31..0].

As described above, the integrated circuit according to the present invention simplifies the structure of the processor board and facilitates the design and control by providing all the data buses on the processor board in one large capacity EPLD. In addition, the data bus is integrated into one device to increase design efficiency and reduce the number of individual components mounted on the board, making it easy to manufacture.

Claims (2)

A processor board of a communication processing system for controlling other boards mounted on the same shelf by mounting a main processor providing an address bus, a data bus, and a control signal line, A local data buffer 320 for transferring write data in a write operation from the main processor to a local device; A VME data buffer 330 for transferring write data during a write operation from the main processor to a VME device; A DRAM data buffer 340 for transferring write data during a write operation from the main processor to the DRAM; A dual port RAM data buffer 350 for transferring write data in the write operation from the main processor to the dual port RAM; A processor data buffer 310 for transferring read data from any one of the local device, a VME device, a DRAM, and a dual port RAM to a main processor according to a selection signal, And said data buffers are embodied on the same chip so as to be compact. The communication process according to claim 1, wherein the VME data buffer 330 transfers write data from the VME device to the DRAM, and the DRAM data buffer 340 transfers read data from the DRAM to the VME device. Data buffer integrated circuit on system processor board.