KR19990042110U - SDRAM clock synchronous circuit - Google Patents

Abstract

The present invention relates to a clock synchronization circuit of an SDRAM. When a non-specified address signal and a mode register signal simultaneously enter a system booting system using a conventional SDRAM, a plurality of delay enable signals are output at a low potential, thereby causing the circuit to malfunction. There was a problem that can not execute the system boot. Accordingly, the present invention has been made to solve the above-mentioned conventional problems, the first, second, third inverter; First, second, and third AND gates; A clock synchronizing circuit composed of a delay control section, comprising: a malfunction prevention section for outputting a delay enable signal so as to have a predetermined delay time upon input of an unspecified address signal, and providing a device configured to provide an apparatus for inputting an unspecified address signal. By outputting a delay enable signal having a delay time specified in Fig. 2, there is an effect of preventing a malfunction of a circuit due to an unspecified address signal and improving the reliability of the system.

Description

SDRAM clock synchronous circuit

The present invention relates to a clock synchronization circuit of an SDRAM. In particular, in a system using an SDRAM, an SD delay output signal is output to have a predetermined delay time when an unspecified address signal is input. The clock synchronization circuit of the RAM.

In general, a SDRAM clock synchronization circuit is a circuit for synchronizing clocks to delay input data by a desired clock when performing a read operation using a mode register signal.

FIG. 1 is a clock synchronization circuit diagram of a conventional SDRAM, and inverts and outputs fourth, fifth, and sixth address signals A4, A5, and A6 input from an external input pad (not shown). First, second, and third inverters I1, I2, and I3; A first AND gate AND1 that receives a mode register signal MRS, an output signal of the first and second inverters I1 and I2, and an AND logic operation to output the fourth address signal A4; A second AND gate AND2 for receiving the mode register signal MRS, the first and third inverter signals I1 and I3, and the fifth address signal A5 and performing an AND operation on the mode register signal; A third AND gate AND3 for receiving the mode register signal MRS, the output signal of the first inverter I1, and the fourth and fifth address signals A4 and A5 and performing an AND operation on the mode register signal; A delay control unit configured to output a delay control signal delayed by a corresponding clock by the delay enable signals LE1, LE2, and LE3 output from the first, second, and third AND gates AND1, AND2, and3; It consists of (10).

Hereinafter, with reference to the truth table of Figure 2 attached to the operation of one embodiment according to the prior art will be described in detail.

First, when the mode register signal MRS has a low potential, since the first, second, and third AND gates AND1 to AND3 output a low potential, and the clock synchronizing circuit does not operate, the mode register signal MRS Is applied at high potential to enable the clock synchronizing circuit.

Therefore, when the fourth address signal A4 is at high potential and the fifth and sixth address signals A5 and A6 are at low potential, the first and second inverters I1 and I2 output high potentials. The third inverter I3 outputs a low potential.

Therefore, the first AND gate receives the high potential mode register signal MRS, the high potential output signal of the first and second inverters I1 and I2, and the high potential fourth address signal A4. AND1 outputs the first delay enable signal LE1 having a high potential, but the low voltages of the second and third AND gates AND2 and AND3 respectively receiving the fifth address signal A5 having the low potential. The above second and third delay enable signals LE2 and LE3 are output.

Accordingly, the delay control unit 10 outputs a delay control signal for delaying the input data by one clock by the high delay first delay enable signal LE1 to a clock delay circuit (not shown).

When the fourth and sixth address signals A4 and A6 have a low potential and the fifth address signal A5 has a high potential, the first and third inverters I1 and I3 output a high potential and 2 The inverter I2 outputs a low potential.

Accordingly, the second AND gate AND2 receiving the high potential mode register signal MRS, the high potential output signal of the first and third inverters I1 and I3, and the high potential fifth address signal A5. ) Outputs a second delay enable signal LE2 having a high potential, but the first and third AND gates AND1 and AND3 receiving the fourth address signal A4 having the low potential are respectively low potential. The first and third delay enable signals LE1 and LE3 are output.

Accordingly, the delay control unit 10 receiving the high potential second delay enable signal LE2 outputs a delay control signal for delaying the input data by two clocks.

In addition, when the fourth and fifth address signals A4 and A5 are high potential and the sixth address signal A6 is low potential, the second and third inverters I2 and I3 output low potential and The first inverter I3 outputs a high potential.

Accordingly, the third AND gate AND3 receiving the high potential mode register signal MRS, the high potential fourth and fifth address signals A4 and A5, and the high potential first inverter I1 output signal. The third delay enable signal LE3 is output at high potential, but the first and second AND gates AND1 and AND2 receiving the output signals of the second and third inverters having low potentials are respectively the first and the second. Since the two delay enable signals LE1 and LE2 are output at a low potential, the delay controller 10 receiving the third delay enable signal LE3 outputs a delay control signal for three clock delays.

However, when the sixth address signal A6 has a high potential or the fourth, fifth, and sixth address signals A4 to A6 have low potentials, the first, second, and third AND gates AND1 to AND3) outputs the first, second and third delay enable signals LE1 to LE3 having low potentials, and thus the delay controller 10 is disabled and cannot operate.

As described above, when a non-specified address signal and a mode register signal simultaneously enter a system booting system using a conventional SDRAM, a plurality of delay enable signals are all output at low potentials, thereby preventing a system from booting due to a malfunction of the circuit. there was.

Accordingly, the present invention has been devised to solve the above-mentioned problems. In the system using the SDRAM, an SDRAM which outputs a predetermined delay time when inputting an unspecified address signal prevents malfunction of the circuit. Its purpose is to provide a clock synchronizing circuit.

1 is a clock synchronization circuit diagram of a conventional SDRAM.

2 is a truth table of FIG. 1.

3 is a clock synchronization circuit diagram of the inventive inventive DRAM.

4 is a truth table of FIG. 3.

*** Description of the symbols for the main parts of the drawings ***

10: delay control unit 100: malfunction prevention unit

I1 to I3: Inverter AND1 to AND5: Logic gate

OR: OR gate

In order to achieve the above object, a constitution of the present invention includes: first, second, and third inverters for inverting and outputting first, second, and third address signals respectively input from an external input pad; A first AND gate that receives a mode register signal, an output signal of the first and second inverters, and a third address signal and performs an AND operation on the mode register signal; A second AND gate receiving the mode register signal, the first and third inverter signals, and the second address signal, and performing an AND operation on the mode register signal; A third AND gate that receives the mode register signal, the output signal of the first inverter, and the second and third address signals to perform an AND operation on the mode register signal; An unspecified address signal input in a clock synchronizing circuit comprising a delay control unit for outputting a delay control signal for delaying a corresponding clock by a delay enable signal output from the first, second, and third AND gates. The apparatus may further include a malfunction prevention unit configured to output a delay enable signal to have a predetermined delay time.

The malfunction prevention unit may include a fourth AND gate that receives the mode register signal and the output signals of the second and third inverters and performs a logical AND operation on the output signal; A fifth AND gate that receives the mode register signal and the first address signal, and performs an AND operation on the mode register signal; And a logic sum gate configured to receive the output signals of the first, fourth, and fifth logical product gates, and to perform a logical sum operation to output a first delay enable signal.

Hereinafter, with reference to the accompanying drawings, the operation and effect of an embodiment of the present invention will be described in detail.

FIG. 3 is a clock synchronization circuit diagram of an inventive SDRAM, and inverts and outputs fourth, fifth, and sixth address signals A4, A5, and A6 input from an external input pad (not shown). First, second, and third inverters I1, I2, and I3; A first AND gate AND1 that receives a mode register signal MRS, an output signal of the first and second inverters I1 and I2, and an AND logic operation to output the fourth address signal A4; A second AND gate AND2 for receiving the mode register signal MRS, the first and third inverter signals I1 and I3, and the fifth address signal A5 and performing an AND operation on the mode register signal; A third AND gate AND3 for receiving the mode register signal MRS, the output signal of the first inverter I1, and the fourth and fifth address signals A4 and A5 and performing an AND operation on the mode register signal; A malfunction prevention unit 100 for outputting a delay enable signal to have a predetermined delay time when inputting an unspecified address signal; The delay enable signal LE1 of the malfunction prevention unit 100 and the delay enable signals LE2 and LE3 of the second and third AND gates AND2 and AND3 are respectively input. The delay control unit 10 outputs a delay control signal delayed by a clock.

The malfunction prevention unit 100 includes a fourth AND gate AND4 for receiving the mode register signal MRS and the output signals of the second and third inverters I1 and I2 and performing an AND operation on the output signals. ; A fifth AND gate AND5 for receiving the mode register signal MRS and the sixth address signal A6 and performing an AND operation on the mode register signal; And a logic sum gate OR that receives the output signals of the first, fourth, and fifth AND gates AND1, AND4, and AND5, and performs a logical sum operation to output a delay enable signal LE1.

Hereinafter, with reference to the truth table of Figure 4 attached to the operation of an embodiment according to the present invention configured as described in detail as follows.

First, when the mode register signal MRS has a low potential, since the first to fifth AND gates AND1 to AND5 output a low potential, the clock synchronizing circuit does not operate, so that the mode register signal MRS is high. Applied upward to enable the clock synchronization circuit.

Here, when the fourth address signal A4 has a high potential and the fifth and sixth address signals A5 and A6 have a low potential, the first and second inverters I1 and I2 output a high potential. The third inverter I3 outputs a low potential.

Therefore, the first AND gate receives the high potential mode register signal MRS, the high potential output signal of the first and second inverters I1 and I2, and the high potential fourth address signal A4. AND1) outputs a high potential, and outputs a low potential of the second to fifth AND gates AND2 to AND5.

Accordingly, the OR gate OR in the malfunction prevention part 100 that receives the output signal of the first AND gate AND1 having high potential and the output signals of the fourth and fifth AND gates AND4 and 5 having low potential is The high potential first delay enable signal LE1 is output, and the second and third AND gates AND2 and AND3 output the low potential second and third delay enable signals LE2 and LE3. .

Accordingly, the delay control unit 10 receiving the high potential first delay enable signal LE1 outputs a delay control signal for delaying one clock to a clock delay circuit (not shown).

The fourth and sixth address signals A4 and A6 have a low potential, the fifth address signal A5 has a high potential, and the fourth and fifth address signals A4 and A5 have a high potential. When the address signal A6 has a low potential, the operation is the same as that of FIG.

On the other hand, when the fourth, fifth, and sixth address signals A4, A5, and A6 are all at low potential, the fifth and fifth inverters receiving the inverted high potential signal from the second and third inverters I2 and I3 may be used. The AND gate AND5 outputs a high potential signal.

Accordingly, as the OR gate OR outputs the first delay enable signal LE1 having the high potential by the output signal of the fifth AND gate AND5 having the high potential, the delay controller 10 delays one clock delay. Outputs a delay control signal.

In addition, when the sixth address signal A6 has a high potential, since the fifth AND gate AND5 receiving the sixth address signal A6 of the high potential outputs a high potential signal, the OR gate OR Outputs a high potential first delay enable signal LE1.

Accordingly, as the OR gate outputs the first delay enable signal LE1 to the high potential by the output signal of the fifth AND gate AND5 of high potential, the delay controller 10 delays one clock delay. Outputs a delay control signal.

That is, when an address signal that is not specified is input when the mode register signal MRS has a high potential, the malfunction prevention unit 100 outputs a first delay enable signal at a high potential.

As described in detail above, the present invention outputs a delay enable signal having a predetermined delay time when inputting an unspecified address signal, thereby preventing a malfunction of a circuit due to an unspecified address signal and improving system reliability. It is effective to improve.

Claims (2)

First, second, and third inverters inverting and outputting first, second, and third address signals respectively input from an external input pad; A first AND gate that receives a mode register signal, an output signal of the first and second inverters, and a third address signal and performs an AND operation on the mode register signal; A second AND gate receiving the mode register signal, the first and third inverter signals, and the second address signal, and performing an AND operation on the mode register signal; A third AND gate that receives the mode register signal, the output signal of the first inverter, and the second and third address signals to perform an AND operation on the mode register signal; An unspecified address signal input in a clock synchronizing circuit comprising a delay control unit for outputting a delay control signal for delaying a corresponding clock by a delay enable signal output from the first, second, and third AND gates. And a malfunction prevention unit for outputting a delay enable signal to have a predetermined delay time at a time. The gate driving circuit of claim 1, wherein the malfunction prevention unit comprises: a fourth AND gate that receives the mode register signal and the output signals of the second and third inverters and performs a logical AND operation on the output signal; A fifth AND gate that receives the mode register signal and the first address signal, and performs an AND operation on the mode register signal; And a logic sum gate configured to receive an output signal of the first, fourth, and fifth logical product gates and perform an OR operation to output a delay enable signal.