KR19990039344A - Automatic Self-Test Circuit Using Multiple Input Code Registers - Google Patents

Abstract

An automatic self test circuit using multiple input code registers is disclosed. The automatic self test circuit using the multiple input code register according to the present invention enters the self test mode in response to the automatic self test mode signal and the predetermined clock signal, and generates the predetermined control signal in the self test mode. A control means, a data generation means for generating a word background of data, and outputting a selected data background in response to a control signal, a memory core for storing the data background in an internal memory cell, a data background and memory output from the data generation means Comparing means for comparing the data background stored in the core, and outputting an error signal in accordance with the comparison result, input an internal signal of the M bit arbitrarily output from the automatic self-test control means, and inputs the input signal to the first selection signal Selectively respond in response First data selecting means, second data selecting means for inputting an internal signal of N bits arbitrarily output from the data generating means, and selectively outputting the input signal in response to the second selecting signal, and first data selecting means. And a multiple input code register for inputting the output of the second data selecting means and the output of the second data selecting means, and outputting the compressed result as a code to obtain the maximum probability of fault detection without increasing the size of the MISR. It can be effective.

Description

Automatic Self-Test Circuit Using Multiple Input Code Registers

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self test circuit of a semiconductor memory, and more particularly, to a self-test circuit (BIST) using a multiple input signature register (MISR).

Automatic self-test logic, or BIST circuitry, represents a logic circuit in hardware that implements a memory test algorithm used to test memory, and is primarily used to self-test embedded memory. In other words, such a BIST circuit is implemented in one chip, and the algorithm to be applied to the test is fixed in hardware, while the memory test pattern is performed in the chip, thereby reducing the routing overhead. Types of memory test algorithms include the MARCH-C (SARLE-C) algorithm or the SINGLE ORDERED ADDRESSING (SOA) algorithm. The MARCH-C algorithm detects address decoder faults, transition faults, transition coupling faults, and IDEMPOTENT faults, and tests the memory by counting up or down counting the addresses of the RAM. While the MARCH-C algorithm requires up / down counting of RAM addresses, the SOA algorithm uses one-way addressing as an algorithm for testing RAM using only up-counting of RAM addresses, thus simplifying address generation and control structure. It is characterized by.

In order to test the above-described BIST circuit, a multiple input signature register (MISR), a scan chain, or an ad hoc technique is used, and the scan circuit is not used in the entire circuit. Most use MISR.

FIG. 1 is a block diagram illustrating a conventional BIST logic circuit using a multiple input code register. The BIST controller 120, the data generator 140, the RAM core 160, the comparator 170, and the MISR 190 are illustrated in FIG. It is composed of

That is, when the BIST mode signal BIST_MODE is enabled, the BIST control unit 120 generates data backgrounds to be written in the RAM core 160 in response to a predetermined clock signal CLK that is normally input. Select from 140 and output to ram core 160. The comparator 170 compares the data background output from the data generator 140 to the RAM core 160 and the data background read from the RAM core 160 and compares the data background with the error. Determine the presence or absence That is, if the two data backgrounds are the same, the comparator 170 outputs a logic '0' to indicate that no error exists, and if the two data backgrounds are different, the comparator 170 outputs a logic '1' to indicate that an error exists. In addition, the MISR 190 is an 8-bit internal signals randomly extracted by the BIST controller 120 while the BIST logic circuit operates, that is, internal register values and 8-bit internally extracted by the data generator 140. The signals are extracted and the values are compressed in a predetermined way, and the compressed result is output as a sign. This sign is input to a comparator (not shown) outside the BIST circuit and detects whether there is a fault in the BIST circuit by comparing the predicted value of the pre-calculated sign value with the result value actually output from the MISR 190. do.

However, the conventional BIST circuit has a primary input pin such as an automatic self test mode signal (BIST_MODE) input pin and a test clock signal (CLK) input pin, an error (ERROR) output pin and a sign (SIGNATURE) compared to the internal number of gates. Test capability is very low due to the small number of primary output pins such as output pins. Therefore, the MISR for testing the conventional BIST circuit has a problem in that a bit having an appropriate size must be selected in consideration of the overhead in the region.

An object of the present invention is to provide an automatic self test circuit using multiple input code registers that can obtain the maximum test point without increasing the size of the MISR by adding an exclusive OR gate or multiplexer.

1 is a block diagram illustrating a conventional automatic self test circuit using a multiple input code register.

Figure 2 is a block diagram of one preferred embodiment for explaining an automatic self test circuit using multiple input code registers in accordance with the present invention.

In order to achieve the above object, the automatic self test circuit using the MISR according to the present invention enters the self test mode in response to the automatic self test mode signal and a predetermined clock signal, and generates a predetermined control signal in the self test mode. Automatic self-test control means, data generation means for generating a data background in word units, and outputting a selected data background in response to a control signal, a memory core for storing the data background in an internal memory cell, and data output from the data generation means. Comparing means for comparing the background and the data background stored in the memory core, and outputting an error signal corresponding to the result of the comparison, inputs an internal signal of M bits arbitrarily output from the automatic self-test control means, and inputs the input signal into the first signal. Optional in response to a selection signal First data selecting means for outputting, second data selecting means for inputting N-bit internal signals arbitrarily output from the data generating means, and selectively outputting the input signal in response to the second selecting signal, and first data selecting It is preferably composed of a multiple input code register which inputs the output of the means and the output of the second data selection means, compresses in a predetermined manner, and outputs the compressed result as a code.

Hereinafter, an automatic self test circuit using the MISR according to the present invention will be described with reference to the accompanying drawings.

2 is a circuit diagram of a preferred embodiment for explaining the automatic self-test circuit using the MISR according to the present invention, the BIST controller 220, the data generator 230, the first data selector 250, the second data The selector 260, the RAM core 240, the comparator 270, and the MISR 290, wherein the first data selector 250 includes a multiplexer 255 and exclusive oar gates 21 to 28. ), And the second data selector 260 includes a multiplexer 265 and exclusive oar gates 31 to 38.

When the BIST mode signal BIST_MODE for entering the self test mode for testing the RAM core 240 is enabled, the BIST controller 220 shown in FIG. 2 controls the predetermined signal in response to the input clock signal CLK. Generate a signal. The generated control signal is input to the data generator 230 and instructs the data generator 230 which data background to write to the ram core 240. The data generator 230 writes the selected data background among the data backgrounds to the designated address of the RAM core 240 in response to the control signal. The comparator 270 compares the data background written in the RAM core 240 with the data background generated by the data generator 230, and detects the presence or absence of an error according to the comparison result.

In addition, although the first data selector 250 is implemented with exclusive ora gates 21 to 28 and multiplexer 255 in the embodiment shown in FIG. 2, the first data selector 250 may be implemented using only a multiplexer or using an exclusive ora gate. It is possible. The exclusive OR gates 21 to 28 of the first data selector 250 are some of internal signals of arbitrary M bits output from the BIST controller 220, that is, internal registers constituting the BIST controller 220. The exclusive OR is received and the result of the exclusive OR is input to the multiplexer 255. The multiplexer 255 selectively outputs an input 2 / M bit signal, and the data output from the multiplexer 255 is input to the MISR 290 and used to detect the fault of the BIST controller 220. In addition, the exclusive OR gates 31 to 38 of the second data selector 260 exclusively OR any N-bit internal signals output from the data generator 230, and the result of the exclusive OR is multiplexer 265. Is entered. The multiplexer 265 selectively outputs the input 2 / N bit signal to the MISR 290, and the data output from the multiplexer 255 is input to the MISR 290 to determine whether the data generator 230 has a fault. It is used to detect. Accordingly, the MISR 290 compresses the predetermined values by inputting the values selectively output from the first data selecting unit 250 and the values selectively output from the second data selecting unit 260 and compressing the result in a predetermined manner. Is output as SIGNATURE. Such a sign is input to a comparator outside the BIST circuit and compared with a predicted value of a pre-simulated sign value, and by determining the result of the comparison, it is possible to detect whether a fault exists in the BIST circuit.

Hereinafter, the operation of the automatic self test circuit using the MISR according to the present invention will be described in detail.

As described above, the BIST circuit has a BIST mode signal (BIST_MODE) and a clock signal (CLK) as primary inputs, an error signal (ERROR) and a sign (SIGNATURE) as primary outputs, and are built in a chip. Test equipment can be minimized.

First, when the BIST mode signal BIST_MODE input to the BIST controller 220 maintains a low level, the chip including the BIST controller 220 and the RAM core 240 operates normally, and the BIST controller 220 is initialized. Set the error signal (ERROR) to zero. At this time, if the high level BIST mode signal BIST_MODE is input, the BIST circuit enters the self test mode and performs the BIST operation. That is, when the self test mode is not in the self test mode, the BIST mode signal BIST_MODE input to the BIST control unit 220 maintains a low level. When the BIST mode signal BIST_MODE is enabled at a high level, the BIST circuit enters the self test mode. Enter.

Here, when the BIST mode signal BIST_MODE is enabled, the BIST controller 220 generates a predetermined control signal for controlling the data generator 230 in response to the input clock signal CLK. The data generator 230 writes the selected data background into the RAM core 240 in response to the input control signal.

In general, a test algorithm such as MARCH-C uses a pattern called a data background (BACKGROUND) as a data pattern to be written / read in memory. This data background is output according to the word size, and has four data backgrounds when the word size is eight. For example, if the data pattern (PATTERN) of the data background (0) of the data background (0-3) is 01010101, the pattern bar (PATTERN BAR) becomes 10101010, and if the pattern of the data background (3) is 00000000, the pattern The bar becomes 11111111. Therefore, by repeatedly applying the test algorithm using the data pattern determined by the above-described data background, it is possible to detect a fault that may be caused by the influence between the cells of the RAM core.

That is, a part of the data backgrounds generated by the data generator 230 is selected in response to a control signal, and the selected data background is written to the designated address of the ram core 240. The comparator 270 compares the data background generated by the data generator 230 with the data background stored in the RAM core 240. At this time, the data background is compared in word units, and if the bits constituting each word are the same, the comparator 270 outputs a logic '0' to the error output terminal ERROR to indicate that no error exists in the RAM core 240. If any one of the bits constituting each word is different, it is determined that a fault exists in an internal cell of the RAM core 240, and a logic '1' is output to the error output terminal ERROR.

In addition, internal signals of M bits arbitrarily selected among the outputs of the registers constituting the BIST controller 220 are input to the exclusive OR gates 21 to 28 of the first data selector 250, respectively, and are exclusively ORed. The number of bits arbitrarily selected in the embodiment shown in FIG. 2 is 16 bits more than the 8-bit signal output from the conventional BIST circuit, and it is possible to variably implement the number of bits according to a design scheme. The 8-bit signals exclusively ORed at each of the exclusive OR gates 21 to 28 are input to the multiplexer 255 and selectively output in response to the first selection signal output from the BIST controller 220. Similarly, any N-bit signal of the outputs of the internal registers constituting the data generator 230 is input to the exclusive ora gates 31 to 38 of the second data selector 260, and is an exclusive ora gate 31. Exclusive AND outputs at ˜38) are input to the multiplexer 265. Referring to the embodiment illustrated in FIG. 2, the number of bits of a signal arbitrarily selected by the data generator 30 is 16 bits, and the number of bits of the signal may be varied as in the first data selector 250. The multiplexer 265 selectively outputs the input signals in response to the second selection signal output from the BIST controller 220. The outputs of the first data selector 250 and the second data selector 260 are input to flip-flops inside the MISR 290, respectively. That is, the MISR 290 is a register that can accept a large number of input signals. The MISR 290 is composed of a plurality of flip-flops and a plurality of exclusive OR gates to compress and store the input data, thus not requiring much memory capacity. . Data compressed in a predetermined manner in the MISR 290 is output as a sign through the output terminal. Such a sign is compared with a prediction value of a sign previously simulated by a comparison unit (not shown) outside the BIST circuit, and it is possible to detect whether a fault exists in the BIST circuit by determining whether the two sign values are the same. have. That is, if the sign value output from the MISR 290 is equal to the predicted sign value, it is determined that there is no fault in the BIST circuit, and when it is different, it is determined that there is a fault in the BIST circuit.

Unlike the conventional BIST circuit, the BIST circuit according to the present invention can obtain a signal of more than 8 bits from the BIST controller 220 or the data generator 230 by using a multiplexer or an exclusive OR gate. Is increased, and thus the probability of fault detection becomes high.

In the embodiment illustrated in FIG. 2, an exclusive OR gate and a multiplexer are used together, but as another embodiment, the BIST circuit may be implemented using only one of the multiplexer or the exclusive OR gate for each data selector 250 and 260. Do. In addition, the input / output may be varied by changing the sizes of the multiplexers used in the above-described embodiment. For example, you can increase test points further by using a 2 * 1 multiplexer, a 4 * 1 multiplexer, or a 12 * 4 multiplexer. Similarly, the fan-in size of the exclusive OR gate can be varied to increase or decrease the number of input signals, or the fan-out size can be varied to increase or decrease the number of output signals. .

According to the present invention, it is possible to obtain the maximum test points without increasing the size of the MISR, thereby improving the test capability to obtain the maximum probability of fault detection.

Claims (7)

Automatic self test control means for entering a self test mode in response to an automatic self test mode signal and a predetermined clock signal and generating a predetermined control signal in the self test mode; Data generating means for generating a data background in word units and outputting a selected data background in response to the control signal; A memory core for storing the data background in an internal memory cell; Comparison means for comparing the data background output from the data generating means with the data background stored in the memory core and outputting an error signal in accordance with the compared result; First data selecting means for inputting an internal signal of M bits arbitrarily output from the automatic self-test control means, and selectively outputting the input signal in response to a first selection signal; Second data selecting means for inputting an N-bit internal signal arbitrarily output from the data generating means, and selectively outputting the input signal in response to a second selection signal; And And a multiple input code register for inputting the output of the first data selecting means and the output of the second data selecting means to compress in a predetermined manner and outputting the compressed result as a code. Automatic self test circuit using resistors. The method of claim 1, wherein the first data selection means, And a multiplexer for selectively outputting the internal signals of the M bits in response to the first selection signal output from the automatic self test control means. The method of claim 1, wherein the first data selection means, And 2 / M exclusive OR means for exclusive ORing the internal signals of the M bits. The method of claim 1, wherein the first data selection means, 2 / M exclusive OR means for exclusive ORing the internal signals of the M bits; And And a multiplexer for selectively outputting the exclusive ORed signals in response to the first selection signal. The method of claim 2, wherein the second data selection means, And a multiplexer for selectively outputting the internal signals of the N bits in response to the second selection signal output from the automatic self test control means. The method of claim 2, wherein the second data selection means, And 2 / N exclusive OR means for exclusive ORing the internal signals of the N bits. The method of claim 2, wherein the second data selection means, 2 / N exclusive OR means for exclusive ORing N bits of internal signals of the data generating means; And And a multiplexer for selectively outputting the exclusive OR of 2 / N signals in response to the second selection signal.