KR19990037135A - Level conversion circuit - Google Patents

Abstract

The disclosed subject matter includes a first inverter driven by a first power supply voltage; A second inverter driven by a second power supply voltage; An n-channel MOS transistor having a drain connected to an output of the first inverter, a source connected to an input of the second inverter, and a gate to which the first power supply voltage is applied; A first diode in parallel with the n-channel MOS transistor, the anode having an anode connected to the output of the first inverter and a cathode connected to the input of the second inverter; And a load circuit for receiving the output of the second inverter and pulling up the input of the second inverter to the vicinity of the second power supply voltage; The above relates to a level conversion circuit for converting an amplitude level between a first power supply voltage and a ground voltage input to a first inverter into an amplitude level between a second power supply voltage and a ground voltage.

Description

Level conversion circuit

The present invention relates to a level converting circuit for producing an amplitude level of an output signal that is higher or lower than an amplitude level of an input signal, and more particularly to a level converting circuit operated using two or more power sources.

1 is a circuit diagram showing a conventional level conversion circuit. This level converting circuit is used in a decoder circuit or the like and needs to be operated at various voltages and at high speed. In particular, in a nonvolatile semiconductor device, when monitoring the threshold voltage of a memory cell having a floating gate, a voltage higher than the external power supply voltage and a voltage lower than the external power supply voltage are required. It may be necessary. The internal high and low voltages are made inside the circuit.

In Fig. 1, the external voltage Vcc is a voltage supplied from the outside, and the internal voltage Vpp is a voltage produced by power supply means (not shown) from Vcc.

The p-channel MOS transistor 21 and the n-channel MOS transistor 22 constitute a first inverter provided with Vcc as a power source and receiving an input signal from the internal terminal IN. The p-channel MOS transistor 25 and the n-channel MOS transistor 26 constitute a second inverter provided with Vpp as a power source and receiving an input signal from the node F. The n-channel MOS transistor 23 transfers the output of the first inverter to the input of the second inverter and prevents current from flowing from the node F at the Vpp level to the node E at the Vcc level. The p-channel MOS transistor 27 accepts the output of the second inverter and pulls up the input of the second inverter to the Vpp level in accordance with this output.

Next, the operation of this level conversion circuit will be described. First, the case where the external power supply voltage Vcc and the internal voltage Vpp have the same potential will be described. The potential level of the input signal applied to the input terminal IN varies between ground potential GND (hereinafter, defined as ground potential GND as 0 V) and Vcc.

When the potential of the input terminal IN changes from Vcc to 0V, the potential of the output node E of the first inverter composed of the transistors 21 and 22 becomes Vcc. The potential of the node F increases through the n-channel MOS transistor 23 to the level of Vcc-Vtn shown in FIG. In addition, Vtn is a threshold value when the back-gate characteristic of the transistor 23 is considered. By the "H" level output of the node F, the potential of the output node OUT of the second inverter composed of the transistors 25 and 26 drops from Vpp to 0V. As the output node OUT changes, the p-channel MOS transistor 27 turns on, raising the node F to the Vpp level.

When the potential of the input terminal IN is changed from 0V to Vcc, the potential of the output node E of the first inverter drops to 0V. Accordingly, the potential of the node F starts to drop to 0V via the n-channel MOS transistor 23. By the "L" level output of the node F, the potential of the output node OUT of the second inverter rises from 0V to Vpp. By the change of the output node OUT, the p-channel MOS transistor 27 is turned off.

When the voltage Vpp is higher than the voltage Vcc, the voltage Vcc and the voltage Vpp are initially at the same level, and after the state is determined as described above, the voltage Vpp can be increased to a high voltage.

The gate potential of the n-channel MOS transistor 23 is at the Vcc level, the potential of the drain connected to the node E is at the Vcc level, and the potential of the source connected to the node F is at the Vpp level. Therefore, it is possible to prevent the through current from the node F at a potential higher than Vcc to the node E at the Vcc level.

Next, Fig. 3 is a circuit diagram showing the level conversion circuit disclosed in Japanese Patent Laid-Open No. 5-304462 (1993). The level conversion circuit includes a p-channel MOS transistor 31 and an n-channel MOS transistor 32 constituting the first inverter, and a p-channel MOS transistor 35 and n-channel constituting the second inverter. MOS transistor 36, a p-channel MOS transistor 37 that accepts the output of the second inverter and supplies Vpp to the input of the second inverter in response to the output, and the drains of these transistors 31 and 32. And a diode 38 connected therebetween.

When the potential of the input terminal IN changes from Vcc to 0V, the potential of the output node G of the first inverter composed of the transistors 31 and 32 rises to the level of Vcc-Vfb, as shown in FIG. . On the other hand, Vfb is the forward voltage of the diode 38. By the "H" level output of the node G, the potential of the output node OUT of the second inverter composed of the transistors 35 and 36 drops from Vpp to 0V. Due to the change of the output node OUT, the p-channel MOS transistor 37 is turned on to raise the node I to the Vpp level.

When the potential of the input terminal IN changes from 0V to Vcc, the potential of the output node G of the first inverter decreases to 0V. By the "L" level output of the node G, the potential of the output node OUT of the second inverter rises to Vpp. By the change of this output node OUT, the p-channel MOS transistor 37 is turned off.

In the level conversion circuit of Fig. 3, there is no normal operating current flowing from Vpp to Vcc and a normal operating current flowing from Vpp to ground potential GND, but there is a normal operating current flowing from Vpp to ground potential GND.

The conventional level conversion circuit is constructed as described above. In the level conversion circuit of Fig. 1, when the external power supply voltage Vcc and the internal voltage Vpp have the same value, the input amplitude (the amplitude of the node F) driving the second inverter of the output stage is the amplitude between Vcc-Vtn and the ground potential GND. Level. Since Vtn is a threshold value in consideration of the back-gate characteristic of the transistor 23, when operating at a low voltage of, for example, Vcc = 2V, Vcc-Vtn is about 1V. For this reason, the input amplitude of the second inverter becomes an amplitude level of about 1V. Therefore, in the level conversion circuit of FIG. 1, there is a problem that the input amplitude of the second inverter of the output stage cannot have sufficient margin.

In the level converting circuit of FIG. 3, the margin of the input amplitude can be increased more than the level converting circuit of FIG. 1, but when the high voltage is selected by the second inverter of the output terminal, the external power supply voltage Vcc is changed to the ground potential GND. Normal operating current exists. Thus, there is a problem that the current consumption increases.

1 and 3, when the voltage Vpp is lower than the external power supply voltage Vcc, a normal operating current from Vcc to Vpp exists. Thus, there is a problem that the current consumption increases.

An object of the present invention is to provide a level converting circuit capable of realizing a reduction in current consumption and an increase in an external power supply operating margin.

1 is a circuit diagram showing a conventional level conversion circuit.

2 is a graph showing a voltage input to a second inverter serving as an output stage inverter,

3 is a circuit diagram showing another conventional level converting circuit;

4 is a circuit diagram showing a level converting circuit in a first preferred embodiment according to the present invention;

FIG. 5 is a sectional view showing a diode used in the level converting circuit of FIG.

Fig. 6 is a circuit diagram showing a level converting circuit in a second preferred embodiment according to the present invention.

According to the present invention, the level conversion circuit,

A first inverter driven by a first power supply voltage;

A second inverter driven by a second power supply voltage;

An n-channel MOS transistor having a drain connected to an output of the first inverter, a source connected to an input of the second inverter, and a gate to which the first power supply voltage is applied;

A first diode in parallel with the n-channel MOS transistor, the anode having an anode connected to the output of the first inverter and a cathode connected to the input of the second inverter; And

And a load circuit for receiving the output of the second inverter and pulling up the input of the second inverter to the vicinity of the second power supply voltage.

In the above, the level converting circuit converts the amplitude level between the first power supply voltage and the ground voltage to be input to the first inverter to the amplitude level between the second power supply voltage and the ground voltage.

Thus, the output amplitude of the first inverter operating between the first power supply voltage and the ground voltage is transmitted to the input of the second inverter at the output terminal via the first diode, thereby providing a second output of the second inverter at the output terminal. The operating margin of the inverter can be increased. In addition, the steady current flowing from the first power supply voltage to the ground voltage, the second power supply voltage to the ground voltage, and the second power supply voltage to the first power supply voltage can be prevented.

The invention is explained in more detail in connection with the accompanying drawings.

First embodiment

Next, embodiments according to the present invention will be described in detail with reference to the drawings.

4 is a circuit diagram showing a level converting circuit in the first preferred embodiment according to the present invention. The external power supply voltage Vcc serving as the first power supply voltage is a voltage supplied from the outside, and the internal voltage Vpp is a voltage generated from Vcc by the power supply means (not shown). On the other hand, both Vcc and Vpp are constant voltages.

The gate is connected to the input terminal IN, the drain is connected to the node A, the p-channel MOS transistor 1 to which the voltage Vcc is applied to the source and the well, the gate is connected to the input terminal IN, and the drain is connected to the node A. The n-channel MOS transistor 2 connected and whose source is grounded constitutes a first inverter which becomes an input terminal inverter.

A gate is connected to node B, a drain is connected to output terminal OUT, a p-channel MOS transistor 5 having a voltage Vpp applied to the source and the well, a gate is connected to node B, and a drain is connected to output terminal OUT. An n-channel MOS transistor 6 connected and whose source is grounded constitutes a second inverter which becomes an output stage inverter.

The n-channel MOS transistor 3, whose drain is connected to the output node A of the first inverter, the source is connected to the input node B of the second inverter, and the voltage Vcc is applied to the gate, The output is sent to the input of the second inverter, and the current flowing from the node B at the Vpp level to the node A at the Vcc level is blocked.

The diode 4, whose anode is connected to the output node A of the first inverter and whose cathode is connected to the input node B of the second inverter, delivers the output of the first inverter to the input of the second inverter.

The p-channel MOS transistor 7 constituting the load circuit accommodates the output of the second inverter and pulls up the input of the second inverter to near the Vpp level in response to this output.

5 is a cross-sectional view of the diode 4 used in the level conversion circuit of FIG. The diode 4 includes a first n-type diffusion layer 11, a p-type diffusion layer 12 to be an anode formed in the n-type diffusion layer 11, and a cathode to be formed in the p-type diffusion layer 12. It consists of the n-type diffused layer 13 of two. The p-type diffusion layer 12 is connected to the node A which is the output of the first inverter, and the n-type diffusion layer 13 is connected to the node B which is the input of the second inverter. In addition, a power supply voltage Vcc is applied to the n-type diffusion layer 11.

Next, the operation of the level converting circuit of the present embodiment will be described. First, the case where the external power supply voltage Vcc and the internal voltage Vpp have the same potential will be described. The potential level of the input signal applied to the input terminal IN varies between ground potential GND (hereinafter, ground potential GND is defined as 0 V) and Vcc.

When the potential of the input terminal IN changes from Vcc to 0V, the potential of the output node A of the first inverter composed of the transistors 1 and 2 is turned on with the transistor 1 turned on and the transistor 2 turned off. Therefore, it becomes Vcc.

By the "H" level output of the node A, the potential of the output node OUT of the second inverter composed of the transistors 5 and 6 is turned on because the transistor 5 is turned off and the transistor 6 is turned on. Drop from Vpp to 0V. Due to the change of the output node OUT, the p-channel MOS transistor 7 is turned on, whereby the node B rises to the Vpp level.

By setting the threshold of the second inverter to a threshold lower than Vcc-Vfb, the amplitude level of the node B between Vcc-Vfb and 0V can be transmitted to the output terminal.

When the potential of the node A rises to Vcc, the p-type diffusion layer 12 of the diode 4 is charged to Vcc. As a result, a forward bias is formed between the p-type diffusion layer 12 and the n-type diffusion layer 13, and the node B is charged up to Vcc-Vfb. The n-type diffusion layer 11 is a diffusion layer region formed by suppressing the current flowing to the substrate when the p-type diffusion layer 12 is filled with Vcc, which is pulled up to the voltage Vcc.

When the potential of the input terminal IN changes from 0 V to Vcc, the transistor 1 is turned off and the transistor 2 is turned on, so that the output node of the first inverter composed of the transistors 1 and 2 is The potential of A drops to 0V.

Corresponding to this, the potential of the node B begins to drop to 0V via the n-channel MOS transistor 3. When the potential of the input terminal IN was 0 V, the potential of the node B was at the "H" level. For this reason, when the potential of the input terminal IN changes to Vcc and the node A changes to the "L" level, the reverse voltage is applied to the diode 4. Therefore, the potential of the node B is brought to the "L" level by the operation of only the transistor 3.

By the "L" level output of the node B, the transistor 5 is turned on and the transistor 6 is turned off. Thus, the potential of the output node OUT of the second inverter composed of the transistors 5, 6 rises from 0V to Vpp. By the change of this output node OUT, the p-channel transistor 7 is turned off.

The above operations are performed when the voltages Vcc and Vpp are at the same potential, but when the voltage Vpp is higher than the voltage Vcc, the voltage Vcc and the voltage Vpp are set at the same level to determine the same state as above, and then the voltage Vpp is boosted to a high voltage. can do. As a result, the first and second inverters can be selectively driven.

When the potential of the input terminal IN is 0V, the path of the current flowing from Vcc to the ground potential GND is shorted by the n-channel transistor 2, and the path of the current flowing from Vpp to the ground potential GND is a p-channel MOS transistor ( 5) and the n-channel MOS transistor 2 are short-circuited. The path of the current flowing from Vpp to Vcc is short-circuited by the n-channel MOS transistor 3 and the diode 4.

When the potential of the input terminal IN is Vcc, the path of the current flowing from Vcc to the ground potential GND is shorted by the p-channel MOS transistor 1, and the path of the current flowing from Vpp to the ground potential GND is the p-channel MOS transistor. (7) and the n-channel MOS transistor 6 are short-circuited. The path of the current flowing from Vpp to Vcc is short-circuited by the p-channel MOS transistor 7.

Therefore, in this embodiment, by providing the diode 4, the input amplitude (amplitude of the node B) for driving the second inverter at the output stage can be the amplitude level between Vcc-Vfb and the ground potential GND. For this reason, the operating margin of the second inverter can be increased in comparison with the level converting circuit of FIG.

The steady-state current flowing from Vcc to ground potential GND, Vpp to ground potential GND, and Vpp to Vcc can be prevented. Therefore, the current consumption can be reduced as compared with the level conversion circuit of FIG.

2nd Embodiment

FIG. 6 is a circuit diagram showing a level conversion circuit in a second preferred embodiment according to the present invention, wherein the same components as in FIG. 4 are denoted by the same reference numerals.

The diode 8, whose anode is connected to the drain of the p-channel MOS transistor 7, and whose cathode is connected to the input node C of the second inverter, constitutes a load circuit together with the transistor 7. Pull up to Vpp-Vfb. This diode 8 has the same configuration as the diode 4. However, the internal voltage Vpp is applied to the first n-type diffusion layer 11 of the diode 8.

Next, the operation of the level converting circuit of the present embodiment will be described. First, the case where the external power supply voltage Vcc and the internal voltage Vpp have the same potential will be described.

When the potential of the input terminal IN changes from Vcc to 0V, since the transistor 1 is turned on and the transistor 2 is turned off, the output node A of the first inverter composed of the transistors 1, 2 is The potential of becomes Vcc.

By the "H" level output of the node A, the forward voltage is applied to the diode 4. As a result, the potential of the node C rises to Vcc-Vfb.

By the " H " level output of the node C, the potential of the output node OUT of the second inverter composed of the transistors 5 and 6 is turned on because the transistor 5 is turned off and the transistor 6 is turned on. Drop from Vpp to 0V. This change in the output node OUT causes the p-channel MOS transistor 7 to be turned on, thereby raising the node D to the Vpp level. The diode 8 outputs to the node C a value lower by Vfb than the voltage level of the node D.

By setting the threshold of the second inverter to a threshold lower than Vcc-Vfb, the amplitude level of the node C between Vcc-Vfb and 0V can be transmitted to the output terminal.

When the potential of the input terminal IN changes from 0 V to Vcc, the transistor 1 is turned off and the transistor 2 is turned on, so that the output node of the first inverter composed of the transistors 1 and 2 is The potential of A drops to 0V.

Corresponding to this, the potential of the node C begins to drop to 0V via the n-channel MOS transistor 3. When the potential of the input terminal IN was 0 V, the potential of the node C was at the "H" level. For this reason, when the potential of the input terminal IN changes to Vcc and the node A changes to the "L" level, the reverse voltage is applied to the diode 4. Therefore, the potential of the node C is brought to the "L" level by the operation of only the transistor 3.

By the "L" level output of the node C, the transistor 5 is turned on and the transistor 6 is turned off. Thus, the potential of the output node OUT of the second inverter composed of the transistors 5, 6 rises from 0V to Vpp. By the change of this output node OUT, the p-channel MOS transistor 7 is turned off.

The above operations are performed when the voltages Vcc and Vpp are at the same potential, but when the voltage Vpp is higher than the voltage Vcc, the voltage Vcc and the voltage Vpp are set at the same level to determine the same state as above, and then the voltage Vpp is boosted to a high voltage. can do. As a result, the first and second inverters can be selectively driven. Moreover, even when the voltage Vpp is made lower than the voltage Vcc, it can drive.

When the potential of the input terminal IN is 0V, the path of the current flowing from Vcc to the ground potential GND is shorted by the n-channel MOS transistor 2, and the path of the current flowing from Vpp to the ground potential GND is a p-channel MOS transistor. (5) and the n-channel MOS transistor 2 are short-circuited. The path of the current flowing from Vpp to Vcc is short-circuited by the n-channel MOS transistor 3 and the diode 4. Moreover, the path of the current flowing from Vcc to Vpp is shorted by diode 8.

When the potential of the input terminal IN is Vcc, the path of the current flowing from Vcc to the ground potential GND is shorted by the p-channel MOS transistor 1, and the path of the current flowing from Vpp to the ground potential GND is the p-channel MOS transistor. (7) and the n-channel MOS transistor 6 are short-circuited. The path of the current flowing from Vpp to Vcc is short-circuited by the p-channel MOS transistor 7. Moreover, the path of the current flowing from Vcc to Vpp is shorted by the diode 8.

Therefore, in this embodiment, an effect similar to that of the first embodiment can be obtained. In addition, in the first embodiment and the present embodiment, when the voltage Vpp is higher than the voltage Vcc, when the voltage is lower than the voltage Vcc, and when the voltage is the same potential as the voltage Vcc, it can operate anywhere. However, in the level conversion circuit of the first embodiment, when the voltage Vpp is lower than the voltage Vcc, there is a normal operating current flowing from Vcc to Vpp.

In contrast, in the level conversion circuit of the present embodiment, the normal operating current flowing from Vcc to Vpp can be prevented.

Although the present invention has been described in connection with specific embodiments for complete and clear disclosure, the appended claims are not limited, and all modifications and variations belonging to the basic spirit described above by those skilled in the art are applied. can do.

As claimed in claim 1, according to the present invention, the output amplitude of the first inverter operating between the first power supply voltage and the ground voltage is inputted by the second inverter of the output terminal via the first diode. By transmitting to, the operating margin of the second inverter of the output terminal can be increased. In addition, the steady current flowing from the first power supply voltage to the ground voltage, the second power supply voltage to the ground voltage, and the second power supply voltage to the first power supply voltage can be prevented. In this way, the current consumption can be reduced.

Further, as claimed in claim 3, by providing the second diode, it is possible to prevent the steady current flowing from the second power supply voltage to the first power supply voltage. By doing this, the current consumption can be reduced.

Claims (5)

A first inverter driven by a first power supply voltage; A second inverter driven by a second power supply voltage; An n-channel MOS transistor having a drain connected to an output of the first inverter, a source connected to an input of the second inverter, and a gate to which the first power supply voltage is applied; A first diode in parallel with the n-channel MOS transistor, the anode having an anode connected to the output of the first inverter and a cathode connected to the input of the second inverter; And A load circuit for receiving the output of the second inverter and pulling up the input of the second inverter to the vicinity of the second power supply voltage; The level conversion circuit for converting an amplitude level between the first power supply voltage and the ground voltage input to the first inverter into an amplitude level between the second power supply voltage and the ground voltage. The load circuit of claim 1, wherein the load circuit includes a source and a well to which the second power supply voltage is applied, a drain connected to an input of the second inverter, and a gate connected to an output of the second inverter. And a p-channel MOS transistor. 2. The p-channel MOS transistor of claim 1, wherein the load circuit includes a source and a well to which the second power supply voltage is applied, a gate connected to an output of the second inverter, and the p-channel MOS transistor. And a second diode having an anode connected to the drain of the transistor and a cathode connected to the input of the second inverter. The first n-type diffusion layer, a p-type diffusion layer to be an anode formed in the first n-type diffusion layer, and a second n to be a cathode formed in the p-type diffusion layer. A type diffusion layer; And said first power supply voltage is applied to said first diode. The second n diode according to claim 3, wherein the second diode is a first n-type diffusion layer, a p-type diffusion layer to be an anode formed in the first n-type diffusion layer, and a second n to be a cathode formed in the p-type diffusion layer. A type diffusion layer; And said second power supply voltage is applied to said second diode.