KR19990036270A - Memory associated system and frame buffers, and systems and methods of using the same - Google Patents

Abstract

Processing system 100 includes a federated memory system 105 having a system memory region 109 and a plurality of frame buffer regions 110/111. The central processing unit 101 has an associated system memory 105 in its address area and allows to update the display data in the first selected area from the frame buffer areas 110/111, while the frame buffer area ( And display data from the second selected area of 110/111 to provide data for refreshing the display screen of the associated display device.

Description

Memory associated system and frame buffers, and systems and methods of using the same

Conventional processing systems with video / graphical display capabilities include a central processing unit (CPU), a display controller connected to the CPU by a CPU local bus (directly and / or via core logic circuitry), System memory coupled to the CPU local bus via a core logic circuit, frame buffer memory coupled to the display controller via a peripheral local bus (eg, PCI), peripheral circuitry (eg, clock drivers and signal converters, display driver circuits), and It includes a display unit.

The CPU is the system master and generally provides overall system control in relation to the software operating system (OS). First of all, the CPU communicates with the system memory through the core logic circuitry to hold instructions and data necessary for program execution. Typically, the core logic circuit consists of two to seven chips, one or more chips being "address intensive" and one or more other chips being "data path intensive". . The CPU also controls, via the display controller, the content of the graphical image to be displayed on the display unit, in accordance with user instructions and program instructions.

For example, a display controller, such as a video graphics structure (VGA) controller, generally interfaces the CPU with the display driver circuitry, exchanges graphics and / or video data between the frame buffer and the CPU, and updates the display data and displays the screen. Manages display when refreshed, controls frame buffer memory operations, and performs additional basic processing on graphics or video data. For example, the display controller can include the performance of performing operations such as line drawing and polygon fill. The display controller is in most cases a slave to the CPU.

In general, the CPU itself provides the display data necessary for updating the display screen when a change in the displayed image (data) is required. Because of the cost burden on the CPU (along with the limitation of bandwidth on the PCI bus or other bus) and the limitation on the size of the display controller write buffer, the updated display data is created and stored in system memory. When the display write buffer has capacity and CPU time is useful, the CPU reads the required information (usually the address for the frame buffer and pixel data) from the system memory, via the core logic circuitry and the CPU local bus, Data is written to the display controller's write buffer via the core logic circuit and the PCI bus. During display update, a plurality of CPU cycles (ie, read and write cycles) are required to write each word of data to the display controller. This is a serious drawback when the efficient use of CPU cycles is crucial to faster processing speeds and expanded performance, not to mention not using a PCI (local) bus for other operations. The display update rate is also limited by the depth of the write buffer on the controller and the bandwidth of the PCI local bus.

Another problem commonly found in the conventional processing / display system architecture described above is unused memory space. Currently, typical system memory is 4 to 8 megabytes in size. In the foreseeable future, system memory may grow in size up to 16 megabytes as new operating systems are developed. In conventional personal computers, system memory, also known as main memory, is normally composed of dynamic RAM devices (DRAMs). Commercial DRAM consists of only four times its density (i.e. 256 KB, 1 MB, 4 MB), and the maximum size of each addressable storage location is 16 widths. Thus, even if the total capacity of each individual device is not used, a plurality of chips are normally required to form system memory (64 to 72 bits wide for today's PC systems). For example, to support a 64-bit wide data bus, four parallel units of 16 bits are required per bank. Depending on which of the 256 KB or 1 MB devices is used, each bank has a corresponding capacity of 1 MB or 4 MB, respectively. For example, if an intermediate capacity of 3 MB is required per bank, a larger increment must be chosen and some memory is unused. This problem is further illustrated by the fact that the CPU does not necessarily store data adjacent to each other in memory for operational efficiency, so that the use of system memory space is also less than optimal.

Sub-optimal use of memory space is also found in conventional frame buffer configurations. The frame buffer typically does not need to be large (typically in the range of 0.8 to 1.25 MB), but needs to be the bandwidth required for display refresh. For example, suppose the frame buffer supports a 64-bit wide data bus for the display controller. To support this bus, four parallel 16-bit DRAMs are required. If a conventional 256KB of 16-bit DRAM is used, the frame buffer has a total capacity of 2 MB. Thus, even for the largest frame buffer (i.e., 1.25 MB), a significant amount of memory space is unused.

Thus, there is a need for improved apparatus, systems, and methods for more efficiently configuring and managing memory in processing and display systems. In particular, there is a need for a technique for preserving CPU operating cycles during display updates. Advantageously, this technique frees the CPU to perform other important operations, thus improving overall system performance. In addition, there is a need for circuits, systems, and methods for more efficiently configuring and managing the system and frame buffer memory required for display processing systems. In particular, the systems and methods of such devices should minimize the number of devices required to construct such memory. As a result, a more compact, cheap and efficient system structure can be realized. These memories, in particular DRAM, may be multiplexed address / RAS-CAS type systems, or multiple clock / synchronous DRAMs (now considered in the industry), or synchronous graphics DRAMs or DRAMs with specific interfaces.

TECHNICAL FIELD The present invention relates generally to data processing systems including display subsystems, and to memory incorporating the system and frame buffers, and systems and methods of using the same.

1 is a functional block diagram of a portion of a processing system for generating and controlling display data in accordance with the principles of the present invention.

2 is a functional block diagram of one of the possible configurations of the associated memory shown in FIG.

3 is a functional block diagram of an integrated display controller / unified memory device suitable for one application in the system of FIG.

The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be more readily understood. Additional features and advantages of the present invention which form the subject of the claims of the present invention are described below. Those skilled in the art will appreciate that the disclosed concepts and specific embodiments can be readily used as a basis for modifying and designing other structures for achieving the same object of the present invention. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the invention as claimed in the appended claims.

In accordance with the principles of the present invention, a processing system including a memory system incorporating a system and a frame buffer is disclosed. In a federated memory system, frame buffer memory and system memory are allocated within a single integrated circuit or a single bank of integrated circuits. This is in contrast to currently available display control systems, where the frame buffer memory is separate, separate from the system memory, and must interface with the rest of the system through the display controller. In accordance with the principles of the present invention, the frame buffer area of the associated memory comprises at least two physical memory blocks. One block is used for screen refresh by the display controller or the CPU. The second block is used for display data update. Advantageously, the system CPU can update data in the update information frame buffer block by writing directly to the desired location. Moreover, these updates can be made to the update buffer while the refresh buffer provides data for refreshing its display screen. This means that in order to perform an update, a currently useful system in which the CPU must first store / retrieve update data in system memory, read the data from system memory, and then write the data to the display controller's write buffer. In contrast to that. The principle of the present invention not only protects valuable system operating cycles since reads can be made directly from the refresh buffer, but also enables the removal of the write buffer in the display controller.

In accordance with a first embodiment of the present invention, a processing system is described that includes an associated system memory having a system memory area and a plurality of frame buffer areas. Such a processing system further includes a central processing unit, wherein the associated memory is placed within the address space of the central processing unit. The central processing unit may be operable to update display data in the first selected area of the frame buffer area, while display data from the second selected area of the frame buffer area is for refreshing the display screen of the associated display device. Provide data.

According to a second embodiment of the present invention, there is provided a processing system comprising an associated memory comprising at least one system memory space and first and second frame buffer spaces. Circuitry for updating display data stored in the first frame buffer space is provided as part of the processing system. Circuitry is also provided for retrieving display data stored in a second frame buffer space for producing a corresponding display substantially simultaneously with updating of display data stored in the first frame buffer space. In addition, the processing system includes circuitry for retrieving display data stored in the first frame buffer space to produce a corresponding updated display.

Additional processing systems implement the present invention. The processing system includes a central processing unit, a CPU local bus coupled to the central processing unit, a core logic circuit coupled to the CPU local bus, a display controller coupled to the core logic circuit and the aforementioned bus, and a system memory coupled to the core logic circuit. An associated memory system provides an area and a number of frame buffer areas.

The principles of the present invention are also implemented in a memory management method. In one of these methods, the associated memory is divided into system memory and first and second frame buffer memories. The display data stored in the first frame buffer is updated while the display data stored in the second frame buffer is used to generate the corresponding display. When the update of the data in the first frame buffer ends, the data stored in the first frame buffer is retrieved to produce the corresponding updated display.

Systems implementing the principles of the present invention have significant advantages over those of the prior art. In particular, during a display update that frees the CPU to perform other important operations, this principle can save CPU operating cycles, thereby improving overall system performance. Additionally, the federated system memory of the present invention allows for more efficient configuration and operation of the memory space required for processing / display systems. In particular, by allocating system memory and frame buffer memory, unused memory space can be minimized, resulting in a more concise, inexpensive, and efficient system.

Although current PC systems do not include direct communication between the CPU local bus and the graphics controller (all communication between the CPU and the graphics controller today is through the PCI local bus only), this will change in the future. When processors such as P6 (Intel) add graphics / video / NSP audio functionality, there is a need for direct communication between the CPU and the graphics controller via the CPU local bus. This is similar to a multitasking situation.

For a more complete understanding of the invention and its advantages, reference is made to the following description in connection with the following figures.

The principles of the present invention and their advantages will be best understood with reference to the illustration shown in Figs. 1 to 3, wherein like numerals represent like parts.

1 is a high level functional block diagram of a portion of a processing system 100 that controls the display of graphical and / or video data. System 100 includes central processing unit 101, CPU local bus 102, core logic circuit 103, display controller 104, federated system / display memory 105, digital-to-analog converter (DAC) 106. And a display device 107.

The CPU 101 is a "master" that controls the overall operation of the system 100. First of all, the CPU 101 performs various data processing functions and determines the contents of the graphic data to be displayed on the display unit 107 in accordance with the execution of user commands and / or application software. The CPU 101 may be a general purpose microprocessor such as, for example, an Intel Pentium class microprocessor and the like used in a commercial personal computer. CPU 101 communicates with the rest of system 100 via CPU local bus 102, which may be, for example, a particular bus or a general bus (common in the industry).

Since the system memory and frame buffer memory are allocated within a single integrated circuit or bank of integrated circuits, the memory 105 is a "associative" memory system. This is in contrast to the prior art system described above, wherein the frame buffer memory is separate and separate from the system memory and interfaces with the rest of the system via the display controller.

The core logic circuit 103 is controlled by the CPU 101 to control the exchange of data, addresses, and instructions between the CPU 101, the display controller 104, and the associated memory 105. The core logic circuit 103 may be any one of a number of commercially available core logic circuit chip sets designed to be compatible with the rest of the system, particularly the CPU 101. In the illustrated system, one or more core logic circuit chips, such as chip 112, are "address related", while one or more core logic circuit chips, such as chip 114 of FIG. 1, are "data related". The CPU 101 may communicate directly with the core logic circuit 103 or via an external (L2) cache 115. It should be noted that the CPU 101 may also include an embedded (L1) cache. L2 cache 115 may be, for example, 256 KB of high speed SRAM device (s).

Display controller 104 can be any of a number of commercially available VGA display controllers. The display controller 104 may receive data, commands and / or addresses from the CPU 101 via the core logic circuit 103 or directly from the CPU 101 via the CPU local bus 102. have. Data, commands and addresses are exchanged between the display controller 104 and the associated memory 105 via the core logic circuit 103. Moreover, addresses and instructions may be exchanged between the core logic circuit 103 and the display controller 104 via a local bus, such as a PCI local bus. In general, display controller 104 controls screen refresh and executes a limited number of graphics functions, such as line drawing, polygon filling, color space conversion, display data interpolation and zooming display, and video streaming. And do other subsidiary tasks such as power management. Video data may be input directly to the display controller 104.

The digital analog converter 106 receives digital data from the controller 104 and accordingly outputs analog data to drive the display device 107. In the illustrated embodiment, the DAC 106 is integrated with the display controller 104 into a single chip. Depending on the particular implementation of system 100, to specify many options, DAC 106 may include color palettes, YUV-RGB format conversion circuits, and / or X- and Y- zooming circuits. The display device 107 may be, for example, a CRT unit, a liquid crystal display device, an electroluminescent display device, a plasma display device, or another type of display device for displaying an image in a plurality of pixels on a screen. In other embodiments, display device 107 may be another type of output device, such as a laser printer or similar document viewing / printing device.

In accordance with the principles of the present invention, the associated memory 105 implements the system memory 109 and the display frame buffer, which is divided into frame buffer block A 110 and frame buffer block B 111. System memory 109 is preferably a traditional system memory that stores data, addresses, and instructions under the instructions of CPU 101, as required to execute various processing functions and application programs. The double block frame buffer 110/111 resides in the same CPU address space as the system memory 109. Preferably, each frame buffer block 110 and 111 is an allocated contiguous block (set) of addresses in the CPU 101 address space, although the address blocks assigned to the two banks may or may not be adjacent to each other. . It should be noted that the address-distributed frame buffer banks A and B may vary depending on the division of the association memory 105 by the OS executed by the CPU 101. Each frame buffer block 110 and 111 maps one pixel to the screen of the display device 107, as is done in a conventional frame buffer.

During display generation and update, each frame buffer bank 110/111 maintains pixel data corresponding to the display screen. One memory bank 110/111 is a "display memory" that is accessed by the display controller 104 (using the address generated by the display controller 104) to refresh the screen on the display device 107. Or "refresh memory". The CPU 101 can also directly access the frame buffer banks 110/111 serving as the current display memory and refresh the screen itself of the display device 107. In this case, the display controller 104 simply acts as a pipeline for pixel data that is bypassed or sent to the DAC 106 and the display device 107. Advantageously, all display data resides in one adjacent "refresh block" in the refresh memory, which allows the display controller to access the stored refresh data with minimal interference of the CPU 101 (if the display data If it is to be stored in a non-adjacent area, more CPU intervention is required to command the display controller for this data). Since 75% of the total display processing time is used for screen refresh, the ability to move the display refresh to the display controller can substantially improve system performance since the CPU 101 is effectively configured for other tasks. have.

At the same time, other frame buffer banks 110/111 are used exclusively for screen update. The CPU 101 updates the display data in the refresh frame buffer block 110/111 by writing directly to the position holding the changed data. The prior art multi-step process of writing to system memory, reading from system memory when the display controller write buffer is valid, and then writing to the frame buffer is thus reduced to a series of direct write operations for the frame buffer update block. . Thus, updating each word of pixel data in the "screen update" bank is done using only one CPU period for each word of data being updated (such as the width of the data bus and / or the number of data bits). According to this coefficient, the CPU 101 can write to the associative memory 105 at once and each word that is changed can represent one or more pixels). That is, if multiple data words are being updated in the update frame buffer bank, the number of CPU clock cycles required to perform the screen update is divided into two.

Once the screen update is completed, the frame memory bank 110/111 currently operating as the display memory and the frame buffer bank 110/111 currently operating as the screen refresh memory switch roles. For example, if block A was used to refresh the screen, while an update to the display was realized through writing to block B, then when the update to block B ends, block A becomes an update block and block B It becomes a screen update block.

In a system such as system 100 implementing the principles of the present invention, the display controller write buffer may even be removed. Display refresh in this case can be performed by simply retrieving data directly from the refresh frame buffer block 110/111, and can be pipelined through the display controller 104 to the display unit 107. In this case, the refresh buffer essentially replaces the display controller write buffer.

The memory 105 associated with the system and the frame buffer may be configured as a single chip or as a subsystem of multiple chips (devices). This subsystem 200 is shown in FIG. System 200 is comprised of multiple memory banks 201. When used in the system 100, each bank 201a is connected to the core logic circuit 103 by an address bus 202, a data bus 203 and a control bus 204. Bank 201 is an address bus 202 that simultaneously provides column and row address bits to bank 201 and may operate in a non-multiplexed addressing structure. Optionally, bank 201 has a multiplexed (RAS / CAS) structure and " asynchronous DRAM structure " (in addition to RAS and CAS, asynchronous clock) with multiplexed row and column addresses on address bus 202. It can work as The control bus 204 carries conventional DRAM control signals (such as RAS and CAS), output enable, and read / write signals of the multiplexed address structure. As will be described further below, each bank 201 is associated with a separate set, and bank selection is made as a function of the address represented on the address bus 202.

In the application of memory 105 in which the system and frame buffer are associated, one bank 201 may be used as frame buffer block A, the second bank 201 may be used as frame buffer block B, and the other The bank 201 may be used as the system memory 109. For purposes of discussion, it is assumed that federated memory 105 is 8 MB (64 Mb) memory suitable to support the latest OS, such as Microsoft Windows 95. In this example, each bank 201 is a 1 MB DRAM device. In order to perform the selection of 1 bit of 64 Mb (ie, one "bit by one" ("by 1") device is used), 26 address bits are required in the non-multiplexed structure. If each bank is constituted by devices of 4, 8, 16, 32, or 64 bits, the number of address bits is appropriately reduced. For one bit device, three bits (eg, three least significant bits) of each address word are used for bank selection. To address frame buffer block A, frame buffer block B or system memory, CPU 101 simply changes these three address bits.

3 is a functional block diagram of another processing system 300. In the system 300, the display controller 104 and the DAC 106 are integrated onto a single integrated circuit 301 of a single chip, along with the system memory 105 and a number of frame buffer blocks. Display controller / DAC 104/106 accesses each frame buffer block through an internal address and data bus 306, which bus is also used to drive display device 107. As in system 100, CPU 101 writes directly to any frame buffer block for display update. As described below, one or more other frame buffer blocks may be used to refresh the display screen.

In particular, a pair of blocks 304A and 304B is provided as memory space for a corresponding pair of video frame buffers A and B. Also included on the integrated circuit 301 are a pair of blocks 305A and 305B that provide corresponding pairs of graphics frame buffers A and B. FIG. As in the case of the frame buffer blocks 110 and 111 described above, the video frame buffer blocks 304A and 304B are selectively used as the video update block (buffer) and the video refresh block (buffer). The same applies to the buffers 305A and 305B which selectively operate as update and refresh blocks (buffers) for graphic data only. Also provided on the integrated circuit 301 is a moving picture expert group (MPEG) frame buffer 307. Block 307 is dedicated to storing data in MPEG format and is also present in the address space within CPU 101.

While the invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (31)

In the processing system, Unified system memory including a system memory area and a plurality of frame buffer memory areas; As a central processing unit, the associated memory is located within an address space of the central processing unit, and the central processing unit is operable to update display data within a first selected area of the frame buffer area. While the display data from the second selected frame buffer of the frame buffers comprises a central processing unit for providing data for refreshing the display screen of the associated display device. The processing system of claim 1, wherein the CPU is further operable to retrieve the display data from the second frame buffer memory for refreshing the display screen. 2. The processing system of claim 1, further comprising a display controller for interfacing the associated system memory with the display device. The processing system of claim 1, wherein the display controller is further operable to retrieve the display data from the second frame buffer area for refreshing the display screen. 2. The processing system of claim 1, wherein the first and second frame buffer regions correspond to adjacent sets of addresses in an address space associated with the associated memory. The processing system of claim 1, wherein the system memory corresponds to an adjacent set of addresses in an address space associated with the associated memory. 2. The processing system of claim 1, wherein the system memory region corresponds to a plurality of sets of address spaces in an address space associated with the associated memory. 2. The processing system of claim 1, wherein each of the memory regions corresponds to a separate and contiguous physical memory region. 2. The processing system of claim 1, wherein said associative memory is comprised from a plurality of integrated circuit chips. 10. The processing system of claim 9, wherein each of said first and second frame buffer memory regions is allocated to at least one dedicated integrated circuit chip. In the processing system, An associated memory comprising at least one system memory region and first and second frame buffer regions; Circuitry for updating display data stored in the first frame buffer area; Circuitry for retrieving display data stored in the second frame buffer area to produce a display that substantially corresponds to updating the display data stored in the first frame buffer area; And circuitry for retrieving display data stored in said first frame buffer area to produce a corresponding update display. 12. The processing system according to claim 11, wherein said circuit for updating said display data stored in said first buffer area comprises a central processing unit. 12. The processing system of claim 11, wherein said circuit for retrieving data stored in said first frame buffer area comprises a central processing unit. 12. The processing system of claim 11, wherein said circuit for retrieving data stored in said second memory area comprises a central processing unit. 12. The processing system of claim 11, wherein said circuitry for retrieving data stored in said first memory space comprises a display controller. 12. The processing system of claim 11, wherein said circuitry for retrieving data stored in said second memory space comprises a display controller. 12. The processing system of claim 11, wherein the associated memory is configured on a single integrated circuit chip. In the processing system, A central processing unit (CPU), A bus connected to the central processing unit, A core logic circuit connected to the bus, And a associated memory system coupled to the core logic circuit, the associated memory system providing a system memory region and a plurality of frame buffer regions. 19. The system of claim 18, wherein the CPU is operable to write data to a first area of the frame buffer area via the system bus and the core logic circuit for display update, the frame buffer for display refresh. And be operable to read data from a second frame buffer in the region. 19. The system of claim 18, wherein the CPU is operable to write data to a first area of the frame buffer area via the system bus and the core logic circuit for display update, wherein the display controller is further configured to refresh the display. And read data from a second one of the frame buffer areas for the purpose of reading. 19. The processing system of claim 18, wherein the associative frame buffer is constructed from a plurality of memory devices. 22. The processing system of claim 21, wherein a selected one of the plurality of memory devices is provided for a corresponding area of the memory area. 19. The processing system of claim 18, wherein the selected area of the frame buffer area comprises a video frame buffer. 19. The processing system of claim 18, wherein one of the frame buffer areas comprises a graphics frame buffer. 19. The processing system of claim 18, wherein said area of said frame buffer area comprises an MPEG frame buffer. In the memory management method, Dividing the associated memory into system memory and first and second frame buffer regions; Updating display data stored in the first frame buffer; During the updating step, retrieving display data stored in the second frame buffer to produce a corresponding display; At the end of the updating step, retrieving display data stored in the first frame buffer to produce a corresponding update display. 27. The method of claim 26, wherein said updating comprises writing to at least one location in said first frame buffer directly from a CPU. 27. The method of claim 26, wherein the retrieving comprises retrieving display data in accordance with an address provided by an associated display controller. 27. The method of claim 26, wherein the retrieving comprises retrieving display data in accordance with an address provided from a CPU. 27. The method of claim 26, wherein the display data includes graphic data. 27. The method of claim 26, wherein the display data includes video data.