KR19990023837A - General Purpose Grid Array Board - Google Patents

Abstract

The present invention provides a general-purpose grid array substrate that can be used as semiconductor dies of various shapes, sizes, and pitches. In one embodiment of the present invention, the general-purpose grid array substrate includes an upper side and a lower side. The array of substrate pads is disposed on the upper side, which is substantially completely on the upper side of the substrate. The array of contacts is disposed opposite on the lower side of the substrate. The array of substrate pads is arranged such that a plurality of dies of various shapes, sizes, and pitches can be suitably attached to a general-purpose grid array. In a variant of the invention, the pitch of the substrate pad array and the contacts may be within 10 mils to 50 mils, but is not limited to this range. Methods of general purpose grid array substrates are also described herein.

Yet another embodiment of the present invention is a method of fabricating a plurality of semiconductor devices from a single universal grid array substrate. A general-purpose grid array substrate is provided that includes an array of substrate pads, a contact array, and a plurality of vias connecting the array. The plurality of semiconductor dies are disposed on a substrate. Each die is connected to a subset of substrate pad arrays corresponding to the substrate pads closest to the die. The plurality of dies are encapsulated and cured. The plurality of dies on the general-purpose grid array are unified to form a plurality of semiconductor devices. Each semiconductor device includes a die, a subset of substrate pad arrays, and a corresponding subset of contact arrays and vias.

Description

General Purpose Grid Array Board

Background of the Invention

The present invention relates generally to semiconductor substrates. More specifically, the present invention relates to a grid array type substrate and a method of manufacturing the same.

Ball grid arrays (BGAs) and fine pitch BGA substrates are commonly used in semiconductor packages. For the first time in FIGS. 1 and 2, a semiconductor package using a BGA substrate typically includes a semiconductor die 10 attached to the substrate 20. In general, die 10 includes a plurality of die bond pads 50. The substrate 20 typically includes many substrate pads 38 on the top surface of the substrate and a plurality of contacts 42 on the bottom surface of the substrate. Each substrate pad is typically electrically connected to an associated contact 42 through traces 39 on the upper and lower surfaces of the substrate and associated vias 45 that electrically connect the upper and lower traces. The vias 45 typically have associated upper and lower via pads 40, 41 to facilitate connecting the vias to the associated traces 39. Typically the substrate pad 38, trace 39 and via pads 40, 41 are plated as a single layer on either surface of the substrate. Typically the substrate pad is positioned as close to die 10 as practically possible to minimize the length of bonding wire 30 necessary to connect die bond pad 50 to substrate pad 38. Thus, the pitch of the substrate pads (eg, the spacing between the centers of adjacent substrate pads) tends to be quite sophisticated to accommodate relatively many I / O terminals (bond pads) 50 on the die. In contrast, vias 45 and via pads 40 and 41 are typically disposed toward the periphery of substrate 20 because processing techniques require that they be further spaced than substrate pads.

After the die 10 is properly attached and electrically connected to the substrate 20, the top surface of the BGA substrate 20 is often encapsulated with an encapsulant material 55. The completed semiconductor package 58 is conventionally hardened to cure the capsule encapsulation material 55. The contacts 42 typically take the form of solder balls, but sometimes other types of contacts are used. When the semiconductor package 58 is attached to the printed circuit board 70, the solder balls 60 are reflowed to electrically and physically connect the semiconductor package 58 to the printed circuit board 70.

One problem with the standard method is that the substrate 20 is typically custom made to meet the specific requirements of a particular die. As will be appreciated by those skilled in the art, bond pad pitches, as well as die size, die shape, and the number of I / O terminals (bond pads) per die, are often quite different for different devices, which requires custom board designs. . A serious problem with custom BGA substrates is the time it takes to manufacture them. Although the cycle time for the die has been dramatically reduced so that the die can be manufactured in a few days, the cycle time for manufacturing the BGA substrate is relatively long. Typically, production of custom BGA substrates requires more than six weeks. In general, most of the delay in the production of custom BGA substrates is due to the complex placement and path selection of the substrate input / output pads 38, via pads 40, 41 and contacts 42.

Another problem with custom BGA substrates is the need for custom tool test equipment to handle each of the new BGA substrates. Because custom BGA substrates usually have different footprints and differ in size and pitch, there is a need for a versatile general-purpose grid array substrate in the drawbacks of this custom BGA substrate design.

1 is a schematic perspective view mounted on a prior art ball grid array substrate, with the cut portion of the substrate exposing a typical via;

2 is a schematic cross-sectional view of the die of FIG. 1 in a completed semiconductor package mounted on a printed circuit board.

3A is a schematic plan view of a universal grid array substrate attached with different types of dies in accordance with one embodiment of the present invention.

3B and 3C are schematic cross-sectional views of the general-purpose grid array substrate of FIG. 3A shown as different types of vias.

4 is a schematic cross-sectional view of a semiconductor package using a general-purpose grid array substrate, in accordance with the present invention.

The present invention provides a general-purpose grid array substrate that can be used in semiconductor dies of various shapes, sizes, and pitches. In one embodiment of the present invention, a general-purpose grid array substrate includes an upper side and a lower side. The array of substrate pads is disposed on the upper side, which is substantially completely disposed on the upper side of the substrate. The array of contacts is disposed opposite on the lower side of the substrate. The plurality of vias electrically connect the array of substrate pads to the contact array. Arrays on the substrate pads are arranged such that a plurality of dies of various shapes, sizes, and pitches can be properly attached to the general-purpose grid array. In a variant of the invention, the pitch of the array of substrate pads may be 10 mils to 50 mils, but is not limited to this range. Also disclosed herein is a method of making a universal grid array substrate.

In another invention, the via has a substantially smaller cross-sectional area than the area of the substrate pad and the contacts. The via is disposed directly between the substrate pad and the contact and allows the substrate pad and the contact to be electrically connected externally.

In another embodiment, a general-purpose grid array substrate is used in semiconductor devices. The die is mounted on the upper side of the general-purpose grid array. The die is connected to an array of substrate pads on the upper side of the universal grid array substrate having a plurality of conductors. The array of substrate pads is electrically connected to the array of contacts on the lower side of the general-purpose grid array substrate by a plurality of vias. The top side of the die and universal grid array is then encapsulated.

Yet another embodiment of the present invention is a method of fabricating a plurality of semiconductor devices from a single universal grid array substrate. A general-purpose grid array substrate is provided that includes an array of substrate pads, a contact array, and a plurality of vias connecting the array. The plurality of semiconductor dies are disposed on a substrate. Each die is connected to an array of subsets of substrate pads corresponding to the substrate pads closest to each die. The plurality of dies are encapsulated and cured. The plurality of dies on the general-purpose grid array are monolayered to form a plurality of semiconductor devices. Each semiconductor device includes a die, a subset of substrate pad arrays, and a subset of contact arrays and vias.

These and other advantages of the present invention will become apparent to those skilled in the art with reference to the following description of the invention and several figures.

Detailed description of the preferred embodiment

Described herein are general-purpose grid array substrates and methods of making the same that can be used using semiconductor dies of different shapes, sizes, and pitches. The present invention can be used in place of conventional grid arrayed substrates that are custom-made without the long procurement time associated with custom-made substrates. The present invention further reduces the time and cost of reconfiguration and refurbishment testers due to similar footprints. Thus, several different types of semiconductor dies can be packaged and tested without the cost and complexity associated with design order substrates.

3A-C, one embodiment of the present invention will be described in more detail. 3A illustrates one embodiment of the present invention. In the illustrated embodiment, the substrate pads 140 are arranged in a uniform two dimensional array across the universal grid array substrate 120. General purpose grid array substrates may take any shape or size. However, the illustrated embodiment takes the form of a strip suitable for use in a typical semiconductor packaging facility.

Substrate pad 140 is used to electrically connect universal grid array substrate 12 to a plurality of die bond pads 50 on attached die 110. By way of example, this illustrated embodiment illustrates the use of a bonding wire 30 to electrically connect the substrate pad 140 to the die bond pad 50. However, other suitable methods such as flexible tapes, ceramics and PCB substrates may be used to electrically connect the universal grid array substrate 120 to the die 10. Bonding wire 30 may be composed of any suitable material. By way of example, aluminum, gold, and other malleable metals and alloys can be used to form bonding wires. Bonding wire 30 may also have an insulating coating.

Due to the variable design of the universal grid array substrate, it can be used to mount dies of any size or shape. As can be seen in FIG. 3A, not only a smaller die 110 ′ with fewer bond pads 50 but also a larger die 110 ″ with a larger number of bond pads 50 can be suitably accommodated. Can be. As can be appreciated, much larger and smaller dies than illustrated can be accommodated on a general-purpose grid array substrate. In the manner illustrated, many die 1010 may be packaged on a general-purpose grid array substrate.

Several dies may be disposed on a single universal grid array substrate 120. Depending on the number of substrate pads 140 and the size of die 110 required to properly connect die 110 to substrate 120, substrate 120 may be cut to an appropriate size. Before and after encapsulation, the appropriate portions of die 110 and universal grid array substrate 120 may be unified at the appropriate cut lines 106. Of course, the application of multiple dies is typically more efficient by bonding and packaging dies of the same type on a universal grid array substrate 120.

General purpose grid array 120 may also be used alone on a single die. Primarily for prototype purposes, a single die needs to be packaged. General purpose grid array substrate 120 may be used to mount a single die and may be suitably packaged.

In Figures 3b and 3c, a cross section of a variant embodiment of the invention is shown. Each of the substrate pads 140 on the side of the general-purpose grid array substrate illustrated in FIG. 3A is part of a substrate pad pair 150. The substrate pad pair 150 includes a substrate pad 140, a contact 142, and a connection via 145. The substrate pad 140 is disposed on the upper side of the universal grid array substrate 120. Contacts 142 are disposed on the other side of general purpose grid array substrate 120, typically opposite the substrate pad 140.

Substrate pad 140 and contact 142 generally define the cross-sectional volume of the substrate therebetween. According to one embodiment of the present invention, the via 145 is typically disposed within or substantially close to the cross-sectional volume of the substrate 120 defined by the substrate pad 140 and the contact 142. The routing of vias 145 is also usually uniform for all substrate pad pairs 150.

As can be appreciated, the complexity of routing between the substrate pad 140 and the contact 150 is considerably less in a custom-made BGA substrate due to the uniform routing of the vias 145. Moreover, in one embodiment of the present invention, there is no difference between the substrate pad and the via pad. Typically, all substrate pads 140 are connected to opposingly disposed contacts 150 by vias 145. Thus, lack of uniform pathing and traces of substrate pad pair 150 reduces the complexity and time required to produce a universal grid array substrate.

In one embodiment shown in FIG. 3B, the via is connected to the substrate pad 140 and the contact 142 such that the substrate pad 140 and the contact 142 are electrically connected during the cutting or singulation process as described in detail herein. As long as it is disposed in the vicinity, the general-purpose grid array substrate 120 can be made of conventional vias formed from conventional paths 145 '. In addition, since wire bonding may be difficult on irregular surfaces directly above the vias, the substrate pad 140 and the contacts 142 should be larger than the area required by the vias 145 'to allow for external connection of the surface area.

In another embodiment of the present invention, the vias 145 ″ of the substrate pad pair 150 are disposed directly between the bond pads 140 and the contacts 142 as shown in FIG. 3C. Via 145 ″ has a smaller cross-sectional area than bond pad 140 and contact 142. Thus, the via 145 ″ may be disposed toward the periphery of the cross-sectional area of the bond pad 140 and the contact 142. However, the vias 145 ″ may be placed anywhere within the cross-sectional area of the bond pads 140, 142 as long as there is sufficient area of the bond pads 140 and contacts 142 for wire bonding and / or solder ball bonding. .

As described, the universal grid array substrate 120 may be cut to accommodate dies 110 of different sizes. General purpose grid array substrate 120 may be cut or unified anywhere along substrate 120. In a preferred embodiment, a cut 106 is made between adjacent substrate pads 150 to minimize separation of any substrate pad pair 150. However, the cutting 106 can be made anywhere on the substrate 120 as long as the substrate pad pair 150 used to connect the die 10 is not disturbed.

In addition, although the substrate pad 140 and the contacts 142 are shown in an embodiment where the size and shape are substantially similar, the present invention is not limited thereto. The substrate pads 140 and contacts 142 can take any size and shape independently of one another as long as they can be disposed opposite one another on the side of the substrate 120.

In another embodiment of the present invention, the universal grid array substrate 120 may be used in a semiconductor device of a multi-chip module. Again in FIG. 3A, dies 110 ″ and 110 ′ may be more easily disposed on the universal grid array substrate 120. As a result, the dies 110 ″ and 110 ′ may be electrically coupled together directly or through the substrate pad 140 of the general-purpose grid array substrate 120. That is, in another embodiment, the wire bond may electrically couple the continuous substrate pads 140 to couple the die 110 ″ to the die 110 ′. As will be clear, more and more individual dies can be placed on a single general-purpose grid array substrate.

In FIG. 4, after die 110 is attached and bonded to universal grid array substrate 120, die 110 is typically encapsulated with encapsulant 55. Encapsulation may be implemented before or after unification of the appropriate portions of die 110 and substrate 120. The completed semiconductor device 158 according to another embodiment of the present invention is a die 110, a subset of substrate pad pair 150 and associated wires corresponding to the substrate pad 140 located closest to the die 110. It is typical to include the bond 30.

In one embodiment of the present invention, the contact 142 may be a landing used to place solder balls 60 that are later bonded to the printed circuit board 70. Solder balls 60 are typically reflowed onto contacts 142. The semiconductor device 158 is then disposed on the printed circuit board 70 including the plurality of traces 75. Trace 75 is configured to align with contact 142. The solder balls 60 are then reflowed to electrically and physically connect the semiconductor device 158 to the printed circuit board 70.

In a variant of the invention, the contact 142 may be another type of semiconductor package interface. By way of example, the contacts 142 may be pins as used in a pin grid array, reinforced contacts or other suitable semiconductor package interface.

An additional advantage of the present invention is the improved heat transfer properties of general purpose grid array substrate 120. The illustrated embodiment in FIG. 4 shows a die 110 attached to a universal grid array substrate 120. Die 110 is in physical contact with several substrate pads 140. When the semiconductor device 158 is properly attached to the printed circuit board 70, the substrate pad pair 150 provides increased heat flow from the die 110 to the printed circuit board 70.

The use of a versatile general-purpose grid array substrate that can be selectively cut to suit several different semiconductor devices is one of the clear features of the present invention. In addition, in one embodiment of the present invention, the substrate pad pitch, ie, the spacing between individual substrate pad pairs 150, is such that the universal grid array substrate 120 may be used with various die pitch sizes. By way of example, general-purpose grid array substrate 120 may have a pitch of approximately 20-30 mils, which is intermediate in the spectrum of die pitch size. Thus, general purpose grid array substrate 120 can be used with various semiconductor dies independently of shape, size or pitch.

Another advantage of the present invention is the general footprint. Most custom BGA substrates differ in shape, size and pitch size, requiring extensive refurbishment before different semiconductor devices can be tested. Semiconductor devices using general-purpose grid array substrates have a general pitch. An automated semiconductor device tester may be allowed to test several different semiconductor devices using a universal grid array substrate with minimal reconfiguration. In addition, semiconductor devices disposed on a single strip or panel of a general-purpose grid array substrate can be continuously tested simultaneously or at a faster rate because they are all the same substrate.

As described, general-purpose grid array substrates may be used for dies of different sizes, as well as for dies of different sizes. However, in another embodiment of the present invention, it may be more efficient to use a group of general-purpose grid array substrates having various pitch sizes. For example, a general-purpose grid array substrate with 20-50 mils can adequately handle dies with 4-10 mils, but may extend current bonding capabilities. To address this possibility limitation, a group of general-purpose grid array substrates can be used to apply the most widely used die pitch. By way of example, general-purpose grid array substrates 120 with pitch sizes in the 20, 32, and 50 mil ranges effectively apply most of the die pitch used by the semiconductor industry. However, the present invention is not limited to the pitch size of one range or value.

One of the many advantages of a single general-purpose grid array substrate is the ability to use common testers for different semiconductor devices made of general-purpose grid array substrates, but fabrication of a group of general-purpose grid array substrates with different pitch sizes. This dramatically reduces the rearrangement required for the tester's contacts from the current number of substrate pitches used today.

The general-purpose grid array substrate is also not limited to the particular size and shape shown by way of example. For example, a general-purpose grid array substrate may be formed into an elongated tape structure to suit semiconductor assembly equipment, large two-dimensional grids, or any other suitable form.

In addition, in a variant embodiment of the present invention, any suitable material may be used in the composition of the universal grid array substrate 120. For example, bismalimide triagine (BT), high temperature epoxy, FR4, PCB and polyimide are types of materials that can be used in the composition of general-purpose grid array substrate 120.

The placement of the substrate pad pair 150 may also vary. For example, in another embodiment, the substrate pad pair 150 may be packed at intervals rather than in a row-column format. Moreover, the cutting of the universal grid array substrate 120 does not have to be located along the portion of the substrate 120 without the vias 145, but the substrate pad pair 150 has most of the bond pads 140 and contacts 142. Can be arranged in any format as long as unification can occur without disturbing the electrical contacts.

While the present invention has been described with respect to some preferred embodiments, alternatives, improvements, modifications, and equivalents thereof will be apparent to those skilled in the art upon reference to the specification and drawings. Accordingly, the following appended claims are intended to cover such alternatives, modifications, improvements and equivalents as fall within the true spirit and scope of the present invention.

The present invention provides a general-purpose grid array substrate that can be used using semiconductor dies of different shapes, sizes, and pitches, and a method of manufacturing the same, wherein the present invention provides a custom-made process without the long procurement time associated with custom-made substrates. It can be used in place of the conventional grid array substrate. The present invention further reduces the time and cost of reconfiguration and refurbishment testers due to similar footprints. Thus, several different types of semiconductor dies can be packaged and tested without the cost and complexity associated with design order substrates.

Claims (5)

A general-purpose grid array substrate comprising an upper side and a lower side, A two-dimensional array of substrate pads disposed on top of the general-purpose grid array such that the array of substrate pads lies substantially completely on the top side of the general-purpose grid array substrate; A contact array disposed on the bottom side of the general-purpose grid array substrate, disposed opposite the array of substrate pads; And A plurality of vias that electrically connect each of the substrate pads to their associated oppositely disposed contacts General-purpose grid array substrate comprising a. In the panel used for manufacturing a semiconductor device, A general-purpose grid array substrate according to claim 1; And Multiple dies mounted on the substrate Panel comprising. In a multi-chip semiconductor device, A two-dimensional array of substrate pads disposed on top of the universal grid array such that the array of substrate pads lies substantially completely on the top side of the universal grid array substrate, A contact array disposed on the bottom side of the general-purpose grid array substrate, disposed opposite the array of substrate pads, and A plurality of vias that electrically connect each of the substrate pads to their associated oppositely disposed contacts A general-purpose grid array substrate comprising a; A plurality of die mounted on the upper side of the general purpose ball grid array; A plurality of bonding wires electrically connecting the plurality of dies to the general-purpose grid array substrate; And Encapsulation that encapsulates substantially all upper sides of a plurality of dies and universal ball grid arrays Multi-chip semiconductor device comprising a. In the process of manufacturing a general-purpose grid array substrate, Forming an array of substrate pads on the upper side of the substrate, the array of substrate pads substantially completely lying on the upper side of the substrate; Forming an array of contacts disposed opposite the array of substrate pads on the lower side of the substrate; And Forming a plurality of vias that electrically connect the array of substrate pads to each of the associated arrays of opposing contacts. Process comprising a. In the process of manufacturing a semiconductor device, Providing a general-purpose grid array substrate, the general-purpose grid array comprising a substrate pad array on an upper side of the substrate, a contact array on a lower side of the substrate disposed opposite the substrate pad array, and a plurality of vias, the plurality of vias Electrically connecting each of the substrate pad arrays to each of the oppositely disposed associated contact arrays; Disposing a plurality of die each comprising a plurality of die bond pads on an upper side of the universal grid array substrate; Wire bonding a plurality of die bond pads of each die to a subset of substrate pad arrays having a plurality of conductors, wherein the subset of substrate pad arrays includes bond pads of the bond pad array closest to each die Process comprising a.