KR19990021982A - Contact carriers (tiles) for anchoring large substrates with spring contacts - Google Patents

Abstract

According to the invention a number of connection elements, such as contact bumps or free upright spring contacts comprising single and complex interconnect elements, are mounted on a relatively small tile substrate which is in turn mounted and connected to a relatively large electronic component substrate, thereby providing contact elements. A plurality of contact elements are settled in the electronic component while eliminating the need to manufacture directly on the electronic component. The relatively large electronic component is suitably the space transducer component of the probe card assembly. In this way, a pressurized connection can be made instantly to the entire semiconductor wafer such that wafer-level burn-in or the like is provided. Solder balls, z-axis conductive adhesives or compliant connections are suitably used to make an electrical connection between the tile substrate and the electronic component. Multiple die sites on a semiconductor wafer are easily probed using the disclosed techniques, and tiles can be arranged to optimize the probing of the entire wafer. Composite interconnect elements having a relatively soft core overcoated with a relatively hard shell, such as an elastic contact structure, are disclosed. Techniques for maintaining the x-y and z-axis alignment of tiles to a substrate are disclosed.

Description

Contact carriers (tiles) for anchoring large substrates with spring contacts

Background of the Invention

Techniques for making pressurized connections with composite interconnect elements are disclosed in US patent application Ser. No. 08 / 450,255 (parent case), filed May 26, 1995, jointly owned.

As described in US patent application Ser. No. 08 / 554,902, filed November 9, 1995, which is still owned jointly, individual semiconductor (integrated circuit) devices (dies) are known techniques such as photolithography, precipitation, and the like. It is typically manufactured by making several identification devices on a semiconductor wafer. In general, these processes seek to create a number of fully functional integrated circuit devices prior to unifying (cutting) individual die from a semiconductor wafer. However, substantially any physical defects in the wafer itself and some defects in the process of the wafer will inevitably cause some dies to be in a good (fully functional) state, while others may be bad (non-functional). Functional).

It is generally desirable to be able to verify that a number of dies on a wafer are good dies before their packaging, preferably before being unified from the wafer. For this purpose, a wafer tester or prober may be usefully used to make multiple discrete pressurized connections on a die against similar multiple discrete contact pads (bond pads). In this way, the semiconductor die can be tested and operated before unifying the die from the wafer.

A conventional component of a wafer tester is a probe card to which a plurality of probe elements are connected, with the tips of the probe elements making a pressure connection to each bond pad of the semiconductor dies.

Some disadvantages are inherent in the technique of probing a semiconductor die. For example, modern integrated circuits include thousands of resistive elements that require hundreds of bond pads that are placed in close proximity to one another (eg, 5 mils center to center). Moreover, the arrangement of bond pads need not be limited to a single row of bond pads disposed closely on the periphery of the die (see, eg, US Pat. No. 5,453,583).

In order to achieve a reliable pressurized connection between the probe element and the semiconductor die, several parameters should be taken into account, but not limited to such parameters: alignment, probe force, overdrive, contact force, balanced contact force, screed Scrub, contact resistance and planarity. A discussion of these parameters can be found in US Pat. No. 4,837,622, entitled HIGH DENSITY PROBE CARD, which is incorporated herein by reference and is described as a high density probe card. Disclosed is a high density epoxy ring probe card comprising a single printed circuit board having a central opening made to receive a ring arrangement.

Generally, prior art probe card assemblies include a plurality of tungsten needles (probe elements) extending in the form of cantilevers from the surface of the probe card. The tungsten needle may be mounted to the probe card in a suitable manner as described above, for example by the middle of the epoxy ring. In general, in some cases, the needle is connected to the terminal of the probe card through the middle of a separate and separate wire connecting the needle to the terminal of the probe card.

The probe card is typically formed of a circular ring and hundreds of probe elements (needles) extend from the inner circumference of the ring (and are connected to the terminals of the probe card). Circuit modules and preferably equal length conductive traces (lines) are associated with each of the probe elements. This ring arrangement is particularly suited to probe multiple non-unified semiconductor dies (multiple regions) on a wafer when the bond pads of each semiconductor die are arranged outside two linear arrays along two opposite edges of the semiconductor die. It makes it difficult, and in some cases impossible.

In US Patent Application No. 5,422,574, which is specifically described by reference in the text and whose name is LARGE SCALE PROTRUSION MEMBRANE FOR SEMICONDUCTOR DEVICES UNDER TEST WITH VERY HIGH PIN COUNTS As disclosed, wafer testers may alternatively use a probe membrane having a central contact bump (probe element) region. As noted in the patent, the test system typically includes a test controller that executes and controls a series of test programs, a wafer distribution system that mechanically processes and positions the wafer during test preparation, and an apparatus-under-test ( device-under-test (DUT) and a probe card to maintain accurate mechanical contact (columns 1, lines 41-46).

Additional references include the following patents, which are incorporated herein by reference and represent the technical field of testing semiconductor devices: US Pat. No. 5,442,282 (testing and implementing individual non-unified dies on wafers); 5,382,898 (high density probe card for electrical circuit testing); 5,378,982 (test probes for panels with overlapping protective members adjacent to the panel contacts); 5,339,027 (Stiffness-Flexible Circuits with Elevated Features as IC Test Probes); 5,180,977 (membrane probe contact bump compliance system); 5,066,907 (probe systems for device and circuit testing); 4,757,256 (High Density Probe Card); Probe devices for integrated circuit wafers); And 3,990,689 (adjustable holder assemblies for positioning vacuum chucks).

In general, interconnections between electronic components can be classified into two types: relatively permanent and easily removable.

One example of a relatively permanent one is a solder joint. Once the two parts are soldered, the process of removing the solder must be used to separate these parts. Wire bonding is also an example of a relatively permanent connection.

One example of the easily detachable one is the rigid pin of another electronic component received by the elastic socket element of one electronic component. The socket element exerts a contact force (pressure) on the pins of sufficient magnitude to ensure a reliable electrical connection between the electronic components.

An interconnect element for making a pressure connection with the terminals of the electronic component is called a spring or spring element. In general, a constant minimum contact force is required to make a reliable press connection to an electronic component (eg, a terminal on the electronic components). For example, a contact force (load) of about 15 grams (less than 2 grams per contact and up to 150 grams or more) can be reliably applied to terminals of electronic components that are contaminated with the film on the surface or have corrosion or oxide on the surface. It is necessary to ensure that the connection is made. The minimum contact force required for each spring requires an increase in the yield strength of the spring material or the size of the spring element. In general, the higher the yield strength of a material, the more difficult its work (perforation and bending, etc.) is. As an alternative, in order to manufacture the spring compactly, it is disadvantageous to increase the cross-sectional area of the springs.

Probe elements (other than the contact bumps of the membrane probes) are a type of spring element in particular associated with the present invention. Conventional probe elements are typically made of tungsten, a relatively rigid (high tensile strength) material. When attempting to mount such a relatively rigid material to the terminals of an electronic component, a relatively hostile (eg, high temperature) process such as soldering is required. Such opposing processes are generally undesirable within the limits of certain relatively fragile electronic components such as semiconductor devices. In contrast, wire bonding is an example of a relatively friendly process, with much less chance of damaging vulnerable electronic components than soldering. Soldering is another example of a relatively affinity process. However, solder and gold are relatively soft (low yield strength) materials and will not function better than spring elements.

A difficult problem associated with interconnecting elements comprising spring contacts is that the terminals of the electronic component are often not completely coplanar. Interconnect elements lacking some mechanisms incorporated to accommodate these tolerances (large non-planarity) will be strongly pressurized to create a constant contact pressure in contact with the terminals of the electronic component.

The following U.S. patents incorporated herein by reference are cited as being of general interest for connecting to electronic devices, in particular for pressurized connections. U.S. Patent 5,386,344 (Flex Circuit Card Elastomer Cable Connector Assemblies), 5,336,380 (Spring-Flat Tapered Contact Elements for Electrical Connectors and Integrated Circuit Packages), 5,317,479 (Plated Flexible Leads), 5,086,337 (connection structures of electronic components and electronic devices using the structures), 5,067,007 (semiconductor devices having leads for mounting on the surface of printed circuit boards), 4,989,069 (with conductors deviating from the support) Semiconductor packages), 4,893,172 (connection structures for electronic components and methods of manufacturing the same), 4,793,814 (electric circuit board interconnections), 4,777,564 (leadforms used with surface-mounted elements), 4,764,848 (Surface Mount Array Strain Relief), 4,667,219 (Semiconductor Chip Interface), 4,642,889 (Flexible Interconnect and Manufacturing Method), 4,330,165 (Pressure Contact Interconnect) Connectors), 4,295,700 (interconnect connectors), 4,067,104 (methods for manufacturing flexible metal interconnect arrays for joining microelectronic elements), 3,795,037 (electrical connector devices), 3,616,532 (multilayer printed circuits) Electrical interconnectors) and 3,509,270 (interconnects for printed circuits and methods of manufacturing the same).

In the aforementioned application, a technique for manufacturing composite interconnect elements (elastic contact component, spring element) on an electronic component is disclosed. In cases where multiple such spring elements are required, failure to yield (successfully manufactured), except for one of the majority of spring elements, is not available or best requires extensive rework on the entire part. It may also cause defects.

Moreover, in the case where it is required to manufacture a large number of spring contacts on a large substrate area, for example to provide a test for the entire semiconductor wafer in a single pass, a significant number of spring contacts are successful. It is not easy to find a suitable substrate (e.g., conforming to the coefficient of thermal expansion) that can be mounted on the substrate.

FIELD OF THE INVENTION The present invention relates to the fabrication of temporary pressurized connections between electronic components, in particular testing and burn-in of semiconductor devices prior to packaging, preferably before individual semiconductor devices are singulated from the semiconductor wafer. -in) relates to a technique for performing the process.

Cross Reference to Related Application

This patent application is part of a pending US patent application Ser. No. 08 / 452,255 filed on May 26, 1995, filed under US Patent Application No. 08 / 452,255, filed hereafter. Is a co-owned, pending US Patent Application No. 08 / 340,144 filed November 15, 1994 (state: pending application) and its PCT Patent Application No. PCT / US94 /, filed November 16, 1994 Part of a continuing application of 13373 (published May 26, 1995 as WO 95/14314), both of which are jointly owned US patent application Ser. No. 08 / 152,812, filed November 16, 1993 (1995). US Patent No. 5,476,211, filed Dec. 19, filed on December 19, 2008.

In addition, this patent application is part of a continuing, pending US patent application of a common ownership.

08 / 526,246 filed September 21, 1995 (PCT / US95 / 14843, November 13, 1995);

08 / 533,584, filed Oct. 18, 1995 (PCT / US95 / 14842, Nov. 13, 1995);

08 / 554,902, filed November 9, 1995 (PCT / US95 / 14844, November 13, 1995);

08 / 558,332, filed November 15, 1995 (PCT / US95 / 14885, November 15, 1995);

08 / 573,945, filed December 18, 1995;

08 / 584,981, filed January 11, 1996;

08 / 602,179, filed February 15, 1996;

60 / 012,027, filed February 21, 1996;

60 / 012,040, filed February 22, 1996;

60 / 012,878, filed March 5, 1996;

60 / 013,247, filed March 11, 1996; And

60 / 005,189, filed May 17, 1996.

All patent applications are part of the above-described parent application, which is incorporated herein by reference.

Brief description of the drawings

Preferred embodiments of the present invention will be described with reference to the accompanying drawings. Although the present invention will be described in terms of preferred embodiments, the present invention is not limited to the above embodiments.

In the side view presented here the parts are often presented in cross-section for clarity of illustration. For example, in many figures the wire stem (core element) is shown completely in bold lines and the overcoat is shown in real section (often without hatching).

In the drawings presented here, the size of certain elements is often exaggerated (unscaled compared to other elements in the figure) for clarity of illustration.

1A is a cross-sectional view of a longitudinal portion including one end of an interconnection element in accordance with one embodiment of the present invention.

1B is a cross-sectional view of a longitudinal portion including one end of a composite interconnect device according to another embodiment of the present invention.

1C is a cross-sectional view of a longitudinal portion including one end of a composite interconnect device according to another embodiment of the present invention.

1D is a cross-sectional view of a longitudinal portion including one end of a composite interconnect device according to another embodiment of the present invention.

1E is a cross-sectional view of a longitudinal portion including one end of a composite interconnect device in accordance with another embodiment of the present invention.

2A is a cross-sectional view of a composite interconnect device mounted to the terminals of an electronic component and having a multilayer shell in accordance with the present invention.

Figure 2B is a cross-sectional view of a composite interconnect device having a multilayer shell in which the intermediate layer is of dielectric material in accordance with the present invention.

Figure 2C is a perspective view of a plurality of interconnect elements mounted in an electronic component (probe card insert) that may be a composite interconnect element in accordance with the present invention.

FIG. 2D is a cross-sectional view illustrating an exemplary first step of a technique for fabricating an interconnect device having curved tips in accordance with the present invention. FIG.

2E is a cross-sectional view illustrating exemplary additional steps of the technique of FIG. 2D to fabricate an interconnect device in accordance with the present invention.

2F is a cross-sectional view illustrating exemplary additional steps of the technique of FIG. 2E to fabricate an interconnect device in accordance with the present invention.

FIG. 2G is a cross-sectional view illustrating a number of exemplary individual interconnect devices fabricated in accordance with the techniques of FIGS. 2D-2F in accordance with the present invention. FIG.

FIG. 2H is a cross-sectional view of a number of exemplary interconnect elements fabricated in accordance with the techniques of FIGS. 2D-2F in accordance with the present invention and associated in a predetermined spatial relationship with one another.

2I is a cross-sectional view illustrating one alternative embodiment of interconnect device fabrication, showing one end of one device in accordance with the present invention.

3 is a cross-sectional view illustrating a schematic embodiment of an interposer component in accordance with the present invention.

4 is a cross-sectional view illustrating a schematic embodiment of a space converter component in accordance with the present invention.

5 is an exploded view partially showing a cross section of a probe card assembly in accordance with the present invention.

5A is a perspective view of a space transducer component suitable for use within the probe card assembly of FIG. 5 in accordance with the present invention.

5B is a perspective view of another spatial transducer component suitable for use within the probe card assembly of FIG. 5 in accordance with the present invention.

6 is a cross-sectional view of one embodiment of a tile component according to the present invention.

Fig. 6A is an exploded perspective view illustrating a technique for mounting a plurality of tile components to a space converter component (large substrate) in accordance with the present invention.

7 is a perspective view of one embodiment of applying one or more tile components to a substrate, such as an electronic component such as a semiconductor wafer, in accordance with the present invention.

8A is a cross-sectional view illustrating a technique of manufacturing a tile part according to the present invention.

8B is a cross-sectional view illustrating additional steps in the technique of FIG. 8A in accordance with the present invention.

8C and 8D are cross-sectional views showing a sacrificial substrate provided with a tip-component that is later mounted to the tips of an interconnect element in accordance with the present invention.

FIG. 8E is a side view partially showing part of an entirety of another technique for making tile sacrificial parts in accordance with the present invention. FIG.

FIG. 8F is a side view partially showing a portion of the entirety of the tile component of FIG. 8C incorporated with the prefabricated tip structure of FIGS. 8C-8D in accordance with the present invention. FIG.

FIG. 8G is a side view, in part, in part, in full, of an additional step of coupling the tip structure to the spring elements on the tile component of FIG. 8D in accordance with the present invention; FIG.

9A is a cross-sectional view illustrating a technique for maintaining a plurality of tile substrates properly aligned with a counter substrate in accordance with the present invention.

Figure 9B is a cross-sectional view showing another technique for holding a plurality of tile substrates properly aligned with a counter substrate in accordance with the present invention.

Figure 9C is a cross sectional view showing another technique for holding a plurality of tile substrates properly aligned with a counter substrate in accordance with the present invention.

Fig. 9D is a cross sectional view showing another technique for holding a plurality of tile substrates properly aligned with a base substrate in accordance with the present invention.

10A is a perspective view of one embodiment of a spring contact carrier (tile), in particular for a probe element, in accordance with the present invention.

10B is a cross-sectional view of the tile of FIG. 10A in accordance with the present invention.

10C is a cross-sectional view of another embodiment of a spring contact carrier (tile), in particular for a probe element, in accordance with the present invention.

10D is a cross-sectional view of another embodiment of a spring contact carrier (tile), in particular for a probe element according to the invention.

Fig. 10E is a cross sectional view of another embodiment of a spring contact carrier (tile), in particular for a probe element according to the invention.

11A is a cross-sectional view illustrating one embodiment of a technique for performing wafer level burn-in in accordance with the present invention.

Figure 11B is a cross-sectional view illustrating another embodiment of a technique for performing wafer level burn-in in accordance with the present invention.

Figure 11C is a cross-sectional view illustrating another embodiment of a technique for performing wafer level burn-in in accordance with the present invention.

12A is a cross-sectional view illustrating one technique for mounting multiple tiles to a large substrate (e.g., the spatial transducer of the probe card assembly of the present invention) in accordance with the present invention, (a) (e.g., with a semiconductor wafer Changing the overall coefficient of thermal expansion of such an assembly to conform to the same probed desired component, and (b) connecting to a substrate (such as the interposer of the probe card assembly of the present invention).

12B is a cross-sectional view illustrating another technique for mounting a plurality of tiles to a large substrate (e.g., a spatial transducer of the probe card assembly of the present invention) in accordance with the present invention, (a) (e.g., with a semiconductor wafer Changing the overall coefficient of thermal expansion of such an assembly to conform to the same probed desired component, and (b) connecting to a substrate (such as the interposer of the probe card assembly of the present invention).

Brief Description of the Invention (Summary)

It is an object of the present invention to cover a large area, such as a probe card, and to avoid the problems associated with the breakdown of (successfully manufactured) probe elements, a number of probe elements on the electronic component, in particular spring elements mounted directly on the electronic component. It is to provide an improved technique for mounting phosphor probe elements.

Another object of the present invention is to provide a technique for providing a spring contact portion to an electronic component such as a space converter and a semiconductor device while solving a problem (e.g. yielding) occurring in manufacturing the spring contact portion on the electronic component.

According to the present invention, probe elements such as spring contacts are prefabricated on individual spring contact carriers (tiles). Many such tiles are in a mutually confined relationship, preferably mounted to other components (such as a space converter substrate or a printed circuit board) such that the tips of the spring contacts are coplanar with each other. Tile substrates are relatively inexpensive and conductive to yield spring contacts. The terminals on the opposite side of the tile are joined to the terminals of an electronic component, such as a space transducer or one or more semiconductor devices (including devices in a unified peninsula) by soldering, z-axis conductive bonding or the like.

The spring contacts are preferably composite interconnect elements. However, any suitable spring contact can lead to the present invention's manner, such as monolithic spring contacts and membrane probe sections.

As used herein, the term probe element refers to terminals (eg, terminal pads) of an electronic component (eg, a semiconductor die including a non-unified semiconductor die located on a semiconductor wafer). And any arbitrary element such as a composite interconnect element, a spring contact, a spring element, a contact bump, etc. suitable for performing a pressurized connection.

As used herein, the term tile includes any component having probe elements on its surface, and a number of tiles (preferably the same) can be mounted on a substrate, so that it can be mounted directly on the substrate. To prevent the fabrication of the probe elements.

As used herein, the term tile substrate refers to not only frames (eg, 1002, 1002a, 1002b, 1002c) but also solid substrates (eg, 602, 902, 922, 942, 962) and the like. It includes.

As used herein, a larger substrate refers to a substrate on which multiple tiles can be mounted. In general, at least four tiles are mounted to the substrate and the surface area of the substrate has at least four times the area of the surface of the individual tiles. This includes in particular the space transformer of the probe card assembly.

As can be used in the text, spark refers to electrical discharge.

According to one embodiment of the present invention, such a plurality of tiles may be attached and connected to a single spatial transducer component of the probe card assembly to perform a wafer level (multi-region) test, wherein the entire semiconductor wafer is a semiconductor located on the semiconductor wafer. It can be burned-in and / or tested by making a simultaneous press connection between multiple bond pads (terminals) of the devices and multiple probe elements.

According to one feature of the invention, the tiles may be a single layer substrate or may be a multilayer substrate that performs significant spatial conversion.

According to another feature of the invention, multiple tiles with spring contact elements fabricated on the surface can be made of a single inexpensive substrate, such as a ceramic wafer, after which the surface of the spatial converter or semiconductor wafer or other electronic component It is preferably diced into the same plurality of separate tiles that can be individually mounted to the surface of the.

According to one aspect of the invention, the electronic component and the tile (s) are each provided with at least one solderable feature to enhance the automatic alignment of the one or more tiles on the corresponding surface of the mounted electronic component. The portions provide the electronic component with an elevated momentum during which solder is provided therebetween and performs automatic alignment of the tile substrate during countercurrent heating.

One advantage of the present invention is that the tiles can be mounted directly to a semiconductor device comprising a fully populated C4 die with the active device after or prior to singulation from the semiconductor wafer. In this way, the spring contact elements are easily mounted in the semiconductor device and solve the disadvantage of manufacturing the spring contact elements directly on the semiconductor device.

Another advantage of the present invention is that the tiles from which the spring elements are fabricated can be a real C4 package with solder bumps on opposite sides of the spring elements. In this way, the tiles can be mounted to the surface of the electronic component (eg, space converter, semiconductor wafer, etc.) by countercurrent heating.

An advantage of the technique of using tiles rather than directly fabricating a spring element on the surface of the electronic component is that the electronic component is easily reworked by simply replacing selected ones of one or more tiles attached / connected.

The present invention can be applied to using tiles to integrate large substrates, and the probe elements on the tiles may be of the contact bump type installed in the membrane probe.

According to one aspect of the invention, a semiconductor device having a spring contact element mounted in the manner described above has a printed circuit board (PCB) having terminals (pads) arranged to engage (by pressure contacts) with the tips of the spring contact elements. Easily tested and / or burned-in using simple test fixtures.

The tile-mounted space converter substrate comprises a probe card (electronic component) having a plurality of terminals on the top, bottom and top surfaces, and a first plurality of elastic contacts extending from the terminals on the top, bottom and bottom surfaces. It can suitably be used as a component of a probe card assembly comprising an interposer (electronic component) having a structure and a second plurality of contact structures extending from a terminal on the top surface. The interposer is located between the probe card and the space transducer, as disclosed in co-owned US patent application Ser. No. 08 // 554,902.

Throughout the description disclosed herein, the use of the term compound is equivalent to the generic meaning of the term (eg, consisting of two or more members), and any use of compound word in other fields, for example, glass It is not to be confused with being applied to a material such as other fibers supported on a matrix such as carbon or resin.

As used herein, the term spring shape means any shape of an elongated element in which the end (tip) of the elongate element exhibits elastic (restoration) movement with respect to the force acting on this tip. It also includes elongate elements of substantially straight shape and substantially straight elements with one or more bends.

As used herein, the terms contact area, terminal, pad, and the like refer to any conductive area on any electronic component to which the interconnect element is mounted or in contact with.

In addition, the core element is shaped before mounting on an electronic component.

In addition, the core element is mounted on or is part of a sacrificial substrate rather than an electronic component. The sacrificial base layer is removed after molding and before or after overcoating. According to a feature of the invention, the tips with various rough surface finishes can be arranged at the contact ends of the interconnection elements (see also FIGS. 11A-11F of the parent source).

In one embodiment of the present invention, the core is a soft material having a relatively low yield strength and is overcoated with a hard material having a relatively high yield strength. For example, a soft material such as gold wire is attached to the terminal of the electronic component (by wire bonding or the like) and overcoated with a hard material such as nickel and its alloy (by electrochemical plating or the like).

Core facing overcoating, single and multilayer overcoating, coarse overcoating with fine protrusions (see FIGS. 5C and 5D of the parent application) and overcoating over the entire length or only a portion of the core are described. In the case of overcoating the entire length or only part of the core, the tip of the core may be appropriately exposed to make a connection to the electronic component (see FIG. 5B of the application).

In general, plating herein is used as one of several methods for overcoating cores. Within the scope of the present invention, all known processes for precipitating materials and depositing materials from aqueous solutions, electrolytic plating, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), separation of liquids, solids or gases, The core may be overcoated by any suitable process, including the method.

Usually, in order to overcoat the core with a metal material such as nickel, an electrochemical process, in particular electrolytic plating, is preferred.

In another embodiment of the present invention, the core is an elongate element made of a hard material, essentially configured to function as a spring element, and is mounted at one end to the terminal of the electronic component. At least one adjacent area of the core and the terminal is overcoated with a material that will help secure the core to the terminal. In this manner, the core does not need to be well mounted to the terminal prior to overcoating, and a process that is substantially less damaging to the electronic components can be used to hold the core in place for subsequent overcoating. These affinity processes include soldering, adhesive bonding, and inserting one end of the hard core through the soft portion of the terminal.

Preferably, the core is in an anterior form. As an alternative, the core is a flat tab (conductive metal ribbon).

Representatives as core and overcoat materials are described.

Mainly, the following describes a method of performing with a relatively soft (low yield strength) core that is generally very small in dimension (eg, 0.0762 mm (3.0 mil) or less). Soft materials such as gold, which are easily attached to the semiconductor device, have sufficient elasticity to function as a spring. (These soft metal materials exhibit primarily plasticity rather than elastic deformation.) Other soft materials that are easily attached to semiconductor devices and have adequate resilience are electrically non-conductive as in the case of most elastomeric materials. In both cases, the required structural and electrical properties can be imposed on the composite interconnect device by overcoating applied over the core. Composite connection elements can be made very small while exhibiting adequate contact forces. In addition, the plurality of the composite connection elements have a length (eg, 2.54 mm (100 mil)) that is much larger than the distance to adjacent composite connection elements (the distance between adjacent connection elements is called pitch). Even finer pitch (eg, 0.254 mm (10 mil)).

Within the scope of the present invention, composite interconnect elements can be made microminiature, for example as miniature springs for connectors and sockets having a cross-sectional dimension of 25 μm or less. This makes it possible to fabricate reliable interconnect elements with dimensions measured in microns rather than mils, indicating the need for interconnect methods and even area array methods.

The composite interconnect device of the present invention exhibits excellent electrical properties including conductivity, solderability, and low resistance. In many cases, deformation of the interconnect elements in response to applied forces results in wiping contacts, which helps to make reliable connections.

Another advantage of the present invention is that the connection made with the interconnection element of the present invention can be easily separated. Soldering to make interconnects to the terminals of electronic components is optional and generally undesirable at the system level.

According to one aspect of the present invention, a method of manufacturing an interconnect device having a controlled impedance is described. These methods involve coating (eg, electrophoretic) the conductive core or the entire composite interconnect device with a dielectric material (insulating layer) and overcoating the dielectric material with an outer layer of conductive material. By grounding the outer conductive material layer, the interconnection element can be effectively shielded and its impedance can be easily controlled (see FIG. 10K of the model).

According to one aspect of the invention, the interconnect elements can be prefabricated as individual units for subsequent attachment to electronic components. Several methods have been described for achieving this purpose. Although not specifically described herein, it takes a relatively straightforward shape to manufacture machines that will be equipped to mount a plurality of individual interconnect elements on a substrate or to suspend a plurality of individual interconnect elements on an elastomer or support substrate. It is supposed to be.

It should be clearly understood that the composite interconnect elements of the present invention are very different from the interconnect elements of conventional methods that are coated to enhance the conductive properties and enhance the resistance to corrosion.

The overcoating of the present invention is particularly intended to enhance the fastening of the interconnect elements to the terminals of the electronic components and / or to impose the required elastic properties on the composite interconnect elements. The stress (contact force) is directed to the portions of the interconnect element that are adapted to absorb this stress.

It is also to be understood that the present invention provides a new method for manufacturing the spring structure. In general, the actuated structure of such springs is a product by plating rather than bending and shaping operations. This makes it possible to use different materials to form the spring shape and use an affinity process to attach the scaffold of the core to the electronic components. Overcoating functions as a superstructure on the scaffolding of the core, both of which are originally used in the field of civil engineering.

According to one aspect of the invention, the elastic contact structure may be formed of at least two composite interconnect elements.

A particularly useful application of the present invention is the provision of a method of probing (electrically contacting) a plurality of spring contact elements to a testable area of an electronic component, which in turn places a plurality of contact carriers (tile substrate) on a substrate to substrate. The spring contact elements extending from the surface of the tile substrate are made by contacting with corresponding terminals on the testable area of the electronic component (by mounting and connecting) and pressing the base substrate and the electronic component toward each other. The electronic component may be a semiconductor wafer, in which case the testable area is a plurality of die sites on the semiconductor wafer. The ability of all spring contacts to suddenly come into contact with multiple die sites can facilitate processes such as wafer-level burn-in. However, the entire electronic component does not need to be in immediate contact. An advantage arises when at least a substantial part of the electronic component is immediately contacted. The electronic component may also be a printed circuit board (PCB) or liquid crystal display (LCD) panel, for example.

Other objects, features and advantages of the invention are clearly described in the following description.

Detailed description of the invention

US patent application Ser. No. 08 / 554,902, co-owned on an ongoing basis, relates to probe card assemblies, parts thereof, and methods of using them. As will be apparent from the following description, it is essential to use an elastic contact structure that performs pressure contacts to the terminals of the electronic component. Elastic contact structures (spring elements, spring contacts, probe elements) are disclosed in US patent application Ser. No. 08 / 452,255, filed on May 26, 1995, which is incorporated herein by reference and is still co-owned. Similarly, there may be single spring elements (as opposed to composite), suitably used as composite interconnect elements, but consisting essentially of materials having a high yield strength (without the need for overcoating of high yield strength materials).

The following description summarizes a number of techniques disclosed in the parent application in the disclosure of FIGS. 1A-1E and 2A-2I.

An important aspect of the invention is that a composite interconnect element (as opposed to a single) starts with a core (mounted to a terminal of an electronic component) and then (1) achieves the mechanical properties of the composite interconnect element and / or ( 2) formed by overcoating the core with a suitable material to firmly secure the interconnect element to the terminal when the interconnect element is mounted to the terminal of the electronic component. In this way, elastic interconnect elements (springs) can be fabricated by starting with a core of soft material that is easily formed into a spring shape and easily attached to even the most vulnerable portions of electronic components. The fact that the soft material can form the base of the spring element is not easily found and intuitively known in the prior art method of forming the spring element from the hard material. Such a composite interconnect element is generally a preferred form of elastic contact structure used in embodiments of the present invention. However, as described above, the spring contact portion of the present invention may be a single type rather than a composite.

1A, 1B, 1C and 1D illustrate various shapes of a composite interconnect device according to the invention in a general manner.

Mainly, composite interconnect elements exhibiting elasticity will be mainly described hereinafter. However, it can be seen that the inelastic composite interconnect element also falls within the scope of the present invention.

Also described is a composite interconnect element having a soft core overcoated by a hard (spring) material (which can be easily shaped and attached to an electronic component by an affinity process). However, within the scope of the present invention, the core can be made of a hard material, where the overcoating mainly functions to securely fix the interconnect element to the terminal of the electronic component.

In FIG. 1A the electrical interconnect element 110 is 2812 kg / cm²Core 112 of soft material having a yield strength of less than 40,000 psi, and 5,624 kg / cm²A shell 114 of hard material having a yield strength in excess of (80,000 psi). Core 112 is a long element that takes the shape (appearance) of a substantially straight cantilever beam and is 0.00127-0.00762 cm (0.0005-0.0030 inch), [0.001 inch = 1 mil ≒ 25 micron (μm)]. The shell 114 is applied over the preformed core 112 by a suitable process such as a suitable plating process (eg, electrochemical plating).

1A shows a simple example of a spring shape for an interconnect element of the present invention, wherein the straight cantilever beam is positioned at an angle with respect to the force F applied to its tip 110b. When this force is exerted by the terminals of the electronic component where the interconnect element is to make a pressure contact, the downward deflection (as seen in the drawing) of the tip is evident at the tip (wiping movement) moving across the terminal. Such wiping contacts make the connection between the interconnecting element and the contacted terminals of the electronic component reliable.

The shell 114 imparts some elasticity to the entire interconnection element 110 by controlling its hardness and its thickness (0.002564-0.00500 inch). In this manner, an elastic interconnect element between electronic components (not shown) is formed between two terminals 110a and 110b of the interconnect element 110. (In FIG. 1A, reference numeral 110a denotes an end portion of the interconnect element 110, and an opposite end of the end 110b is not shown.) When connecting the terminals of the electronic component, the interconnect element 110 is indicated by an arrow. As shown by (F), the contact force (pressure) is applied.

The interconnect element (eg 110) is deflected in response to the applied contact force, which deflection (elasticity) is determined in part by the overall shape of the interconnect element and is excellent (with respect to the core) of the overcoating material. High) yield strength in part and partly in thickness of overcoating material.

As used herein, the term cantilever and cantilever beam are mounted (fixed) at one end with an elongated structure (such as, for example, overcoated core 112), and the other end is generally transverse to the longitudinal axis of the elongated device. It was used to indicate that it was free to move in response to a force acting on it. The use of these terms does not imply any other specific or restrictive meaning.

In FIG. 1B the electrical interconnect device 120 includes a soft core 122 and a hard shell 124. In this embodiment, it can be seen that the core 122 takes the shape with two bends and thus takes the S shape. In this manner as in the embodiment of FIG. 1A, an elastic interconnect element between electronic components (not shown) is formed between the two ends 120a and 120b of the interconnect element 120. (In FIG. 1B, reference numeral 120a denotes an end portion of the interconnect element 120, and an opposite end of the end 120b is not shown.) When connecting the terminals of the electronic component, the interconnect element 120 is indicated by an arrow. As shown by (F), the contact force (pressure) is applied.

In FIG. 1C, the electrical interconnect device 130 includes a soft core 132 and a hard shell 134. In this embodiment, it can be seen that the core 132 takes the shape with one bend and therefore takes the U shape. In this manner as in the embodiment of FIG. 1A, an elastic interconnect element between electronic components (not shown) is formed between the two ends 130a and 130b of the interconnect element 130. (In FIG. 1C, reference numeral 130a denotes an end portion of the interconnect element 130, and an opposite end of the end element 130b is not shown.) When connecting the terminals of the electronic component, the interconnect element 130 is indicated by an arrow. As shown by (F), the contact force (pressure) is applied. Alternatively, interconnect element 130 may be used to form a connection at a location other than its end 130b, as shown by arrow F '.

1D shows another embodiment of an elastic interconnect element 140 having a soft core 142 and a hard shell 144. In this embodiment the interconnect element 140 necessarily includes a simple cantilever (unlike FIG. 1A) with a curved tip 140b that receives a contact force F across its longitudinal axis.

1E shows another embodiment of an elastic interconnect element 150 having a soft core 152 and a hard shell 154. In this embodiment, the interconnect element 150 is suitable for taking the form C with the slightly curved tip 150b and making a pressurized connection as shown by arrow F. FIG.

The soft core can easily be formed into any spring shape, ie, the shape forms an interconnecting element that is elastically deflected in response to the force applied to the tip. For example, the core may be formed in a conventional coil shape. However, the coil shape is not preferable because it adversely affects a circuit operating at a high frequency (speed) due to the total length of the interconnect element and the related inductance.

At least one of the material of the shell or the multilayer shell (described later) has a significantly higher yield strength than the material of the core. Thus, the shell influences to achieve the mechanical properties (eg elasticity) of the interconnect structure. The yield strength ratio of shell to core is preferably at least 2: 1, including at least 3: 1, 5: 1, highest 10: 1. This ensures that at least the outer layer of the shell or multilayer shell is conductive, which is more pronounced when the shell covers the ends of the core. (However, in the case of the parent application, the case where the end of the core is exposed and the core must be conductive is described.)

From an academic point of view, only the spring (shape) portion of the composite interconnect element overcoated with a hard material is needed. In this respect, the two ends of the core to be overcoated are not necessary. In practice, however, it is desirable to overcoat the entire core. Particular reasons and advantages of overcoating the ends of the cores that are secured (attached) to the electronic components will be described in detail later.

Suitable materials for the cores 112, 122, 132, 142 include, but are not limited to, gold, aluminum, copper, and alloys thereof. These materials are alloys with small amounts of other metals such as beryllium, cadmium, silicon and magnesium in order to obtain the required physical properties. Moreover, silver, palladium, platinum, or its alloys, such as a metal of a platinum group, can also be used. Lead, tin, indium, bismuth, cadmium, antimony and alloys thereof may also be used to form solder.

Wires of any material that can be bent (using temperature, pressure and / or ultrasonic energy to perform the bending) for bonding by attaching the core to the terminals of the electronic component (described later in detail) implement the invention. Suitable for It is also within the scope of the present invention to use any material in the core that is bendable, including non-metallic materials, for overcoating (eg, plating).

Suitable materials for the shells 114, 124, 134, and 144 (and materials suitable for the individual layers of the multilayer shell as described later) include nickel and its alloys, copper, cobalt, iron and its alloys, good current carrying capacity and good Gold (particularly hard gold) and silver exhibiting contact resistance properties, but are not limited to, devices of the platinum group, rare metals, semi-rare metals and their alloys, in particular devices of the platinum group and their alloys, tungsten and molybdenum . Tin, lead, bismuth, indium and their alloys can be used when soldering finishes are required.

The method of choice for applying the coating material on the various core materials is different in each case as described later. Electrolytic plating and electroless plating are generally good methods. In general, however, plating on gold cores is counterintuitive.

According to one aspect of the present invention, when plating a nickel shell on a gold core (particularly, electrolytic plating), it is preferable to first apply a thin copper starting layer on the gold wire stem to facilitate the plating initiation operation.

Exemplary interconnect elements, as shown in FIGS. 1A-1E, have a core diameter of about 0.00254 cm (0.001 inch) and a shell thickness of 0.00254 cm (0.001 inch), so that the interconnect elements are approximately 0.00762 cm (0.003 inch; That is, it has the total diameter of core diameter + 2 times of shell thickness). In general, the thickness of the shell is 0.2-5.0 times the core thickness (diameter).

Examples of some parameters of the composite interconnect device are as follows.

(a) A gold wire with a diameter of 0.0381 mm (1.5 mils) has a shape of C-shaped curve (different from Figure 1E) with a total height of 1.016 mm (40 mils) and a radius of 0.2286 mm (9 mils). Take a final overcoating of nickel at a thickness of 0.01905 mm (0.75 mil) (total diameter = 1.5 + 2 × 0.75 = 3 mil) and 50 microinches of thickness (to lower and enhance contact resistance). Accept selectively. The composite interconnect device thus formed exhibits a spring constant (k) of about 3-5 grams / mil. (The term spring constant here means force per unit strain.) In use, a deflection of 3-5 mils results in a contact force of 9-25 grams. This embodiment is useful in the case of spring elements for interposers.

(b) A gold wire with a diameter of 0.0254 mm (1.0 mil) has a height of 35 mils in total and has a curved cantilever shape, nickel plated to a thickness of 0.03175 mm (1.25 mils) (total diameter = 1.0 + 2 × 1.25 = 3.5 mil), 50 microin thick, optionally accepts the final overcoating in gold. The composite interconnect element thus formed exhibits a spring constant k of about 3 grams / mil and is useful in the case of probe spring elements.

As will be explained in more detail below, the core element need not have a round cross section, but rather may be a flat tab (ribbon) (having a rectangular cross section) extending from the sheet. As used herein, the term tab is a term different from Tape Automated Bonding (TAB).

Further, the cross section of the wire stem may be rectangular or other non-circular, which is within the scope of the present invention.

Multilayer shell

2A shows a specific example 200 of an interconnect element 210 mounted to an electronic component 212 having a terminal 214. In this embodiment, the soft (eg gold) wire core 216 is coupled (attached) to the terminal 214 at one end, extending from the terminal and taking a spring shape (other than the shape shown in FIG. 1B) and It is cut | disconnected to have the free end 216b. Joining, shaping, and cutting wires in this manner is accomplished by using wire bonding equipment. Coupling at the end 216b of the core covers only a relatively small portion of the exposed surface of the terminal 214.

The shell (overcoat) is disposed over the wire core 216 shown in this embodiment as having an inner layer 218 and an outer layer 220 which are multi-layered and appropriately applied by the plating process. One or more layers of the multilayer shell are formed of a hard material (eg, nickel and its alloys) to impart the required elasticity to the interconnect element 210. For example, the outer layer 220 may be a hard material, and the inner layer may be a material that acts as a buffer or a blocking layer (or an active layer or an adhesive layer) when the hard material 220 is plated on the core material 216. Alternatively, inner layer 218 may be a hard material, and outer layer 220 may be a material (eg, soft gold) that exhibits excellent electrical properties, including conductivity and solderability. If solder or soldered connections are required, the outer layers of the interconnect elements can be made of lead-tin solder or gold-tin solder material, respectively.

Fixation to terminal

Figure 2A illustrates another key feature of the present invention in a general manner, showing that the elastic interconnect element can be securely fixed to a terminal on an electronic component. The attachment end 210a of the interconnection element is subjected to significant mechanical stress, resulting in a compressive force F applied to the free end 210b of the interconnection element.

As shown in FIG. 2A, overcoats 218 and 219 cover core 216, and the entire remaining exposed surface of the terminal 214 adjacent to core 216 in a continuous (non-interruptive) manner (i.e. And parts other than 216a). This firmly and reliably secures the interconnect elements 220 to the terminals, and the overcoating material contributes to securing the interconnect elements to the terminals (eg, 50% or more). In general, the overcoating material is only required to cover at least a portion of the terminal adjacent the core. However, the overcoating material preferably covers the entire remaining surface of the terminal. It is preferable that each layer of a shell becomes metallic.

In general, the relatively small area where the core is to be attached (coupled) to the terminal is not suitable for receiving the stresses arising from the contact force F imposed on the interconnect element. The entire interconnect structure is firmly attached to the terminal by a shell covering the entire exposed surface of the terminal (other than a relatively small area including the core end 216a attachment to the terminal). The ability to respond to the adhesive strength and contact force of the overcoating is very good compared to the ability at the core end itself.

As used herein, the term electronic component (eg, 212) includes semiconductor wafers and dies of any suitable semiconductor material, such as interconnect and interposer base layers, silicon (Si) or gallium arsenide (GaAs), Interconnect sockets, test sockets, sacrificial members, devices and substrates as described in the parent application, semiconductor packages including ceramic and plastic packages and chip carriers, connectors, including but not limited to.

The interconnect elements of the present invention are particularly suitable for the following uses.

Interconnect elements mounted directly on the silicon die without the need for semiconductor packages;

Interconnection elements (described in detail later) extending from the substrate as probes for testing electronic components,

Interconnection elements of the interposer (described in detail later).

The interconnect elements of the present invention are unique and have the advantage of obtaining the mechanical properties (eg high yield strength) of the hard material without being limited by the bad bonding properties typical of the hard material. As described in the parent application, this offers the possibility that the shell (overcoating) will function as a structure overlapping on the poles' walkwork, both terms being used mainly in the field of civil engineering. This is very different from conventionally plated interconnect elements in which plating was used as a protective (eg, corrosion resistant) coating and could not impart certain mechanical properties to the interconnect element.

Among the several advantages of the present invention, a plurality of free standing interconnect structures are readily formed on a substrate such as a PCB having a separate capacitor at a height different from the common height above the substrate such that their free ends are located in a common plane with each other. . In addition, the electrical and mechanical properties (eg plasticity and elasticity) of the interconnect elements according to the invention are easily obtained in special applications. For example, in certain applications, it is desirable for the interconnect elements to exhibit plasticity and elastic deformation. (The plastic deformation preferably accommodates the components interconnected by the interconnecting elements in a non-planar form as a whole.) When elastic properties are required, the interconnecting elements generate the minimum contact force required to perform a reliable connection. Needs to be. In addition, the tip of the interconnect element forms a wiping contact with the terminal of the electronic component due to the occasional contamination film on the connection surface.

As used herein, the term elastic refers to an elastic structure (interconnecting element), which is mainly applied to a contact structure and exhibits elastic behavior in response to an applied load (contact force), and the term compliant refers to an applied load ( It refers to a contact structure (interconnection element) which exhibits both elasticity and plastic behavior in response to contact force). The following contact structure used here is an elastic contact structure. The composite interconnect device of the present invention is a special case which is either a follower or elastic contact structure.

The parent application has several features: a method of manufacturing an interconnect element on a sacrificial substrate, a method of transferring a plurality of interconnect elements to electronic components singly, a method of providing a connection tip with a rough surface finish on the interconnect element, A method of using an interconnect element on an electronic part to make a temporary connection to the electronic part and then to make a permanent connection, a method of arranging the interconnect element to have a different space at one ends rather than opposing ends, and manufacturing the interconnect element A method of manufacturing and arranging the spring clips in the same process steps as the ones used, a method of using the interconnect elements to accommodate the difference in thermal expansion between the connected parts, a method of eliminating the need to separate the semiconductor package (for the SIMM), A method of selectively soldering an elastic interconnect element (elastic connection structure) is described. , But it is not limited to.

Controlled impedance

2B shows a composite interconnect device 220 having multiple layers. The innermost portion of the interconnect element 220 (inner long conductive element 222) is an uncoated or overcoated core, as described above. Tip 222b of innermost portion 222 is masked with a suitable masking material (not shown). The dielectric layer 124 is applied over the innermost portion 222 by an electroless process or the like. The outermost portion 226 of the conductive material is applied over the dielectric layer 124.

In use, electrically grounding the outer layer 226 causes the interconnect element 220 to have a controlled impedance. One example of the dielectric layer 124 material is a polymeric material and is applied in any suitable method and thickness (eg, 0.00254-0.0762 mm (0.1-3.0 mil)).

The outer layer 226 may be multilayered. For example, if the entire interconnection element needs to be elastic when the innermost portion 222 is an uncoated core, at least one layer of the outer layer 226 is made of spring material.

Changing pitch

2C shows a plurality (only six) of interconnection elements 251,..., 256 mounted on the surface of an electronic component 260, such as a probe card insert (an assembly conventionally mounted to a probe card). Example 250 is shown. Terminals and conductive traces of the probe card insert are not shown in the figures for clarity. The attachment ends 251a, ..., 256a of the interconnect elements 251, ..., 256 form a first pitch (space), such as 0.127-0.254 cm (0.05-0.10 inch). The interconnect elements 251, ..., 256 take a shape and direction such that their free ends (tips) are at a second finer pitch, such as 0.0127-0.0254 cm (0.005-0.010 inch). An interconnect assembly that interconnects from one pitch to another is called a space transformer.

As shown, the tips 251b, ..., 256b of the interconnect elements are arranged in two parallel rows to make a connection (for testing and / or firing) to a semiconductor device having two parallel rows of coupling pads (contacts). Are arranged. The interconnect elements are arranged to have different tip patterns to make connections to electronic components having different contact patterns as an array.

Generally, only one interconnection element is shown in the embodiments described herein, but the present invention manufactures a plurality of interconnection elements and spaces the plurality of interconnection elements apart from each other such that they have a predetermined distance from each other, such as a peripheral pattern or a rectangular array pattern. The same applies to arranging.

Techniques for using the sacrificial base

Direct attachment of the interconnect element to the terminal of the electronic component has been described above. In general, the interconnect elements of the present invention may be manufactured or mounted on any suitable surface of any suitable substrate, including a sacrificial substrate.

Referring to Fig. 11A through Fig. 11F, a method of manufacturing a plurality of interconnect structures (e.g., elastic connection structures) as a separating and dividing structure for continuous mounting on electronic components, and Figs. 12A to 11F. Referring to 12C, a method of mounting a plurality of interconnect elements on a sacrificial substrate (carrier) and then transferring them all at once to an electronic component is described.

2D-2F illustrate a method of fabricating a plurality of interconnect elements having a preformed tip structure using a sacrificial base layer.

2D illustrates a first step of a method of applying a patterned layer of masking material 252 to the surface of sacrificial base layer 254. The sacrificial base layer 254 is, for example, a thin [0.0254-0.254 mm (1-10 mil)] copper, aluminum foil or silicon substrate, and the masking material 252 is a conventional photoresist. Masking layer 252 takes a pattern such that at locations 256a, 256b, and 256c, there are a plurality of openings (only three are shown) needed to fabricate interconnect elements. The positions 256a, 256b and 256c are compared to the terminals of the electronic component. The positions 256a, 256b, 256c are preferably treated at this stage to have a rough or shaped surface texture. As shown, the method is mechanically accomplished by an embossing tool 257 that forms a recess in the foil 254 at locations 256a, 256b, 256c. Unlike this. At these locations the surface of the foil may be chemically etched to have surface texture. Any method suitable for achieving this overall purpose, for example sand blasting and pinning, is also within the scope of the present invention.

Next, a plurality of (only one) conductive tip structures 258 are formed at each location (eg, 256b) in the manner shown in FIG. 2E. This is accomplished by using any suitable method, such as electrolytic plating, and may include a tip structure having a multilayer material. For example, tip structure 258 has a thin (eg, 10-100 microinches) nickel barrier layer applied on the sacrificial base layer, a thin (10 microinches) soft gold layer, thin (20 microinches) hard It is applied with a gold layer, a relatively thick (200 microinches) nickel layer, and finally a thin (100 microinches) soft gold layer. In general, the first thin barrier layer of nickel protects subsequent gold layers that are neutralized by the material of base layer 254 (eg, aluminum, copper), and the relatively thick nickel layer gives strength to the tip structure, The final thin soft gold layer provides a surface that allows for easy bonding. The present invention is not limited to the particular method by which the tip structure, which will vary with use, is formed on the sacrificial substrate.

As shown in Fig. 2E, a plurality of (only one) cores 260 for the mutual coupling element are formed on the tip structure 258 by any method or the like that couples the soft wire cores to the terminals of the electronic component as described above. It may be formed. The core 260 is then overcoated with a hard material 262, preferably in the manner described above, and the masking material 252 has been removed and mounted to the surface of the sacrificial substrate as shown in FIG. 2F. Free standing interconnect elements 264 (only three are shown) are formed.

Similar to the overcoating material covering at least the adjacent region of the terminal 241 described with reference to FIG. 2A, the overcoating material 262 also firmly secures the core 260 to their respective tip structures 258 and is necessary. Some impose elastic properties on the interconnect element 264. As described in the parent application, a plurality of interconnecting elements mounted on the sacrificial base may be transferred all at once to the terminals of the electronic component. Alternatively, it may take two widely diverged passageways.

It can be seen that the silicon wafer can be used as a sacrificial base from which the tip structure is fabricated, and that the tip structures so fabricated can be connected (eg, soldered or brazed) to an elastic contact structure already mounted on the electronic component. It is within the scope of the invention. Additional description of this technique is defined in the following Figures 8A-8E.

As shown in Figure 2G, the sacrificial base layer 254 may be simply removed by any suitable process, such as selective chemical etching. Since most chemical etching processes are etched with one material at a much higher rate than other materials, the other material is only slightly etched in this process, which eliminates the sacrificial base layer while simultaneously removing the thin nickel barrier layer of the tip structure. Preferably used. However, if desired, the thin nickel barrier layer can be removed in each subsequent step. This causes multiple (only three) individual discrete interconnect elements 264 to be shown as dashed lines and then mounted (by soldering or soldering, etc.) to the terminals on the electronic component.

The overcoating material may be slightly thinner in the process of removing the sacrificial base layer and / or the thin barrier layer. However, it is preferable that this phenomenon does not occur.

In order to prevent overcoating from thinning, it is desirable to apply a thin gold layer or a layer of soft gold, for example 10 microinches, applied over hard gold of about 20 microinches as the final layer over the overcoating material 262. This gold outer layer is intended to have good conductivity, contact resistance and solderability and exhibits high impermeability to most etching solutions intended to be used to remove thin barrier and sacrificial base layers.

Alternatively, as shown in FIG. 2H, a thin (with only three) interconnect elements 264 having a plurality of holes in itself upon removal of the sacrificial base 254 before removal of the sacrificial base 254. The plate or the like may be fixed to each other by any suitable supporting structure 266 in a predetermined spaced relationship. The support structure 266 may be a dielectric material or a conductive material overcoated with the dielectric material. Subsequently, subsequent processing steps (not shown) may be performed, such as mounting a plurality of interconnect elements to an electronic component, such as a silicon wafer or printed circuit substrate. In addition, in some applications it is necessary to stabilize the tip of the interconnect element 264 (opposite to the tip structure) to prevent it from being removed, especially when contact force is applied thereto. To this end, it is necessary to limit the movement of the tip of the interconnect element with a suitable sheet 268 such as a mesh having a plurality of holes formed of dielectric material.

Another advantage of the method 250 described above is that the tip structure 258 may be formed of any desired material and any desired tissue. As described above, gold is an example of a rare metal that exhibits excellent electrical properties, low contact resistance, solderability and corrosion resistance. In addition, because gold is a good material, it is well suited for the final overcoating applied on the interconnect elements described herein, in particular the elastic interconnect elements. Other rare metals likewise exhibit desirable properties. However, some materials, such as rhodium, exhibit good electrical properties but are not suitable for overcoating the entire interconnect device. For example, rhodium is brittle and difficult to perform with final overcoating on elastic interconnect elements. In this regard, the method illustrated by method 250 easily addresses this limitation. For example, the first layer of the multilayer tip structure (see 258) can be made of rhodium (rather than gold as described above) to provide excellent electrical properties for making connections to electronic components without compromising the mechanical properties of the interconnect elements. Indicates.

2I illustrates a modification embodiment 270 for fabricating interconnect devices. In this embodiment, the masking material 272 is applied to the surface of the sacrificial base layer 274 and patterned to have multiple (only one) openings 276 in a manner similar to the method described above with respect to FIG. 2D. do. The opening 276 defines the area of the interconnect element that is to be manufactured as a free upright structure. (As generally described herein, the interconnect element has one end coupled to the terminal or sacrificial base layer of the electronic component and the opposite end of the interconnect element becomes free standing when not coupled to the electronic component or sacrificial base layer.)

The area within the opening is shaped in any suitable manner to have one or more recesses as shown by a single recess 278 extending to the surface of the sacrificial base layer 274.

The core (wire stem) 280 is bonded to the surface of the sacrificial base layer in the opening 276 to take any suitable shape. In this embodiment, only one end of the interconnect element is shown for clarity of illustration. The other end (not shown) may be attached to the electronic component. It can be seen that the method 270 differs from the method 250 described above that the core 280 is attached directly to the sacrificial base 274 rather than the tip structure 258. By way of example, the gold wire core 280 is easily bonded to the surface of the aluminum base layer 274 using conventional wire bonding methods.

In the next step of the method 270, a gold layer 282 is applied (by plating) on the core 280 and on the exposed area of the base layer 274 in the opening 276 included in the recess 278. Is applied. The main purpose of this layer 282 is to form a connection surface at the end of the interconnect element (after the sacrificial base layer is once removed).

Next, a layer 284 of relatively hard material of nickel or the like is applied over the layer 282. As described above, one main purpose of the layer 284 is to impart certain mechanical properties (elasticity) to the composite interconnect device. In this embodiment, another purpose of layer 284 is to enhance the durability of the connection surface fabricated at the bottom of the interconnect element. A final layer of gold (not shown) is applied to layer 284 to enhance the electrical properties of the interconnect device.

In the final step, the masking material 272 and the sacrificial base layer 274 are removed, thereby allowing a plurality of unified interconnect elements (different from Fig. 2G) or a plurality of interconnections spaced in a predetermined relationship to each other (different from Fig. 2H). The device is formed.

This embodiment 270 illustrates an example of a method of manufacturing a shaped tip on an end of an interconnect element. In this case, an excellent example of gold over nickel has been described. However, it is also possible to manufacture other similar connecting tips at the ends of the interconnecting elements in accordance with the methods described above within the scope of the present invention. Another feature of this embodiment 270 is that the connecting tip is made entirely over the sacrificial base 274 rather than being manufactured within the surface of the sacrificial base 254 as in the previous embodiment 250.

General information about interposers and space transformers

The technique described above generally describes a novel technique for assembling a composite interconnect element, the physical properties of which are well suited for facilitating alignment to develop a desired elasticity and for making pressure connections with terminals of electronic components. It may be combined with a tip structure having surface tissue.

In general, the composite interconnect elements of the present invention are easily mounted (or assembled) on a substrate that functions as an interposer, and are arranged and interconnected between two electronic components, one for each side of the interposer. Assembly and use of composite interconnect elements in an interposer is described in detail in the concurrently owned, concurrent US patent application Ser. No. 08 / 526,426. Such an application discloses various techniques for closely inspecting a semiconductor device.

The use of the interconnect device of the present invention in an interposer has been described above. In general, as used herein, an interposer is a substrate having contact portions on two opposing surfaces as disposed between two electrical components for interconnecting two electronic components. In some cases, it may be desirable for the interposer to allow at least one of the two interconnect electronic components to be removable (eg, to replace, upgrade, implement technical changes, etc.).

FIG. 3 illustrates one embodiment of a generic interposer 300, such as any one of various interposers as previously described in several patent applications of officially owned patent applications as described above. will be.

In general, an insulated substrate 302, such as a PCB-type substrate, is provided with a plurality of terminals (304, 306) on one surface 302 and the same number of terminals 308, 310 is provided on the surface 302b opposite the surface. Each of the spring contacts 312 and 314 (not shown in the top coating for clarity) is mounted to each of the terminals 304 and 306 and the spring contacts 316 and 318 (for clarity). Each of the top coating is omitted) is mounted to each of the terminals 308, 310. Such spring contacts are preferably a composite interconnect element of the type already disclosed in Fig. 2A, but these spring contacts are unitary spring elements.

As mentioned in the concurrently owned concurrent US patent application Ser. No. 08 / 554,902, the interposer has a different set of spring elements on its respective side (FIG. 3A of the above-mentioned US patent application Ser. No. 08 / 554,902). A spring element (see, for example, US Pat. App. 08 / 554,902, FIG. 3B and FIG. 3), which is supported (eg, by solder or elastomer) in a hole extending through the support substrate 302. 3C).

The spring elements 312, 314, 316, and 318 of FIG. 3 are suitably formed as composite interconnect elements as described above, and the illustration of the top coating is omitted for clarity.

It will be apparent that any elastic interconnect member (spring) may be used, including a unitary spring member made of an inherently elastic material such as phosphor bronze and beryllium copper. This is also true of the various embodiments disclosed herein illustrating the composite interconnect member.

The present invention is also top coated with a hard metal by forming an interconnect member formed from a patterned soft metal plate (by pressing or etching) into a flat, long member (tab, ribbon). This has been found in officially owned concurrent US patent application Ser. No. 08 / 526,246.

Spatial transformation (sometimes referred to as pitch expansion) is an important concept applied to the present invention. In short, it is often important that the ends (ends) of the elastic contact structure are spaced apart from one another (with relatively fine pitches) closer than the adjoining bases. As illustrated in FIG. 2C mentioned above, this is accomplished by shaping and orienting each spring member 251-256 to converge with each other, with the result that each elastic contact structure tends to have a different length. This happens. In general, in a probe card assembly, it is very important that all the probe members (elastic contact structures) have the same length as the other so as to ensure consistency within the number of single paths involved.

4 illustrates an exemplary configuration of a space transducer component 400 (not shown for spring members for clarity), wherein a given spatial transformation is each elastic contact (not shown) attached thereto. This is achieved by the substrate 402 of the spatial transducer rather than the shape of the structure.

The space converter substrate 402 has an upper surface 402a (in perspective direction) and a lower surface 402b, with multiple layers having alternating insulating and conductive materials (such as ceramics, for example). It is preferable to form as a layer part. In this embodiment, one wiring layer is shown to include two conductive traces 404a and 404b (among several conductive traces).

A plurality of terminals 406a, 406b (only two of which are shown) are disposed (or recessed within) at a relatively fine pitch (relatively close to each other) on the top surface 402a of the space transducer substrate 402. )do. A plurality of terminals 408a and 408b (only two of which are shown) are arranged in coarse pitch on the lower surface 402b of the space converter substrate 402 (away from each other with respect to the terminals 406a and 406b). Or recessed therein). In one example, the bottom terminals 408a and 408b are disposed at a pitch of 1.27 mm to 2.54 mm (comparable to the pitch limit of the printed circuit board) and the top terminals 406a and 406b are spaced between centers of the semiconductor die bond pads. With a pitch of 0.127 mm to 0.254 mm (comparable to distance), resulting in a pitch shift of 10: 1. Each of the upper terminals 406a, 406b is connected to each of the corresponding bottom terminals 408a, 408b by the attached conductors 410a, 412a, 410b, 412b so that these terminals are connected to each of the conductive traces 404a, 404b. . All of these are well understood in the context of a multi-layer land grid array (LGA) support substrate.

Probe card assembly

5, 5A, and 5B are taken directly from officially owned concurrent US patent application Ser. No. 08 / 554,902. As will be described in detail below, the present invention is very useful in connection with the space converter of US patent application Ser. No. 08 / 554,902, but its use is not limited thereto.

5 includes a probe card 502, interposer 504, and space transducer 504 as main functional components and suitable for use in temporary interconnection to semiconductor wafer 508. An example of this is shown. In this exploded cross-sectional view, specific members of specific components are exaggerated for clarity. However, the vertical alignment of the various parts (as shown) is appropriately indicated by dashed lines in the figures. The interconnect members 514, 516, 524 (described in detail below) are shown in their entirety, not in part.

The probe card 502 is a conventional circuit board generally having a plurality of contact areas (terminals) 510 (only two of which are shown) disposed on the top surface (as shown). Additional components (not shown), such as active and passive electronic components and connectors, may be mounted to the probe card. Terminals 510 on the circuit board may generally be arranged at 2.54 mm per pitch (as defined above for pitch). Probe card 502 is suitably circular, having a diameter of about 30.5 cm (12 inches).

Interposer 504 includes a substrate 512 (comparable to substrate 302). In the same manner as described above, a number of elastic interconnect members 514 (only two of which are shown) are mounted to and from the bottom surface (as shown) of the substrate 512 (by its distal end). Extending downwards (as shown) and correspondingly a plurality of elastic interconnect members 516 (only two of which are shown) (by its proximal end) to the top surface of the substrate 512 (shown) As shown) and extend upwards (as shown) therefrom. Any shape of the spring as described above is suitable for the elastic interconnect members 514 and 516, with the composite interconnect members of the present invention being preferred. As a general suggestion, the front end (end) of both the plurality of lower interconnect members 514 and the plurality of upper interconnect members 516 corresponds to the pitch of the terminal 510 of the probe card 502, for example 2.54. It is arranged at a pitch of mm. Interconnect members 514 and 516 are shown in exaggerated size for clarity of illustration. Typically, interconnect members 514 and 516 extend from 0.51 mm to 2.54 mm total height from each of the lower and upper surfaces of interposer substrate 512. In general, the height of the interconnect member has been described as a given compliance size.

Spatial transducer 506 is provided on a plurality of terminals (contact area, pads) 520 (only two of which are shown) and on top (as shown) disposed on the bottom (as shown). A properly circuitd substrate 518 (substrate 402 as described above), such as a multilayer ceramic substrate having a plurality of terminals (contact areas, pads) 522 (only two of which are shown) disposed; Compared). In this embodiment, the plurality of lower contact pads 520 are disposed at the leading pitch of the interconnect member 516 (eg, 2.54 mm) and the plurality of upper contact pads 522 have a finer (closer) pitch. (For example, 1.27 mm). Such elastic interconnect members 514 and 516 are preferably but not essential to the composite interconnect member of the present invention (compared to member 210 as described above).

A number of elastic interconnect members (probes, probe members) 524 (only two of which are shown) are connected directly to the terminal (contact pad) 522 (by its distal end) (ie, the probe member Additional material, such as soldering or soldering a wire or probe member and a terminal connected to the terminal, is mounted upwards (as shown) from the top surface (as shown) of the space converter substrate 518. Is extended). As shown, such an elastic interconnect member 524 is suitably arranged such that its tip (end) is spaced at a uniform and finer pitch (eg 0.254 mm) than its proximal end, whereby a space transducer ( The pitch reduction of 506 is increased. Such an elastic contact structure (interconnect member) 524 is preferably, but not necessarily, a composite interconnect member of the present invention (compared to the member 210 described above).

A probe member 524 is fabricated on an electrically conductive surface (see FIGS. 2D-2F) and then mounted to the terminal 522 of the space transducer component 506 (see FIG. 2G) or delivered in a bunch (FIG. 2H). Belong to the scope of the present invention.

As is known, semiconductor wafer 508 includes a number of die sites (not shown) formed on the front face (bottom face as shown) by photolithography, deposition, diffusion, and the like. Typically, these die sites are made identical to each other. However, as is known, defects in the wafer itself or in any process in which the wafer is processed to form a die site may result in certain die sites becoming nonfunctional according to well established test conditions. Often due to the difficulties associated with probing the die site prior to specifying the semiconductor die from the semiconductor wafer, the test is performed after the specification and packaging of the semiconductor die. If a defect is found after packaging the semiconductor die, the net loss is exacerbated by the costs associated with packaging the die. Semiconductor wafers typically have a diameter of at least 15.24 cm, including a diameter of at least 20.32 cm.

Each of the die sites typically has a plurality of contact areas (eg, bond pads), which are disposed in any pattern at any location on the surface of the die site. Two bond pads 526 (of several bond pads) of either die site are shown in the figure.

A small number of techniques are known for testing die sites prior to characterizing the die sites with each semiconductor die. Representative prior art involves fabricating a probe card insert having a plurality of tungsten needles embedded in and extending from a ceramic substrate, such that each needle makes a temporary connection to any one bond pad. . Such probe card inserts are expensive and somewhat complex in manufacturing, and thus the manufacturing cost is relatively expensive and the time to obtain is considerable. Given the wide variety of bond pad devices available for semiconductor dies, each bond pad device must be unique to vary the probe card insert.

The rapidity in the fabrication of unusual semiconductor dies represents a rapidly demanding demand for probe card inserts that are simple and inexpensive to manufacture while shortening process turnaround times. The use of the interposer 504 and the space transducer 506 as probe card inserts is an accurate indication of such an irresistible need.

In use, the interposer 504 is disposed on the top surface (as shown) of the probe card 502 and the spatial transducer 506 is stacked on top of the interposer 504 (as shown). The interconnect member 514 makes a reliable press contact with the contact terminal 510 of the probe card 502 and the interconnect member 516 makes a reliable press contact with the contact pad 520 of the spatial transducer 506. Is achieved. Any suitable mechanism for laminating these parts and making a reliable press contact may be used, one of which is described below.

The probe card assembly 500 includes a back mounting plate 530 made of a rigid material, such as stainless steel, which includes the interposer 506 and the space transducer 506 stacked on the probe card 502 as follows: And an actuator mounting plate 532 made of a rigid material such as stainless steel, a front mounting plate 534 made of a rigid material such as stainless steel, an external differential screw element 536 and an internal differential screw element 538. A mounting ring having a plurality of differential screws (only two of which are shown, three of which are preferred) and a pattern of elastic tabs (not shown) which are preferably made from an elastic material such as phosphor bronze and extend from it 540 and a plurality of (only two of them shown) screws 534 for holding the mounting ring 538 on the front mounting plate 534 with the space transducer 506 interposed therebetween, and Accept tolerance An optional spatial ring 544 disposed between the mounting ring 540 and the spatial transducer 506, and on top of the differential screw (as shown) (eg, at the top of the internal differential screw element 538). ) Arranged a plurality of (only two of them are shown) pivot sphere 546.

The rear mounting plate 530 is a metal plate or ring (shown in the figure as a ring) disposed on the bottom surface (as shown) of the probe card 502. Multiple (only two of them shown) holes 548 extend through the rear mounting plate.

The actuator mounting plate 532 is a metal plate or ring (shown in the figure as a ring) disposed on the bottom surface (as shown) of the rear mounting plate 530. Multiple (only two of them shown) holes 550 extend through the actuator mounting plate. In use, the actuator mounting plate 532 is secured to the rear mounting plate 530 in any suitable manner, such as by screwing (not shown in the drawings for clarity).

The front mounting plate 534 is rigid, preferably a metal ring. In use, the front mounting plate 534 is rearwarded in any suitable manner, such as with screws extending through corresponding holes (not shown in the drawings for clarity) through the probe card 502. It is fixed to the mounting plate 530 (not shown in the drawings for clarity), whereby the probe card 520 is firmly fixed between the front mounting plate 534 and the rear mounting plate 530.

The front mounting plate 534 has a flat lower surface (as shown) disposed relative to the upper surface (as shown) of the probe card 502. The front mounting plate 534 has a large center hole through which it is formed by an inner edge 552, the size of which is shown by the number of contact terminals 510 of the probe card 502. As such, it is sized to be present in the central hole of the front mounting plate 534.

As described above, the front mounting plate 534 is a ring-shaped structure having a flat lower surface (as shown). The upper surface (as shown) of the front mounting surface 534 is stepped, wherein the thickness in the outer region (vertical range in the figure) of the front mounting surface is thicker than the thickness in the inner region. The step or shoulder is positioned at the location of the dashed line 554 and the size is such that the space transducer 5506 lies on the inner region of the front mounting plate 534 with a gap with the outer region of the front mounting plate ( However, as can be seen from the figure, the spatial transducer is substantially on the pivot sphere 546).

A plurality of (one of which is shown) holes 554 extend at least the front mounting plate 534 from the top surface (as shown) of the front mounting plate 534 into the outer region of the front mounting plate 534. Extending partially through (these holes are shown as only partially penetrating the front mounting plate 534 in the drawing), as can be seen in the drawing to accommodate the corresponding ends of a plurality of screws 542 do. For this purpose, a screw is formed in the hole 554. This allows the space transducer 506 to be fixed to the front mounting plate by the mounting ring 540, thereby pressing against the probe card 502.

A plurality of (only one of the plurality) holes 558 extends through the thin inner region of the front mounting plate 534 and extends through the probe card 502 (only one of the many) And holes 550 in the rear mounting plate and eventually the holes 550 in the actuator mounting plate 538.

The pivot sphere 546 is loosely disposed in the holes 558, 560 aligned at the top end (as shown) of the internal differential screw element 538. The external differential screw element 536 is screwed into the (threaded) hole 550 of the actuator mounting plate 532 and the internal differential screw element 538 is screwed into the threaded hole of the external differential screw element 536. do. In this way, the position of each pivot sphere 546 can be adjusted very finely. In one example, external differential screw element 536 has an external screw of 72 screws per inch, and internal differential screw element 538 has an external screw of 80 screws per inch. Advancing the external differential screw element 536 in one revolution in the actuator mounting plate 532 and holding the corresponding internal differential screw element 538 (relative to the actuator mounting plate 532) results in a corresponding pivot sphere ( The net change in the position of 546 is (+) 1/72 (0.0139) inches (0.3531 mm), (−) 1/80 (0.0125) inches (0.3175 mm) or 0.0014 inches (0.0356 mm). This makes it possible to adjust the planarity of the space transducer 506 easily and precisely compared to the probe card 502. Therefore, the position of the tip (the upper end as shown) of the probe (interconnection member) 524 can be changed without changing the direction of the probe card 502. These features, techniques for performing probe tip alignment, and optional mechanisms for adjusting the planarity of the spatial transducers are described in more detail in officially-owned concurrent US patent application Ser. No. 08 / 554,902. It is described. Obviously, the interposer 504 is electrically connected between the space transducer 506 and the probe card 502 over the adjustment range of the space transducer by an elastic contact structure or compliant contact structure disposed on both surfaces of the interposer. Let it go.

The probe card assembly 500 places the interposer 504 in the hole 552 of the front mounting plate 534 such that the tip of the interconnect member 514 contacts the contact terminal 510 of the probe card 502. And the spatial transducer 506 is placed on top of the interposer 504 such that the tip of the interconnect member 516 contacts the contact pad 520 of the spatial transducer 506, and optionally the spacer 544. Position the top of the space transducer 506, position the mounting ring 540 over the spacer 544, and penetrate the spacer 544 through the mounting ring 540 to allow holes in the front mounting plate 534 ( 554 and the lower surface of the front mounting plate 534 (as shown) through a screw (only one partially shown) 555 through the rear mounting plate 530 and the probe card 520. This preassembly is inserted by inserting it into a threaded hole (not shown) in the By mounting the card lobe 502, it can simply be assembled. The actuator mounting plate 538 is then assembled to the rear mounting plate 530 (e.g., by screws 556, which are only partially shown in the figures), and the pivot sphere 560 is a hole in the actuator mounting plate 532. Falling into 550, the differential screw elements 536, 538 are inserted into the holes 550 of the actuator mounting plate 532.

In this manner, a plurality of elastic contact structures extending from itself to make contact with a plurality of bond pads (contact areas) on a semiconductor die at a fine pitch to match today's bond pad space prior to singulation from the semiconductor wafer. A probe card having 524 is provided. In general, in use, assembly 500 may be used inverted from the state shown in the figures, wherein the semiconductor wafer is pushed (by an external device, not shown) onto the tip of elastic contact structure 524. I will go.

As can be clearly seen from the figure, the front mounting plate (substrate plate) 524 determines the position of the interposer 504 relative to the probe card 502. In order to accurately position the front mounting plate 534 relative to the probe card 502, a number of alignment devices (not shown in the drawings for clarity) and probe cards (such as pins extending from the front mounting plate) A hole extending into 502 may be provided.

Interposers 504 and / or any suitable elastic contact structures 514, 516, 524 including tabs (ribbons) made of phosphor bronze material, or the like, soldered or soldered to each interposer or contact area on the space transducer. Or use in the space transformer 506 is within the scope of the present invention.

The interposer 504 and the like are described as elements 486 of FIG. 29 of officially owned concurrent patent application No. PCT / US94 / 13373 as described above, such as spring clips extending from the interposer substrate. It is also within the scope of the present invention to pre-assemble the space transducers 506 with each other.

It is also within the scope of the present invention to omit the interposer 504 and instead mount a number of elastic contact structures comparable to the member 514 directly on the contact pad 520 on the bottom surface of the spatial transducer. However, maintaining coplanarity between the probe card and the space transducer is difficult. The basic function of the interposer is to provide compliance to ensure such coplanarity.

Space converter board

As described above, the present invention is very advantageous when used in connection with a spatial transducer which is a component part of the probe assembly.

On the other hand, the spatial transducer 506 of the probe assembly described in the officially owned concurrently pending US patent application Ser. No. 08 / 554,902 is adapted to have a spring (probe) element mounted (directly assembled) on its upper surface. Although preferably manufactured, the present invention avoids the problem of coupling the spring element to the top surface of the spatial transducer component and extends the range of usability of the entire probe assembly.

5A is a perspective view illustrating a space converter substrate 518 suitable for the probe card assembly 500 of FIG. As shown in this figure, the space converter substrate 518 is preferably a rectangular solid body having a length L, a width W, and a thickness T. This figure shows the top surface 518a of the space converter substrate 518, which is mounted with a probing interconnect element 524. As shown, multiple (eg, hundreds) contact pads 522 are disposed in a predetermined area on the top surface 518a of the space converter substrate 518. The predetermined area is indicated by a dashed line 570, as will be apparent, the contact pads 520 are arranged in any suitable pattern within the predetermined area 570.

As described above, the space converter substrate 518 is suitably formed of a multilayer ceramic substrate having layers of alternating layers of ceramic layers and patterned conductive materials.

The manufacture of such multilayer ceramic substrates is known and is used in the manufacture of land grid array (LGA) semiconductor packages, for example. By appropriately determining the path of the patterned conductive material in the multilayer substrate as described above, the contact pads (not shown in the figures and compared to 520) are placed on the bottom surface (not shown in the figures) of the substrate 518. The contact pads 520 together with the contact pads 522 can be disposed simply and directly at a pitch different from the pitch of the contact pads 522 on the top surface 518a of the 518 (eg, a larger pitch). The substrate 518 may be integrally contacted with each other. It is very easy to set the pitch between the contact pads 522 on the substrate to about 0.254 mm (10 mil).

5A shows a preferred configuration of the space converter substrate 518. As described, the substrate 518 is a rectangular solid body having an upper surface 518a, a lower surface (not shown), and four side edges 518b, 518c, 518d, and 518e. As shown, notches 572b, 572c, 572d, and 572e are provided along the side edges 518b, 518c, 518d, and 518e, respectively, and the top surface 518a of the substrate 518 is defined by the side edges 518b, 518c, 518d, 518e) along the entire length of each (except corner). These notches 572b, 572c, 572d, 572e generally facilitate the fabrication of the space converter substrate 518 into a multilayer ceramic structure, which is also shown in FIG. 5. Notches are not essential. As can be clearly seen, since no notches are formed in the four corners of the substrate 518 (which are basically described by the process of manufacturing the ceramic multilayer substrate), the mounting plate 540 (see Fig. 5) is Clearly, this corner configuration must be accommodated.

5B illustrates a space converter substrate 574 compared to the space converter substrate 518 illustrated above, which may similarly be used for the probe card assembly 500 of FIG. In this case, a plurality of (only four of them are shown) regions 570a, 570b, 570c, and 570d are defined, in which a plurality of contact pads 522a, 522b, 522c, and 522d are defined in a predetermined pattern. It can be arranged easily. In general, the spacing of the regions 570a, 570b, 570c, 570d corresponds to the spacing of the die sites of the semiconductor wafer so that multiple die sites can be probed simultaneously by one pass of the probe card. (This is particularly useful for probing multiple memory chips residing on semiconductor wafers.) Typically, contact pads 522a, 522b, 522c, 522d are provided with regions 570a, 570b, 570c, 570d) Patterning in each is the same, but this is not absolutely necessary.

As illustrated in the contents of concurrently-owned concurrent US patent application Ser. No. 08 / 526,426, the example of FIG. 5B illustrates the use of a semiconductor in a single space converter with multiple (for example, four as shown) adjacent die sites. It clearly illustrates that a probe element is provided for probing (pressing contact) on the wafer. This is advantageous for reducing the number of mountings (steps) needed to probe many die sites or all die sites on a wafer. For example, if there are one hundred die sites on the wafer and four sets of probe elements are on the spatial transducer, the wafer only needs to be placed 25 times relative to the spatial transducer (for purposes of this embodiment, Ignore the slight decrease in efficiency at the edges. Optimizing the arrangement of probe sites (e.g., 570a through 570d) and the orientation of each probe element (e.g., misaligning) to minimize the number of contacts (passes) required to probe the entire wafer is a matter of the invention. Belongs to the category. It is also within the scope of the present invention to arrange the probe element on the surface of the spatial transducer in such a way that the optional probe element is in contact with a different one of two adjacent die sites on the wafer. Where it is generally desirable for all of the probe elements to have the same overall length, a non-limiting way of attaching (mounting) the probe element directly to any point on the two-dimensional surface of the spatial transducer can be used to attach the probe element to a probe card (e.g. It is clear that it is superior to any technique for limiting the position of attachment to a ring arrangement as described in the following). It is also within the scope of the present invention to probe multiple non-adjacent die sites on a wafer in this manner. The present invention is particularly advantageous for probing unspecificized memory devices on wafers and is also useful for probing die sites having any aspect ratio.

The space converter substrate 574 is an example of a larger substrate than can be settled by a small tile-like substrate having spring contact portions or probe elements or the like arranged on the surface as described in more detail below.

Examples and descriptions of FIGS. 5C, 6A, 6B, 7, 7A, 8A, and 8B of concurrently owned US patent application Ser. No. 08 / 526,426 are not essential and are described herein. Omitted but included for reference.

Tiling of Tile and Spatial Transducer Substrates (Zhengzhou)

As described above, the spring contacts, which are probe elements (eg 524, 526), may be mounted directly to the face of the space transducer substrate (eg 506, 518, 574) of the probe card assembly (eg 500). . However, this method has certain inherent limitations. Space transducers typically include relatively expensive substrates thereon for fabricating spring (probe) elements. In the process of manufacturing a composite interconnect device on a surface, at best, difficulty in reworking (time consuming and expensive) of the space transducer components can lead to problems in yield (successful manufacturing). In addition, it is an expensive method to design different spatial transducers (ie, design of adhesive pads / terminals on the electronic component to be contacted / tested) for each and every test application. In particular, it would be desirable to have the ability to test the entire semiconductor wafer in one pass, which would require a proportionally large space converter with limited design and worsening yield problems.

According to one aspect of the invention, the probe element may be fabricated on a relatively inexpensive substrate, referred to herein as the term tile. These tiles are easily attached (mounted, connected) to the face of the space transducer and are electrically connected to the terminals of the space transducer by soldering or with a z-axis conductive adhesive. Many of these tiles may be attached and connected to one spatial transducer component to perform wafer level testing. The tile may be a single layer substrate or may be a multilayer substrate (see FIG. 4) that affects the degree of space transformation. The z-axis space between the tile (s) and the face of the space transducer can be easily controlled by the volume of solder, z-axis adhesive, and the like used to form the attachment (s) / connection (s).

Multiple tiles with spring contact elements fabricated on the surface can be fabricated from a single inexpensive substrate, such as a ceramic wafer, which is then diced onto the surface of the spatial transducer or a semiconductor wafer or other (described below). It consists of a number of separate and preferably identical tiles that can be mounted separately to the surface of the electronic component.

For level testing (including burn-in), in order to perform level probing (testing) of the entire semiconductor wafer in one pass, a number of such tiles from which spring (probe) elements are manufactured are Can be attached / connected to a large space transducer component.

It is within the scope of the present invention that a tile substrate (eg 600; described below) can be easily soldered to an existing substrate such as a C4 package (Sans semiconductor die). Such C4 packages are readily available.

An advantage of the technique of using tiles without fabricating spring contact elements directly on the surface of the space transducer is that the space transducer is easily reworked by simply swapping a given tile of one or more tiles attached / connected.

6 shows a substrate 602 formed of an insulating material, such as ceramic terminals (two of which are shown) 604 and 606 disposed (or shown) on top surface 602a (as shown), and an opposite bottom surface. One embodiment of a tile 600 with terminals (two of which are shown) 608 and 610 disposed at 602b is shown. The tile substrate 602 is similar to the interposer substrate 302 of FIG. 3 or the space converter substrate 402 of FIG. 4. Certain of the terminals 604, 606 are electrically connected to corresponding predetermined ones of the terminals 608, 610, respectively, in any suitable manner, such as conductive bias (not shown) extending through the substrate 602. . (Bias through through or internal wiring in the substrate is shown in FIG. 4, for example.)

A number of spring elements (two of which are shown) 612 and 614 are mounted to terminals 604 and 606, respectively, and include a composite interconnect element as described above or a single spring element as described above. It may be.

As used herein, the term spring contact carrier refers to a tile substrate (eg 602) having spring contacts (eg 612, 614) mounted on one surface.

In FIG. 6, the spring elements 612 and 614 are shown to have the same structure as the probe element 524 shown in FIG. This is for illustrative purposes only, and any spring element having any structure (shape) may be attached to the surface 602a of the tile substrate 602.

As described above, the tile substrate with the spring element attached is easily mounted and connected to the space transducer component (eg 506) of the probe card assembly (eg 500). As shown, solder bumps 616 and 618 are easily formed on terminals 608 and 610, respectively, such that tile 600 reflows the solder connection between the terminal of the tile component and the terminal of the spatial transducer component. Can be connected to a corresponding pad (terminal) of the space transducer component. Alternatively, a z conductive adhesive (not shown) may be used in place of the solder to effect electrical connection between the terminal of the tile component and the terminal of the spatial transducer component.

6A illustrates how a number of tiles 620 (see tile 600 in FIG. 6) may be mounted to the space converter component substrate 574 shown in space converter component 622 (FIG. 5B). do.

The upper (visible) face of the space transducer component has a plurality of zones 624a, 624b in which a plurality of contact pads (not shown, see 522a, 522b, 522c, 522d) are each arranged in a predetermined pattern (four of which are shown). , 624c, 624d (see 570a, 570b, 570c, 570d).

In FIG. 6A, solder bumps on the surface of the tile substrate opposite (for example) spring elements are omitted for clarity. When reflow heated to solder the tile substrate to the space transducer substrate, the tile 620 improves the automatic alignment of each tile 620 for each zone 624a, 624d of the space transducer 622. Will be. However, small solder shapes (such as C4 bumps) do not always have a surface tension of sufficient magnitude to perform this automatic alignment.

According to one aspect of the invention, at least on the top surface (as shown in the drawing) of the space converter substrate 622 to improve the automatic alignment of each tile 620 with respect to each zone 624a, 624d. One solderable shape 626 is provided and a corresponding at least one solderable shape 628 is provided on the bottom surface (as seen in the drawing) of the tile substrate 620. During reflow heating, the solder disposed thereon and wetting these two corresponding mating features 626, 628 will provide the spatial converter substrate with enhanced momentum for performing automatic alignment of the tile substrate. The solder may be applied to any one of the shapes that are joined prior to reflow heating.

6A illustrates an important feature of the present invention, namely one space of a probe card assembly for performing multiple head testing of multiple die sites on a semiconductor wafer in one pass (touch down) where multiple tiles include wafer scale testing. It can be mounted on the transducer part. Space converter substrates with multiple tiles attached readily function as multiple device test heads.

In this embodiment and in the tiled semiconductor wafer embodiments described below, it is within the scope of the present invention that the spring elements can extend beyond the perimeter of the tile substrate.

With reference to FIGS. 9A-9D, a discussion is described for maintaining proper alignment between multiple tiles and larger components.

The volume of each solder connection (including alignment shapes 626/628) must be carefully controlled to form a precise standoff (gap) between the back surface of the tile substrate and the front surface of the substrate. Any deviation in the solder volume may cause an unacceptable height (z-axis) deviation. When height non-uniformity is required, any appropriately precise means of controlling the solder volume may be used, including the use of systems of precisely formed solder preforms, systems for accurate transfer of solder paste mass, precise volume of solder balls, and the like. have.

Tiling of tiles and semiconductor wafers for test / burn-in

In some instances, it may not be desirable to fabricate spring elements directly on the surface of certain semiconductor devices. For example, fabricating a composite interconnect device of the present invention on a fully populated C4 die (semiconductor device) with active devices may damage the device, or to any shape of the device. It may interfere with accessibility.

In accordance with this aspect of the invention, the tiles may be mounted directly to a semiconductor device including a fully-stable C4 die with active elements before or after their singulation from the semiconductor wafer. In this manner, the spring contact element is easily mounted to the semiconductor device while avoiding manufacturing the spring contact element directly on the semiconductor device.

According to a feature of this aspect of the invention, a semiconductor device having a spring contact element mounted in the manner described above has a printed circuit board (PCB) having a terminal (pad) adapted to be coupled (by a pressure contact) with a tip of the spring contact element. It may be easily tested and / or burned-in using a simple test fixture, which may be as simple as.

In general, the advantages of the mounting tile for the semiconductor device, in particular before being unified from the semiconductor wafer, are similar to the advantages for the aforementioned tiling of the space converter substrate. That is, there is no need to inspect the entire wafer, rework is very easy, and any (ie, complex or single) spring elements may be easily mounted and connected to the semiconductor device.

This technique of mounting a tile in a semiconductor device is, in some instances, superior to the wire bonding substrate technology in which the spring element is made of a semiconductor device, as disclosed in the joint US patent application, filed Feb. 15, 1996.

7 illustrates a technique 700 for restoring the surface of the substrate 706 versus a silicon wafer having multiple die sites 704 (or may not be a silicon wafer).

Each tile substrate 702 has a number of free upright interconnect elements 710 extending from the top surface (two of which are shown). This interconnect element 710 may be a single interconnect element or a complex interconnect element and may or may not have a tip structure attached to the free end. The interconnect element 710 is preferably a spring element and a suitable probe element. Each tile substrate 702 may be mounted by solder connections 708 to corresponding terminals (not shown) on the top surface (shown) of the base substrate 706. Solder connection 708 may be a C4 solder connection.

In this manner, a large number of spring contact carriers (ie, tile substrate 702) are anchored to the base substrate 706. It is one of many advantages of this technique 700 that any problem in producing (successfully producing) interconnect elements affects only the smaller tile substrate 702 and does not affect the substrate 706.

Collective Transfer of Spring Elements to Tile Substrates

In the above description, a composite interconnect (elastic contact) structure is manufactured by bonding the ends of the wires to the terminals of the electronic component, forming the wires into wire stems having an elastic shape, and overcoating the wires with an elastic (high yield strength) material. Techniques for doing this have been described. In this way, the elastic contact structure can be manufactured directly on the terminal of an electronic component such as the tile of the present invention.

According to the present invention, a number of spring elements can be mounted without mounting the spring elements (elastic contact structures) on the electronic parts for mounting (for example by brazing) on the electronic parts (after the elastic contact structures have been manufactured). It is manufactured in advance.

According to one technique, a supply (for example a bucket) of a spring element can be manufactured and stored for later attachment (mounting) to a terminal of an electronic component, for example by brazing. See Figure 2g. According to another technique, a number of spring elements can be prefabricated on the sacrificial substrate and then gan-transfered to the terminals of the electronic component (eg tile). These two techniques are described in the parent application (see FIGS. 11A-11F and 12A-12E of the parent application).

8A and 8B illustrate a technique 800 for collectively transferring a number of prefabricated contact structures 802 to terminals of an electronic component 806 (such as the tile component 600 of FIG. 6). In this example, the tile part performs some space transformation, but this is not necessary.

As shown in FIG. 8A, for example, a number of spring elements 802 of the type shown in FIG. 1E are according to the description described herein or in accordance with the technology described in any of the above-described ongoing patent applications owned by the applicant. It is fabricated on a tip structure 808 formed in the sacrificial substrate 810.

In FIG. 8B, the spring element 802 is, for example, soldered 812 to the terminal 804 of the electronic component 806 after the sacrificial substrate 810 is readily removed (e.g., by selective wet etching). Is collectively mounted (collective transfer). Solder balls 814 are easily attached to the terminals on opposite surfaces of the tile substrate. The tile substrate of FIG. 8B can be compared to the tile of FIG. 6 in that it has both solder balls on one surface and spring elements on opposite surfaces.

In several of the above-owned applications of the applicant's own application, the advantages of having a textured textured tip for making a more reliable pressurized connection to the terminals of other electronic components have been described in more detail. 8B illustrates one of many ways in which a spring element may be provided with a tip (if necessary) on a tile substrate.

Flattening and tip mounting on spring elements

The advantage that the distal end (tip) of the spring element is in the same plane and how to easily achieve it has been described in detail in the various patents owned by the above applicants.

8C-8G illustrate an example technique for forming a tip structure on a sacrificial substrate and transferring a prefabricated tip structure to the tip of an interconnect element mounted to a tile substrate.

8C shows a technique 820 for fabricating a tip structure on a sacrificial substrate and then attaching it to the tip of an interconnect element extending from an electronic component (eg, a tile substrate), which is particularly described above. Useful for, but not limited to, composite interconnect devices. In this example, a silicon substrate (wafer) having a top surface (shown) is used as the sacrificial substrate. Titanium layer 824 is deposited on the top surface of silicon substrate 822 (eg, by sputtering) and has a thickness of about 250 mW (1 mW = 0.1 nm = 10 ^-10 m). Aluminum layer 826 is deposited (eg by sputtering) on titanium layer 824 and has a thickness of about 10,000 mm 3. Titanium layer 824 is optional and functions as an adhesive layer for aluminum layer 826. Copper filler 828 is deposited (eg, by sputtering) on top of aluminum layer 826 and has a thickness of about 5,000 mm 3. Masking material (eg photoresist) layer 830 is deposited over copper layer 828 and has a thickness of about 0.0508 mm (2 mil). Masking layer 830 is treated in any suitable manner to have a plurality of holes (832 shown) extending through photoresist layer 830 in underlying copper layer 828. For example, each hole 822 may be 0.1524 mm (6 mil) in diameter, and the hole 832 may be disposed at a pitch of 0.254 mm (10 mil). In this manner, the sacrificial substrate 822 is prepared to fabricate multiple multi-layer contact tips in the holes 832 as follows.

The layer 834 of nickel is deposited on the copper layer 828 by, for example, plating, and has a thickness of about 0.0254 to 0.0381 mm (0.0254 to 0.0381 mm (1.0 to 1.5 mil)). Alternatively, a thin layer of noble metal such as rhodium (not shown) may be laminated to the copper layer before laminating nickel. Next, a gold layer 836 is deposited on the nickel layer 834 by, for example, plating. The multilayer structure of nickel and aluminum (and, optionally, rhodium) will function as the tip structure 840 (shown in FIG. 8D) that is manufactured.

Next, as shown in FIG. 8D, photoresist 830 is stripped (using any suitable solvent), leaving a number of fabricated tip structures 840 seated over copper layer 828. Copper 828 is then subjected to a rapid etch process, thereby exposing aluminum layer 826. Aluminum is useful in subsequent steps because it is generally not wettable for solder and brass materials.

It is preferable to pattern the photoresist with additional holes from which the ersats tip structure 842 can be fabricated in the same processing step used to make the tip structure 840. These Ersart tip structures 842 serve to uniformize the plating steps described above in a known manner by reducing the rapid gradient (non-uniformity) from manifesting themselves to the surface to be plated. Such a structure 842 is known in the plating art as robbers.

Next, solder or braze paste (connecting material) 844 is laminated to the top surface (shown) of the tip structure 840. (It is not necessary to stack the paste on top of the Hertz tip structure 842.) This is done in any suitable manner, such as a stainless steel screen or stencil. A typical paste (connecting material) 844 will include, for example, a gold-tin alloy (in the flux matrix) of 0.0254 mm (1 mil) exhibiting.

Tip structure 840 is ready to be mounted (eg by brazing) to an end (tip) of a sao connection element, such as, for example, a composite interconnect element of the present invention. However, the interconnect element is first specifically prepared to receive the tip structure 840.

FIG. 8E shows a plurality of interconnect elements 854 (612, 614) in the anticipation of a prefabricated tip structure 840 mounted at the end of the interconnect element 854. FIG. A technique 850 is shown for preparing a tile substrate 852 with a structure. The interconnect elements (spring contacts) 854 are shown fully (not in cross section).

In this example, the interconnect element 854 is a multilayer composite interconnect element (see FIG. 2A) and is coated with a copper layer (not shown) and nickel cobalt having a Ni: Co ratio of preferably 90:10. Alloy) layer (not shown) and also a gold (wire) core coated with a copper layer (not shown). The nickel layer is laminated only to the majority (eg 80%) of the desired final thickness, and the remaining small portion (eg 20%) of the nickel thickness is deposited in subsequent steps described below.

In this example, the tile substrate 852 is provided with a plurality of pillar-like structures 856 extending from the top surface (shown) that serve as a polishing stop. It is not necessary to have many of these polishing stops, they may be easily manufactured with the same material as the substrate (eg ceramic) and may be removed after polishing (described later).

Thereafter, the tile substrate 854 is, for example, a thermally-meltable, solution soluble polymer that functions to support the interconnect element 852 extending from the top surface of the tile substrate 852. Cast into a suitable casting material 858, such as < RTI ID = 0.0 > The top surface (shown) of the overmolded substrate is then polished, for example, with a polishing wheel 860 pressed down (as shown) to the top surface of the cast material. The polishing stop 858 described above determines the final position of the polishing wheel as indicated by the dashed label P. In this way, the tips (top end shown) of the interconnection elements 854 are polished to be generally completely flush with one another.

As described above, the instrument (eg differential screw or automatic instrument) is such that the tip of the elastic contact structure extending from the mounted tile is flush with the semiconductor being tested and the tip of the spring (probe) element is generally in contact with the wafer. To ensure flattening at the same time, it is provided in the entire probe card assembly 500 facing the space transducer substrate. Certainly, starting with a tip flattened by polishing (or by other suitable means) contributes to achieving this important purpose. In particular, by ensuring that the tip of the probe element 854 is coplanar to begin with, it is non-flat (by flexibility) within the tip of the probe element 854 extending from the tile part. Constraints placed on interposer component 534 are relaxed (reduced) to accommodate the angle.

After polishing the tip of the interconnect (eg probe) element by polishing, the cast material 858 is removed with a suitable solvent. (Polishing stop 856 will be removed at this time.) Castings are known, as are solvents. It is within the scope of the present invention that a casting material, such as wax, which can be simply melted and removed, can be used to support the probe element 854 for polishing. In this manner, the spring element 854 of the tile 852 is prepared to receive the tip structure 840 described above.

A beneficial side effect of the polishing operation is that the material overcoating the gold wire stem (core) of the interconnect element 854, which is a composite interconnect element, will be removed from the tip to expose the gold core. Since it is desirable to braze the tip structure 840 to the tip of the composite interconnect element, it is desirable to braze the exposed gold material.

By first performing a further plating step, i.e., nickel plating, on the composite interconnect element 854 to provide the composite interconnect element with the remaining remaining small portion (e.g. 20%) of the desired overall nickel thickness. It is also desirable to prepare the tile substrate 852 to receive the tip structure 840. If desired, the above-described exposed gold tip (see previous paragraph) can be masked during this additional plating step.

The sacrificial substrate 822 with the tip structure 840 is adapted to be supported by the prepared tile substrate 852. As shown in FIG. 8F, tip structure 840 (only two tip structures are shown in FIG. 8F for clarity) is a standard flip-chip technique, for example split prism. ) Is aligned with the tip of the free upright interconnect element 854, the assembly is passed through a brazing furnace to reflow the connecting material 844, whereby it advances to the end of the contact structure 854. The manufactured tip structure 840 is connected (eg brazed).

It is within the scope of the present invention that such techniques can be used to connect (eg, braze) prefabricated tip structures to the ends of non-elastic contact structures, elastic contact structures, composite interconnect elements, single interconnect elements, and the like. have.

In the final step, the sacrificial substrate 822 is removed in any suitable manner, with the tile substrate having a plurality of free upright interconnect elements 854 each having a prefabricated tip structure 840 as shown in FIG. 8G. (852). (The connecting material 844 is reflowed into the fillet on the end portion of the interconnect element 854.)

The brazing paste 844 is omitted, and instead, the layer of eutectic material (eg, gold-tin) is plated on the elastic contact structure prior to mounting the contact tip 840. Is in the range of.

Alignment of tiles on a substrate

As described above, a process such as wafer level burn-in (WLBI) to be performed by facilitating the formation of pressure connections in other electronic components with relatively large surface areas, such as entire semiconductor wafers. To enable this, a relatively large substrate (eg 622), such as a space transducer substrate of a probe card assembly, may be provided with a number of relatively small tiles with spring contacts on a surface (eg 620).

In many tile mounting processes, each with a large number of free upstanding spring elements on a substrate, proper alignment must be maintained.

1) in the z axis, maintain a certain height (usually the same plane) relative to the tip (end, free end) of the spring element; And

2) In the x and y axes, maintain some space between the tips of the spring elements.

In general, a method of manufacturing a plurality of free upright spring elements on a tile substrate is known in that the height (z-axis) and spacing (x and y-axis) of the plurality of spring elements on an individual tile is greater than before mounting the tile to the substrate. It is important that it can be checked. Tiles with spring elements with the wrong height or spacing can be reworked or discarded.

As described above with respect to Figure 6A, a number of tiles (e.g. 620) can be mounted to the base substrate (e.g. 622) by reflowing the solder. Large, deeply located solder shapes (eg, lithography) (eg 628, 626) generally control the x-y alignment of the tiles with respect to the substrate. And by carefully controlling the amount of solder used, it is possible to implement alternative control over the space between the back of the tile (eg 602b) and the front face of the counter substrate (eg 622). As mentioned above, it is assumed for this reason that the tip of the free standing spring element is crucial for the rear face of the tile substrate.

9A illustrates another technique 900 for holding a plurality of tile substrates 902 (see 620), suitably aligned with a large substrate 904. In this case, a number of recesses (three of which are shown) are sized to accommodate the individual tiles 902 on the front (top shown) side of the substrate 904 to hold them in a predetermined xy alignment with each other. (Well) is provided. As in Figure 6A, careful control of the volume of the solder can ensure a repeatable z axis (vertical in the figure) between the rear face of the tile and the front face of the substrate 904. This technique is generally not preferred because it increases the level of complexity for the substrate 904.

FIG. 9B illustrates another technique 920 for holding a large number of tile substrates 922 (three of which are shown) in proper alignment with the large substrate 924 (see 904). In this case, the front (upper shown) face is provided with a plurality of free upright spring contact portions 926, each of which is prefabricated in a predominant manner (e.g., material, spring shape) which is primarily operated in an elastic mode rather than a firing mode. The back (lower shown) face of the tile 922 is each provided with a plurality of contact elements 928 (two of which are shown) fabricated in a manner that generally operates in a predetermined deformation mode. (These contact elements 928 are referred to as compliant connections.) The tile 922 is soldered to the substrate 924 in any suitable manner, and the surface tension will keep the tiles x-y aligned with each other. In order to establish the coplanarity of the tip (top end shown) of many spring elements 926, the pressure plate 930 is downwardly directed against the tip of the spring element until it is in contact with all spring elements 926. Is pressurized. Plastic deformation of the spring element 928 may allow individual tiles to move downward in the z axis. After ensuring that the tips of all spring elements 926 are in the same plane, the pressure plate 930 is removed and the tile 922 can be fixed by a potting compound (not shown), for example epoxy. have. The potting compound should at least underfill the space between the tile and the substrate, and may also cover the tile (so that the bottom of the free standing spring contact 926 is covered). This technique is generally not preferred because reworking (removing and replacing) one of many tile substrates 922 is not conductive.

For example, as shown in Figures 9A-9B, the tile substrates 902, 922 achieve some spatial conversion (e.g., in Figure 9A) and the solder balls are free standing spring contacts (see Figure 8A). Spaced apart from the base). In these and other embodiments of the invention it is within the scope of the invention for the spring contact portion to be equal to or greater than the solder ball (pitch).

9C shows another technique 940 for keeping a number (three of which are shown) tile substrates 942 (922) properly z-axis aligned with each other. For clarity of illustration, the base substrates (eg 904, 924) and the connections (eg solder balls) on the rear (shown bottom) face of the tile substrate have been omitted from the figures.

In this example, the side edges of the tile substrate 942 are provided with interlocking tongue and groove shapes, such as the convex shape 944 that engages with the concave shape 946. For example, adjacent side edges of a right angle or rectangular tile substrate will have a concave shape, and the remaining two adjacent side edges will have a convex shape. This technique is generally not preferred because rework is problematic in relation to the level of complexity of the tile substrate.

In all the techniques described above, the goal of maintaining the alignment of the tips of the spring contacts on the tiles is slightly indirect, ie the alignment of the rear sides and / or edges of the tile substrate facing the front surface of the substrate against which the multiple tile substrates are mounted. By controlling it, it is addressed.

A more direct method is to ensure that the tip of the spring element is properly aligned regardless of the alignment of the rear face of the tile substrate, and that the rear face of the tile substrate is just aligned to ensure proper connectivity with the counter substrate.

9D shows that a number (three of which are shown) tiles 962 (see 600) are aligned with each other by the front (top shown) face, not by the rear face. Each tile 962 has a number of spring contacts 964 (two of which are shown) extending from the top surface, and solder balls (or pads 966) are provided on the rear surface. The tile substrate 962 can be carefully inspected prior to mounting the spring contact 964, the spring contact 964 being fabricated on the surface of the tile substrate (or on a special substrate and into the tile substrate) in a highly controlled manner. It can be assumed that the spring loaded tiles can be easily inspected to ensure that only good tiles are assembled to the substrate 968 (see 622). In general, fabrication of a plurality of spring contacts on the surface of the substrate 962 is relatively simple and reliable (repeatable), and each spring contact 964 is a technique described above (eg, FIG. 2A) extends to a predetermined height above the surface of the substrate 962 with the ends of the spring contacts well aligned (spaced apart). Such techniques are usually undesirable.

Stiffener substrate 970 is provided and has a number of holes 972 therethrough. A very high degree of precision for the hole locations is achieved by lithographic molding of those locations. Stiffener 970 may be a relatively rigid insulating material or a metal substrate covered with insulating material.

In this case, the tile substrate 962 is mounted to the back (bottom, as shown) surface by the front (top, as shown) surface, and each spring contact 964 is within the stiffener substrate 970. It extends through the corresponding hole in the hole 972. It may be manufactured with a suitable (not shown) adhesive, and a visualization system may be used to ensure that the tips of the spring contact portions are inter-aligned between tiles during the process of mounting the tiles to the stiffener substrate. In other words, this can be easily accomplished with great precision.

After all tile substrates 962 have been aligned (in xy) with the stiffener substrates and attached to the substrates, the tile / stiffener assemblies are then solder ball 966 and corresponding pads on the front (top shown) surface of the substrate 968. The substrate 968 can be mounted in any suitable manner, such as 976.

It is within the scope of the present invention that the tile 962 may be attached to the stiffener substrate 970 in a temporary manner, such that the stiffener substrate 970 may be removed if the assembly of the tile 962 is mounted to the base substrate 968. It belongs.

For rework (removal of individual tiles from the substrate to the substrate), in the case of permanently mounted stiffener substrates, the entire assembly of stiffeners / tiles can be removed from the substrate (such as solder removal) and the individual tile (s) ) Can be replaced and the assembly can be remounted on the substrate. For temporary stiffener substrates that are not part of the final assembly (of the tiles of the substrate), the individual tile (s) may be removed and the replacement tile (s) may be less than or equal to the stiffener substrate 970 (only a few adjacent It can be installed using a rework stiffener substrate (not shown) of size) that covers the tile.

For example, as shown in Figures 9A-9D, the free standing spring is C-shaped (relative to Figure 1E). It is within the scope of the present invention that the free standing spring element may be of any shape and may be a composite connecting element or a single connecting element.

Membrane tile

Multiple tiles with contacts other than (single or composite) spring contacts extending from the surface thereof may be assembled on a substrate for the purpose of performing wafer-level burn-in or the like such that the above-described effects occur equally. It is within the scope of the present invention.

For example, consider a typical membrane probe as disclosed in the aforementioned US Pat. Nos. 5,180,977 (Huff) and 5,422,574 (Kister). As disclosed in Huff's patent, a membrane probe may consist of a thin dielectric film, such as a row of microcontacts, commonly referred to as contact bumps, on a membrane. For each contact bump, a fine strip transfer line is formed on the membrane for electrical connection to the performance substrate (probe card). The contact bumps may be formed by a metal plating method to generate a large number of contact parts with a high probe density. As disclosed in Kister, membrane probes typically have a row of fine contacts on the protrusion of a thin flexible electrical film membrane. The membrane may have a central contact bump area and a plurality of signal connections separated by a triangular relief therein. The system of triangular relief in the membrane allows the membrane to shrink so that the center contact bump area can rise above the general plane of the probe card.

10A and 10B show an alternative embodiment 1000 of the present invention. As shown, the tile substrate 1002 may be formed like a frame having a central opening 1004, rather than a ring (eg, a square ring) or a solid substrate (eg, reference numerals 902, 922, 942, 962). Optionally, the central opening 1004 may be simply a grooved central region in the solid substrate shown by the tile substrate 1002 shown in FIG. 10C.

Thin dielectric film 1006 is mounted across the top surface (in the direction shown in the figure) of tile frame 1002 and functions as a membrane. Optionally, a thin dielectric film 1006 may be sandwiched between two halves of the upper half 1008a and the lower half 1008b of the tile frame 1002b as shown in FIG. 10D.

A number of (four of many shown) contact bumps 1010 are formed on the top surface (in the direction shown) of the membrane 1006. In the case as shown in FIG. It is necessary to ensure that bump 1010 extends beyond the plane of top ring 1008a in a suitable manner.

Signal lines 1012 (e.g., fine strip transfer lines) are formed on the membrane, and in any suitable way, tile frames or for electrical connection to a substrate (not shown) such as a performance substrate (probe card) Connected through the substrate. One embodiment is shown in FIG. 10E, wherein the tile frame 1002c with the upper tile frame halves 1018a (as opposed to 1008a) includes conductive vias 1020, 1020a, 1020b (vias) and solder bumps (or pads); Line 1022 terminating 1024. As shown in Fig. 10E, the bottom features of the final assembly (in this embodiment, the top tile frame half 1018a, bottom tile frame half 1018b, membrane 1006) are not shown in any of the ways described above (not shown). Solder balls 1024 used to connect individual tiles to the substrate.

10E is stylized and the bump contacts are characterized as topmost (in the direction shown) and any suitable means of enabling connection between the probe card and these contact bumps may be used (all of FIGS. 10C-10E). It will be appreciated by those skilled in the art that elastomers may be used behind the membrane 1006).

Wafer-Level Burn-In (WLBI)

As mentioned above, the advantage of large tile substrates with multiple spring contact carriers is that the entire semiconductor wafer can be contacted at once (for test and burn-in) (with a single pressure connection between the probe card assembly and the semiconductor wafer). Sufficient number of probe elements may be provided on the probe card assembly so as to be sufficient. As used herein, the term wafer-level burn-in includes any electrical function performed on the entire semiconductor wafer in the above manner.

11A illustrates an embodiment 1100 of a technique for achieving wafer-level burn-in. Although not limited to this (as shown) a number of (6 of many shown) with probe elements 1106 including free upright spring contacts or contact bumps 1000 of membrane tiles, and the like. Tile 1102 is mounted to base substrate 1104, which may be a space transformer of the probe card assembly (as compared to FIG. 5). A number of (6 of many shown) semiconductor die 1108 are located on the semiconductor wafer 1110. In this embodiment, each tile 1102 is coupled (aligned) with a predetermined semiconductor die 1108 and thus the probe elements 1106 are arranged in a pattern corresponding to the bonding pad of interest on the semiconductor die.

11B shows another embodiment 1120 of a technique for achieving wafer-level burn-in. Probe element 1126 (also including, but not limited to, free upright spring contacts or contact bumps of membrane tiles, etc.) may include many (three of many shown) tiles 1122a, 1122b, 1122c. It is mounted on a substrate 1124 (which may again be a space transducer or a probe card assembly). A number of (six of the many shown) semiconductor dies 1128a-1128f are located on the semiconductor wafer 1130. In this embodiment, each tile 1122a-1122c is coupled (aligned) with two adjacent semiconductor dies 1128a-1128f. Tile 1122a has two sets of probe elements 1126, each set disposed in a pattern corresponding to the bond pad of interest in one of the two corresponding semiconductor dies 1128a, 1128b. Tile 1122b has two sets of probe elements 1126, each set disposed in a pattern corresponding to the bond pad of interest in one of the two corresponding semiconductor dies 1128c, 1128d. Tile 1122c has two sets of probe elements 1126, each set disposed in a pattern corresponding to the bond pad of interest in one of the two corresponding semiconductor dies 1128e, 1128f.

11C shows another embodiment 1140 of the technique for achieving wafer-level burn-in. Probe element 1106 (also including but not limited to free upright spring contacts or contact bumps of membrane tiles, etc.) may include a number of (1 of 6 shown) tiles 1142a-1142f (again) , Mounted on a substrate to substrate 1144 (which may be a space transducer or a probe card assembly). A number of (five of many shown) semiconductor dies 1148a-1148e are located on the semiconductor wafer 1150. In this figure, the edges of the semiconductor wafer 1150 are shown and the entire semiconductor die is fabricated to the right of the semiconductor die 1148a (in the direction shown) as well as to the right of the semiconductor die 1148e (in the direction shown). Indicates that it cannot be.

In this embodiment 1140, the probe element on each tile only has a portion of the bond pad on one semiconductor die and a portion of the bond pad on another adjacent die even if there is (typically) a tile for each semiconductor die. It is arranged that it is arranged to be in contact. For example, the probe elements of tile 1142b are in contact with the left side (in the direction shown) of the semiconductor die 1148a and the right side (in the direction shown) of the semiconductor die 1148b.

Tile 1142a extends above the unusable die point at the edge of the semiconductor wafer and only needs to be in contact with the left portion (in the direction shown) of semiconductor die 1148a. Thus, tiles 1142a need not have a complete set of probe elements, but are different from most of the tiles 1142b-1142e. Similar results are derived from tile 1142f. However, it is within the scope of the present invention that tiles 1142a and 1142f are identical to tiles 1142b-1142e.

In the above example (embodiment) relating to a technique for achieving wafer-level burn-in, it is natural that all semiconductor dies on a semiconductor wafer are identical in terms of mutual design and placement. Thus, the tiles are generally identical to one another (except for the circumferential tiles 1142a and 1142f). However, it is within the scope of the present invention that multiple, non-identical tiles with dissimilar arrangements of probe elements can be mounted to a substrate for wafer-level burn-in and other applications requiring multiple pressure contact connections.

Consideration of thermal expansion coefficient

As mentioned above, a probe card element, such as spatial transducer element 622, may be disposed with a plurality of tiles 600 on its surface, each tile having a plurality of spring contacts that can be easily deformed at the tile level. Support sub-elements 612, 614 and also flip-chips connected to the surface of the substrate (e.g., probe card elements) to facilitate, for example, wafer-level burn-in.

In this effort, it is often necessary to take into account the thermal expansion coefficients of the various devices involved, including the probed elements (eg, matching the thermal expansion coefficient of the probe card with that of the semiconductor wafer). In general, as is known, the coefficients of thermal expansion of various materials match (sufficiently) the coefficients of thermal expansion of silicon, including Gri-Invar-copper laminates, aluminum nitride ceramics (insulating materials), and glass ceramics (insulating materials). do. The thermal expansion coefficient of molybdenum is similar to that of ceramics.

12A is a method of varying the coefficient of thermal expansion of a probe card assembly as described above to sufficiently match the coefficient of thermal expansion of a probed (not shown) semiconductor wafer, such as for wafer-level burn-in, as appropriate for the space transducer of the assembly. (504 of the probe card assembly of the present invention, for mounting a plurality of tiles (one of many shown) (120) Is a cross-sectional view of a technique 1200 for making the necessary connections to the substrate 1204 with other connection elements 1206, such as interposer elements.

A number of (6 of many shown) spring elements 1210 are mounted to the top surface (in the direction shown) of the tile substrate 1202, such as terminals disposed thereon in any suitable manner described above. In the present embodiment, the tile substrate 1202 does not perform any spatial transformation. The tile substrate 1202 is mounted on the top surface (in the direction of the drawing) of the base substrate 1204 having terminals on the bottom surface (in the direction of drawing) that are different (coarse) pitch from the terminals on the top surface of one pitch (space). Flip-chip. The base substrate 1204 is suitably a multi-layered wiring substrate, such as the aforementioned space transducer element of the probe card assembly described above.

Passive substrate 1220 is mounted to the bottom surface (in the direction of the drawing) of the base substrate 1204 with a suitable adhesive and is aligned with the terminals on the bottom surface (in the direction of the drawing) of the large (space conversion) substrate 604. With an opening 1226 (two of many shown). The purpose of the passive substrate 1220 is to control (modify) the coefficient of thermal expansion of the tile 1202 assembly and the space transducer 1204, preferably by the tip of the spring element 1210 (upper end as shown). This corresponds to the thermal expansion coefficient of the device being probed.

In this embodiment, the passive substrate 1220 is a readily available electrically conductive copper / invar / copper laminate. In order to prevent shorting of the terminals on the bottom surface of the space converter substrate (in this case, also to prevent shorting of the spring element 1230 which will be described later), the substrate 1220 is made of parylene. Coated with a suitable insulating material 1224.

The connection of the (large) space converter substrate 1204 to the bottom terminal (in the illustrated direction) may have a support substrate having an opening through which the spring element 1230 can extend and be held by a suitable elastomeric compound 1234. It is performed as the tip of the spring element 1230 (shown in the upper end), which is a suitable composite connection element (shown) of the present invention maintained in a predetermined interspatial relationship by 1232.

12B is a cross-sectional view of an optional embodiment 1250 for mounting a plurality of (one of many shown) tiles 1202 to a base substrate 1204 having the following modifications in the manner described above.

In embodiment 1250, the top end (in the illustrated direction) of the connection element 1230 is not in direct contact with the terminal on the bottom surface (in the illustrated direction) of the base substrate 1204. On the other hand, holes (openings) 1226 in the substrate 1220 are filled with a connecting material 1252, such as a z-axis conductive adhesive or a conductive (eg, silver filled) epoxy. This relaxes the constraints on the shape and height of the connection element 1230 that do not need to extend through the hole 1226.

This allows the coefficient of thermal expansion of the tile assembly with the substrate to (almost) coincide with that of other electronic components contacted by spring contacts on the tile.

Although the invention has been shown and disclosed in the accompanying drawings and the description, it is intended to be illustrative and not restrictive in nature, ie only preferred embodiments have been disclosed and all modifications and variations that fall within the scope of the invention should be protected. Apparently, many other changes to the foregoing subject matter are readily applicable to those skilled in the art, and such changes are deemed to be within the scope of the present invention as described above. Some of these variations have already been disclosed.

For example, masking material (eg, photoresist) is applied to the substrate and patterned such as exposure to light passing through the mask and chemical removal of some of the masking material (eg, conventional photolithography). In any of the embodiments disclosed herein, the portion of the masking material is irradiated by irradiating a portion of the masking material (eg, a blanket hardened photoresist) that is intended to remove suitably aimed light (eg, from an excimer laser). Optional techniques may be used, such as removing the or removing the uncured masking material by irradiating the cured portion of the masking material directly (without using a mask) with suitably aimed light.

It is proposed that the composite connection element of the present invention is merely an embodiment of a suitable elastic contact arrangement that can be mounted directly to the terminal of the tile element of the probe card assembly. For example, a needle of elastic material (which has a relatively large yield strength), such as tungsten, can be soldered so that the needle can be soldered and optionally supported in a predetermined pattern and soldered onto the terminals of the tile. Or to be coated with a material such as gold is within the scope of the present invention.

For example, a tile substrate having a conductive bias penetrating from a terminal on one surface to a terminal on an opposing surface may include a spring element mounted on a terminal on one substrate and a semiconductor mounted directly on the terminal on the opposite surface (such as a C4 solder joint). It can be provided, and wrapped so that it can function as a semiconductor chip assembly.

It is within the scope of the present invention that the substrate has a translucent (or transparent) material to provide the ability to determine the offset of the tip of a spring contact portion on one surface of the tile substrate from a terminal on an opposite surface of the tile substrate. It also belongs. In addition, for this determination, it may be necessary to use a measuring system such as an x-ray or a visualization system with two cameras.

For example, a substrate in which a tile is present may be an electronic component such as a resistor or capacitor in (or buried) the substrate, a current limiting element (typically a resistive network), and an active switch element (eg, a predetermined terminal). To provide a signal).

For example, it may occur when a tile soldered to a substrate is pressed (wafer probing) against an electronic component (e.g., a semiconductor wafer) and the temperature is elevated to degrade the solder joint that bonds the tile to the substrate. To prevent reflow crushing, a standoff element (as opposed to 856) is placed on the rear (back side) side of the tile substrate (or, optionally, on the front (front side) of the substrate. ) On the side.

For example, the front end of a plurality of springs extending from a plurality of tiles mounted on a large substrate may be arranged on an alignment substrate (as opposed to 930 in FIG. 9B) by finely machining the recess at a predetermined position (interval, alignment position) of the front end. Can be aligned by squeezing the tip inwardly.

Claims (21)

A method of probing an electronic component while contacting the electronic component with a plurality of spring contact elements, Providing a relatively large substrate, wherein the substrate has a front surface, as large as the testable area of the electronic component to be probed; Mounting and connecting a plurality of at least two tile substrates, each having a plurality of spring contact elements extending from the surface thereof, to the front surface of the substrate; Pressing the substrate and the electronic component together so that a spring contact element contacts the electronic component Method comprising a. The method of claim 1 wherein the electronic component is a semiconductor wafer. 3. The method of claim 2, wherein the testable area is a plurality of die sides on the semiconductor wafer, and the spring contacts contact the plurality of die sides at once. The method of claim 1 wherein the testable area of the electronic component is at least half of the total surface area of the electronic component. The method of claim 1 wherein the electronic component is a printed circuit board. The method of claim 1, wherein the electronic component is a liquid crystal display panel. The method of claim 1 wherein the spring contact element is a probe element. The method of claim 1 wherein the spring contact element is a composite contact element. The method of claim 1 wherein the spring contact element is a contact bump disposed on the membrane. The method of claim 1 wherein a solder connection is made between the tile substrate and the substrate. The method of claim 1, wherein the relatively large substrate is a spatial transducer of a probe card assembly. The method of claim 1 wherein the electronic component is a semiconductor wafer and the spring contact elements of each tile substrate contact individual semiconductor dies on the semiconductor wafer in a one-to-one relationship. The method of claim 1, wherein the electronic component is a semiconductor wafer and the spring contact elements of each tile substrate contact at least two semiconductor dies on the semiconductor wafer. The method of claim 1, wherein the tile substrate is aligned with the counter substrate by a solder joint. The method of claim 1 wherein the counter substrate on which the tile substrate is mounted is mounted to the probe card. The method of claim 1, wherein the counter substrate on which the tile substrate is mounted is mounted to the probe card and connected to the probe card by an interposer. A probe card assembly having a probe card and a plurality of probe elements, A space converter substrate having a top surface, a bottom surface, a plurality of first terminals disposed on the top surface, a plurality of second terminals disposed on the bottom surface, At least two tile substrates each having an upper and a lower surface, Means for making an electrical connection between the tile substrate and the space converter substrate; Multiple probe elements disposed on the top surface of the tile substrate. Probe card assembly characterized by. 18. The probe card assembly of claim 17, wherein said probe element is a free upright space contact. 19. The probe card assembly of claim 18, wherein the probe card assembly is characterized by a tip configuration mounted at the ends of the plurality of free standing spring contacts. 19. The probe card assembly of claim 18, wherein the free standing spring contact portion is a composite contact element. A tile designed to be mounted and used on a large substrate as one of a plurality of tiles, A tile substrate having two opposing surfaces, A spring contact extending from one of said two surfaces, A solderable terminal on the other of the two opposing surfaces, And means inside said tile substrate for connecting solderable terminals to spring contacts.