KR19990021127A - Modeling Methods and Modeling Circuits for MOSFETs - Google Patents

Abstract

A modeling method and circuit for a field effect transistor is disclosed. A field effect transistor including a gate terminal, a source terminal and a drain terminal on a semiconductor substrate and used as a spice built-in function model, having a source and drain region and a gate electrode, and having a channel region formed on the substrate is modeled. A pair of PN-junction diodes having polarities in opposite directions are formed between the first terminal between the drain region and the drain terminal and the second terminal between the source region and the source terminal. A drain external resistor is formed between the first terminal and the drain terminal, a source external resistor is formed between the second terminal and the source terminal, and an external substrate resistance is formed between the semiconductor substrate and the channel region. The channel breakdown characteristic of the transistor is modeled using the breakdown characteristics of the first and second diodes, and the series resistance characteristic of the diode is modeled using an external substrate resistance formed between the semiconductor substrate and the channel region. The internal resistance of the transistor is modeled by the drain external resistance and the source external resistance, respectively. A model can be obtained for a field effect transistor that includes channel breakdown characteristics and forward series characteristics of the drain (source) / substrate (N-well) PN-junction diode.

Description

Modeling Methods and Modeling Circuits for MOSFETs

The present invention relates to a modeling method and a modeling circuit of a semiconductor device, and more particularly, to a modeling method and a modeling circuit for a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) for use at an input of an ESD circuit. .

In recent years, reliability issues related to electrostatic discharge (ESD), electric overstress (EOS), and latch-up have emerged as important technical challenges in product development, and have become an important indicator of quality control. There has been a rapid need for the design and development of output stage electrostatic protection circuits and related devices.

The electrostatic problem of MOS products can be largely divided into the tasks of improving the input voltage and the output voltage.

Electrostatic breakdown of output stage is mostly caused by junction breakdown of MOSFET by contact metal filamentation, and the improvement of electrostatic breakdown voltage of output stage improves MOSFET device and process design for output buffer. This can be achieved by improving the electrothermal properties of the device. In other words, when designing the device, the channel breakdown of the output buffer FET is designed so that the channel occurs evenly through the entire region, so as to prevent current concentration in the breakdown state of the FET, and at the same time, the junction metal in the drain. Such methods include increasing the contact-to-metal space sufficiently to increase the propagation delay of filamentation.

On the contrary, the breakdown caused by static electricity at the input stage is mainly caused by the overvoltage of the input buffer FET gate-oxide, and the voltage applied to the gate of the input buffer buffer FET breaks down the gate oxide. Limiting the voltage below about ± 25V for 1.2µm CMOS is the main function of input stage protection.

In particular, the input-level electrostatic protection circuit not only has a large number of related devices (RNWELL, RPOLY, main protection MOSFET (or diode), secondary protection MOSFET, etc.), but also because the overall characteristics of the device have a sensitive effect on the electrostatic breakdown voltage. It is essential to develop a circuit simulation for the optimization of the circuit design and the prediction of the electrostatic breakdown voltage and the development of a spice model of the related device to support the circuit.

The MOSFET is used in an ESD circuit, and when it is used to build a circuit, an isolated field effect transistor (Metal-Oxide-Semiconductor Field) mounted in a conventional circuit simulator (SPICE), a simulation program with integrated circuit emphasis (SPICE). Subroutines of Effect Transistors (MOSFETs) are used. Spice is a simulator for detailed simulation of transistors or integrated circuits (ICs) and evaluation before fabricating integrated circuits, which can be used to construct and verify the contents of integrated circuits. There are many effects in terms of back.

1 is a circuit diagram showing a transient analysis equivalent circuit of a MOSFET.

The equivalent circuit of FIG. 1 consists of a substrate, a drain, a gate, a source, and a capacitance, resistor, diode, and current source. When the elements included in FIG. 1 are normally interpreted, they are as follows. The resistors Rd and Rs are internal resistances for indicating the voltage drop at the drain and the source end, and the capacitance is the capacitance generated by the process deviation between the gate, the source, the drain, and the substrate, and the two current sources are the source at the drain. It is a component for indicating the amount of current or electrons moving between (and the substrate).

The MOSFET shown in FIG. 1 does not include the channel breakdown characteristic of the MOSFET in the model, as well as the series resistance of the PN-junction diode formed between the active diffusion region of the drain and source and the substrate (or well). Or not included. Therefore, these characteristics need to be modeled by separately inserting a PN-diode and a resistor, respectively. However, for convenience, the transient analysis equivalent circuit of the MOSFET is adopted as the basic circuit block.

Accordingly, a first object of the present invention is to provide a method for modeling a MOSFET including channel breakdown characteristics and forward series characteristics of a drain (source) / substrate (N-well) PN-junction diode.

It is a second object of the present invention to provide a modeling circuit generated by the modeling method.

1 is a circuit diagram showing a transient analysis equivalent circuit of a MOSFET.

2A to 2B show a transient analysis equivalent circuit of mosfet according to the present invention.

Explanation of symbols for main parts of the drawings

MOSFET: Field Effect Transistor

GATE: Gate DRAIN: Drain

SOURCE: Source SUBSTRATE: Substrate

Rd, Rs, RDEX, RSEX, RBEX: Resistor

Cgb, Cgs, Csb Cgd, Cdb: Capacitance

Dsb, Ddb, DDS1, DDS2: Diode

N11, N12, N13, N14, N21, N22, N23, N24: connection terminal

In order to achieve the first object of the present invention described above, the present invention is used as a spice built-in function model including a gate terminal, a source terminal and a drain terminal on a semiconductor substrate and formed on the semiconductor substrate, and the source and drain regions. And modeling a field effect transistor having a gate electrode and having a channel region formed on the semiconductor substrate. A pair of PN-junction first and second diodes connected between a first terminal between the drain region and the drain terminal and a second terminal between the source region and the source terminal and having opposite polarities to each other; Doing; Forming a drain external resistor formed between the first terminal and the drain terminal, a source external resistor formed between the second terminal and the source terminal, and an external substrate resistor formed between the semiconductor substrate and the channel region. step; Modeling channel breakdown characteristics of the field effect transistor using breakdown characteristics of the first and second diodes; Modeling the series resistance characteristics of the first and second diodes formed between the first terminal and the second terminal using an external substrate resistance formed between the semiconductor substrate and the channel region; And modeling the internal resistance of the field effect transistor as the drain external resistance and the source external resistance, respectively.

In order to achieve the above-mentioned second object of the present invention, the present invention is used as a spice built-in function model including a gate terminal, a source terminal, and a drain terminal and formed on a semiconductor substrate. A field effect transistor having a channel region formed on the semiconductor substrate; A pair of PN-junctions connected between a first terminal between the drain region and the drain terminal and a second terminal between the source region and the source terminal and back-to-back connected to a third terminal; Second diode; A drain external resistor formed between the first terminal and the drain terminal; A source external resistor formed between the second terminal and the source terminal; And an external substrate resistor formed between the semiconductor substrate and the channel region.

According to the present invention, the channel breakdown characteristics of the NMOS FET and the PMOS FET are modeled using the forward series resistance characteristics of the PN-junction diode between the drain (source) and the substrate (N-Well). Thus, it is possible to implement an ESD protection circuit at the input stage that can protect the circuit from overvoltage on the drain or source from the channel drop characteristic and forward series characteristic of the PN-junction diode included in the equivalent circuit.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

2 shows a transient analysis equivalent circuit of a MOSFET according to the present invention. 2 (a) is a transient analysis equivalent circuit for the NMOS FET, Figure 2 (b) is a transient analysis equivalent circuit for the PMOS FET. FIG. 2 shows a transient analysis equivalent circuit including channel drop characteristics of the NMOS FET and PMOS FET and forward series resistance characteristics of the PN-junction diode between the drain (source) / substrate (N-Well).

2A to 2, MN and MP are spice transient analysis equivalent circuits of the NMOS and PMOS FETs shown in FIG. 1, respectively, and Rd and Rs of FIG. As shown in FIG. 2, the channel breakdown characteristic of the MOSFET is modeled using the breakdown characteristics of the PN-junction diodes DDS1 and DDS2 connected back-to-back, and the drain (source) active region and the substrate (or N). The series resistance of a PN-junction diode formed between the wells is modeled using an external resistor RBEX. On the other hand, RD and RS are modeled by external resistors RDEX and RSEX, respectively. (I.e., RD = 0, RS = 0 when model input)

2A is a spice equivalent circuit of an NMOS FET according to the present invention, in which a PN-junction diode having channel breakdown characteristics is added to the equivalent circuit of the MOSFET shown in FIG.

Referring to FIG. 2A, the source and drain regions may be used as a spice built-in function model including a gate terminal gte, a source terminal src, and a drain terminal drn formed on a semiconductor substrate. A field effect transistor (NMOS FET) having a gate electrode and having a channel region N14 formed on the semiconductor substrate is modeled.

In the field effect transistor, the first terminal N11 between the drain region and the drain terminal drn and the second terminal N12 between the source region and the source terminal src are connected to each other in opposite directions. A pair of PN-junction first and second diodes DD1 and DD2 having a polarity of is formed, and a drain external resistor RDEX is formed between the first terminal N11 and the drain terminal drn. . A source external resistor RSEX is formed between the second terminal N12 and the source terminal src, and an external substrate resistor RBEX is formed between the semiconductor substrate and the channel region.

The channel breakdown characteristics of the field effect transistor are modeled using the breakdown characteristics of the first and second diodes DDS1 and DDS2, and are formed between the first terminal N11 and the second terminal N12. The series resistance characteristics of the second diodes DDS1 and DDS2 are modeled using an external substrate resistance RBEX formed between the semiconductor substrate and the channel region. The internal resistances RD and RS of the field effect transistor are modeled as the drain external resistance RDEX and the source external resistance RSEX, respectively.

FIG. 2B is a spice equivalent circuit of the PMOS FET according to the present invention, the operation principle of which is the same as that of the NMOS FET shown in FIG. 2A.

In order to evaluate the performance of the MOS FET before actually manufacturing the MOS FET according to the present invention, performing a simulation may be an essential task before performing the process. Therefore, the circuit of 2 can also be simulated by the Spice which is a conventional circuit design simulator.

Codes for spice simulation of the NMOS FET and PMOS FET shown in Figs. 2A to 2B are as follows.

* ---------------------------------------

.subckt NMOST drn grn gte src sub

* ---------------------------------------

.param RD_NMOS = 33.78 RS_NMOS = 33.78

+ L = LENGTH, W = WIDTH

+ AD = 'W * WD' AS = 'W * WS'

+ PD = '2 * (W + WD)' PS = '2 * (W + WS)'

MOSFET 1 gte2 4 NMOS L = L W = W AD = AD PD = PD AS = ASPS = PS

DDS1 1 3 NMOSD AREA = 'W * 1u'

DDS2 2 3 NMOSD AREA = W * 1u '

RDEX drn 1 R = 'RD_NMOS * (25u / W)'

RSEX src 2 R = 'RS_NMOS * (25u / W)'

RBEXsub4R = '149 * (20u * 20u) / AD'

.ends

* ---------------------------------------

.subckt PMOST drn gte src sub

* ---------------------------------------

.param RD_PMOS = 55.99 RS_NMOS = 55.99

+ L = LENGTH, W = WIDTH

+ AD = 'W * WD' AS = 'W * WS'

+ PD = '2 * (W + WD)' PS = '2 * (W + WS)'

MOSFET 1 gte2 4 NMOS L = L W = W AD = AD PD = PD AS = ASPS = PS

DDS1 3 1 NMOSD AREA = 'W * 1u'

DDS2 3 2 NMOSD AREA = W * 1u '

RDEX drn 1 R = 'RD_PMOS * (25u / W)'

RSEX src 2 R = 'RS_PMOS * (25u / W)'

RBEX sub 4 R = '37 * (20u * 20u) / AD '

.ends

*

In the code for spice simulation, 'subckt NMOS drn gte src sub' is an NMOS FET spice model including the breakdown characteristics of the channel and the junction between the drain, the source, the active region and the substrate, and 'RD_NMOS, RS_NMOS' The drain, source, and ohmic sheet resistances of the NMOS FETs (RS, RD of the LEVEL3 spice parameters are input, respectively). The MOSFET model is embedded in a MOSFET spice, and the DDS1 and DDS2 are spice diode equivalent models of MOSFET channel drop. 'RDEX and RSEX' are drain and source ohmic resistors. RD and RS of level 3 spice parameters do not contain geometric elements and must be scaled to the gate width (W). 'RBEX' is an equivalent model of the active diffusion of drain and source and the junction diode series resistance between the substrate.

The code will be described in more detail with reference to the symbols in the circuit diagrams shown in FIGS. 2A and 2B. The code is divided into NMOS FETs and code portions for PMOS FETs. The code portion for the NMOS FET is described in detail, for example, and includes a drain terminal drn, a gate terminal gte, a source terminal src, and a source and drain region and a gate electrode, and an upper portion of the semiconductor substrate. A field effect transistor (MOSFET) having a channel region (N14) formed therein, a first diode (DDS1), a first terminal (N12), and a third terminal (N13) connected between the first terminal (N11) and the third terminal (N13). ), The second diode DDS2 connected between the second diode, the drain external resistor RDEX connected between the drain terminal drn, and the drain region, the source external resistor RSEX connected between the source terminal src, and the second terminal N12, and the semiconductor. An external substrate resistor RBEX is formed between the substrate and the channel region N14.

The code portion for the NMOS FET is described in detail, for example, and includes a drain terminal drn, a gate terminal gte, a source terminal src, and a source and drain region and a gate electrode, and an upper portion of the semiconductor substrate. A field effect transistor (MOSFET) having a channel region N24 formed therein, a first diode DDS1, a first terminal N12, and a third terminal N23 connected between the first terminal N21 and the third terminal N23. The second diode DDS2 connected between the second diode DDS2, the drain external resistor RDEX connected between the drain terminal drn and the drain region, the source external resistor RSEX connected between the source terminal src and the second terminal N22, and the semiconductor An external substrate resistor RBEX is formed between the substrate and the channel region N24.

That is, the spice code may be said to be coded according to the grammar of the phenomena analysis equivalent circuit with the MOSFETs of FIGS. 2A and 2B according to the present invention.

Therefore, the MOSFET protection circuit of the input stage capable of protecting the circuit from the overvoltage applied to the drain or the source from the channel drop characteristic and the forward series characteristic of the PN-junction diode included in the equivalent circuit of Figs. 2A and 2B shown above. It is possible to implement using

As described above, according to the modeling for the MOSFET according to the present invention, a model of the MOSFET including the channel drop characteristics and the forward series characteristics of the PN-junction diode between the drain (source) and the substrate (N-well) in the conventional MOSFET By design, it is possible to implement an ESD protection circuit at the input stage using a MOSFET that protects the circuit from overvoltage across the drain or source.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (7)

It is used as a spice built-in function model which is formed on a semiconductor substrate and includes a gate terminal (gte), a source terminal (src) and a drain terminal (drn) on a semiconductor substrate, and has a source and drain region and a gate electrode. Modeling a field effect transistor (MOS FET) having a channel region N14 formed over the semiconductor substrate; A pair connected between a first terminal N11 between the drain region and the drain terminal drn and a second terminal N12 between the source region and the source terminal src and having polarities in opposite directions. Forming PN-junction first and second diodes (DDS1, DDS2) of the; A drain external resistor (RDEX) formed between the first terminal (N11) and the drain terminal (drn), a source external resistor (RSEX) formed between the second terminal (N12) and the source terminal (src); Forming an external substrate resistor (RBEX) formed between the semiconductor substrate and the channel region; Modeling channel breakdown characteristics of the field effect transistor using breakdown characteristics of the first and second diodes DDS1 and DDS2; The series resistance characteristic of the first and second diodes DDS1 and DDS2 formed between the first terminal N11 and the second terminal N12 is an external substrate resistance RBEX formed between the semiconductor substrate and the channel region. Modeling using; And And modeling internal resistances RD and RS of the field effect transistors as the drain external resistance RDEX and the source external resistance RSEX, respectively. The method of claim 1 wherein the field effect transistor is N-type. The n-pole terminal and the first terminal N11 of the first diode DDS1 are connected, and the n-pole terminal and the second terminal N12 of the second diode DDS2 are connected. Spice modeling of a field effect transistor (NMOS FET) for modeling the p-pole terminal of the first diode DDS1 and the p-pole terminal of the second diode DDS2 to be connected back-to-back to the third terminal N13. Way. The spice modeling method of claim 1, wherein the field effect transistor is P-type. The method of spice modeling of the field effect transistor according to claim 4 The n-pole terminal and the first terminal N21 of the first diode DDS1 are connected, the n-pole terminal and the second terminal N22 of the second diode DDS2 are connected, and the first diode DDS1 is connected. A method of spice modeling of a field effect transistor (PMOS FET) is modeled such that the p-pole terminal of) and the p-pole terminal of the second diode (DDS2) are connected back-to-back to the third terminal (N23). It is used as a spice built-in function model that is formed on a semiconductor substrate and includes a gate terminal gte, a source terminal src, and a drain terminal drn, and has a source and drain region and a gate electrode, and an upper portion of the semiconductor substrate. A field effect transistor having a channel region formed in the; It is connected between the first terminal N11 between the drain region and the drain terminal drn and the second terminal N12 between the source region and the source terminal src and is connected to the third terminal N13. A pair of PN-junction first and second diodes DDS1 and DDS2 connected two-back; A drain external resistor RDEX formed between the first terminal N11 and the drain terminal drn; A source external resistor (RSEX) formed between the second terminal (N12) and the source terminal (src); And A spice modeling circuit of a field effect transistor (MOS FET) composed of an external substrate resistor (RBEX) formed between the semiconductor substrate and the channel region (N14). 7. The field spice modeling circuit of claim 6, wherein the field effect transistor is N-type or P-type.