KR19990021108A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR19990021108A KR19990021108A KR1019970044613A KR19970044613A KR19990021108A KR 19990021108 A KR19990021108 A KR 19990021108A KR 1019970044613 A KR1019970044613 A KR 1019970044613A KR 19970044613 A KR19970044613 A KR 19970044613A KR 19990021108 A KR19990021108 A KR 19990021108A
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- South Korea
- Prior art keywords
- wafer
- amphoteric surfactant
- semiconductor device
- manufacturing
- hydrophobic
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 61
- 238000004140 cleaning Methods 0.000 claims abstract description 26
- 230000002209 hydrophobic effect Effects 0.000 claims abstract description 13
- 150000001768 cations Chemical class 0.000 claims abstract description 6
- 239000002280 amphoteric surfactant Substances 0.000 claims description 23
- 125000001165 hydrophobic group Chemical group 0.000 claims description 9
- 239000004094 surface-active agent Substances 0.000 claims description 6
- 239000002002 slurry Substances 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 239000008367 deionised water Substances 0.000 claims description 4
- 229910021641 deionized water Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- BDHFUVZGWQCTTF-UHFFFAOYSA-M sulfonate Chemical compound [O-]S(=O)=O BDHFUVZGWQCTTF-UHFFFAOYSA-M 0.000 claims description 3
- KWIUHFFTVRNATP-UHFFFAOYSA-N glycine betaine Chemical compound C[N+](C)(C)CC([O-])=O KWIUHFFTVRNATP-UHFFFAOYSA-N 0.000 claims description 2
- -1 sulfuric acid ester Chemical class 0.000 claims description 2
- IUCJMVBFZDHPDX-UHFFFAOYSA-N tretamine Chemical compound C1CN1C1=NC(N2CC2)=NC(N2CC2)=N1 IUCJMVBFZDHPDX-UHFFFAOYSA-N 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 1
- 238000005507 spraying Methods 0.000 claims 1
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims 1
- 239000002245 particle Substances 0.000 abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 25
- 239000000126 substance Substances 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000005498 polishing Methods 0.000 abstract description 5
- 239000012190 activator Substances 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 46
- 229920005591 polysilicon Polymers 0.000 description 14
- 238000007517 polishing process Methods 0.000 description 9
- 239000000693 micelle Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 125000003178 carboxy group Chemical group [H]OC(*)=O 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 125000001183 hydrocarbyl group Chemical group 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 화학적 기계적 연마공정으로 드러난 다결정실리콘으로 인해 소수성을 띠는 반도체기판의 전면을 친수기와 소수기를 동시에 가지며 친수기가 한 분자내에 음, 양이온을 함께 갖는 양상 계면활성제로 처리하여 반도체기판의 특성을 친수성으로 변화시켜 후속 브러시에 의한 세정 능력을 향상시킴으로써 반도체기판 상부의 입자를 완전히 제거하여 별도의 세정공정을 하지 않으므로 공정을 간단하게 하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein the front surface of a semiconductor substrate having hydrophobicity is simultaneously hydrophilic and hydrophobic due to polycrystalline silicon exposed by chemical mechanical polishing, and the hydrophilic group has negative and cations in one molecule. By treating with an activator, the characteristics of the semiconductor substrate are changed to hydrophilicity, and the cleaning ability by the subsequent brush is improved to completely remove the particles on the upper surface of the semiconductor substrate so that a separate cleaning process is not performed. It is a technology to improve reliability.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로써, 특히 평탄화 공정 후 드러난 다결정실리콘으로 인해 소수성을 띠는 웨이퍼 전면을 친수기 및 소수기를 가지며, 친수기가 한분자내에 음, 양이온을 함께 갖는 양성 계면활성제로 처리함으로써 웨이퍼의 특성을 친수성으로 변화시켜 브러시에 의한 세정능력을 향상시키고 그에 따른 반도체소자의 특성 및 신회성을 향상시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, in particular, a hydrophobic group having a hydrophilic group and a hydrophobic group on the entire surface of a wafer due to polycrystalline silicon exposed after the planarization process, and a hydrophilic group as an amphoteric surfactant having both negative and cations in one molecule. The present invention relates to a technique capable of improving the cleaning ability by a brush by changing the characteristics of a wafer to hydrophilicity by treatment and thereby improving the characteristics and the reproducibility of the semiconductor device.
일반적으로 반도체소자 제조시 평탄화 공정 방법으로 에치백 식각 공정을 이용하였으나, 소자가 고집적화됨에 따라 단차가 심하게 발생되고 그로 인하여 에치백 공정으로 완전한 평탄화 작업이 어렵게 된다. 그로 인해 평탄화 공정을 용이하게 실시하기 위해 화학적 기계적 연마공정 방법이 대두되었다.In general, an etchback etching process is used as a planarization method for manufacturing a semiconductor device, but as the device is highly integrated, a step difference is severely generated, which makes it difficult to fully planarize the etchback process. Therefore, a chemical mechanical polishing process method has emerged to facilitate the planarization process.
상기 화학적 기계적 연마공정 방법은 연마포인 패드를 회전시키고 실리카 콜로이드(colloidal) 용액인 pH 10~11의 슬러리를 공급하면서 웨이퍼 상부면이 상기 패드에 마찰이 되도록 하여 웨이퍼 상부면을 일정 두께 제거하는 것이다.The chemical mechanical polishing process is to rotate the pad, which is a polishing cloth, and supply a slurry of pH 10-11, which is a silica colloidal solution, so that the upper surface of the wafer is rubbed to the pad, thereby removing a predetermined thickness of the upper surface of the wafer.
그러나, 종래의 화학적 기계적 연마공정에서 산화막을 평탄화할 때, 산화막의 제타 포텐셜(zeta potential)은 음성이고, 브러시의 제타 포텐셜 역시 음성이기 때문에 상기 연마공정에서 발생한 입자는 상기 산화막과 브러시의 반발력을 이용해서 제거해 왔다.However, when the oxide film is planarized in the conventional chemical mechanical polishing process, the zeta potential of the oxide film is negative and the zeta potential of the brush is also negative, so that the particles generated in the polishing process use the repulsive force of the oxide film and the brush. Has been removed.
한편, 다결정실리콘의 평탄화 공정에서 셀지역에 드러나는 다결정실리콘으로 인해 웨이퍼 전면이 소수성 띠는데 상기 다결정실리콘의 제타 포텐셜은 양성이므로 브러시에 의한 세정공정을 실시하면 다결정실리콘상의 입자들이 브러시에 붙게되는 현상이 발생하게 된다.On the other hand, the entire surface of the wafer is hydrophobic due to the polysilicon exposed to the cell region during the planarization of the polysilicon. Since the zeta potential of the polysilicon is positive, the cleaning process by the brush causes the particles of the polysilicon to adhere to the brush. Will occur.
여기서, 상기 브러시에 부착된 입자들은 이후 브러시 세정되는 친수성 웨이퍼 전면에 입자의 수를 증가시키고, 이렇게 형성된 입자들은 반도체소자의 쇼트 또는 브리지(bridge)를 발생시켜 소자특성을 악화시킨다.Here, the particles attached to the brush increase the number of particles on the entire surface of the hydrophilic wafer which is subsequently brush-cleaned, and the particles thus formed deteriorate device characteristics by generating a short or bridge of the semiconductor device.
그리고, 대머신(damascene) 공정을 적용한 다결정실리콘 콘택 및 배선 평탄화 공정진행후 셀지역의 다결정실리콘에 의해 소수성을 띠게 되고, 웨이퍼 상의 입자들은 이후 브러시 세정공정에 의해 제거되지 않는다.After the polysilicon contact and wiring planarization process using the damascene process, the polysilicon in the cell region becomes hydrophobic, and the particles on the wafer are not subsequently removed by the brush cleaning process.
또한, 현재 연마패드 안정화 목적으로 사용되는 더미(dummy) 웨이퍼의 과도 연마시 웨이퍼 가장자리에 드러나는 실리콘이 갖는 수소성 때문에 브러시가 오염되고, 이로 인해 소자가 형성된 웨이퍼를 평탄화한 후 상기 웨이퍼를 오염시키게 되어 소자의 특성을 나쁘게 한다.In addition, the brush is contaminated due to the hydrogen property of silicon exposed to the edge of the wafer during excessive polishing of a dummy wafer currently used for polishing pad stabilization purposes, thereby contaminating the wafer after planarizing the wafer on which the device is formed. Deteriorates the device characteristics.
그리고, 상기 브러시 세정공정으로 제거되지 않는 입자를 제거하기 위해 브러시 세정공정 진행시 과수를 첨가하거나 이후 불산 세정공정이나 SC-2 세정공정을 추가하기 때문에 브러시의 사용주기를 단축시키는 결과를 낳게되어 소모재 비용을 증가시킨다.And, in order to remove the particles that are not removed by the brush cleaning process, fruit or water is added during the brush cleaning process or a hydrofluoric acid cleaning process or SC-2 cleaning process is added, resulting in a shortening of the use cycle of the brush. Increase the re-cost.
상기와 같이 종래기술에 따른 반도체소자의 평탄화방법은, 완전히 제거되지 않은 입자와 브러시에 부착된 입자들에 의해서 후속 세정공정시 소자가 형성되어 있는 웨이퍼를 오염시켜 반도체소자의 특성을 악화시키고, 상기 입자들을 제거하기 위한 별도의 세정공정을 추가해야하므로 공정을 복잡하게 하고 비용을 증가시키는 문제점이 있다.As described above, the planarization method of the semiconductor device according to the related art deteriorates the characteristics of the semiconductor device by contaminating the wafer on which the device is formed in a subsequent cleaning process by particles not completely removed and particles attached to the brush. Since a separate cleaning process for removing the particles must be added, there is a problem of complicated process and increased cost.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 다결정실리콘 평탄화 공정후 셀지역에 드러난 다결정실리콘으로 인해 소수성을 띠는 웨이퍼의 전표면을 친수기와 소수기를 동시에 가지며 친수기가 한 분자내에 음, 양이온을 함께 갖는 양성 계면활성제로 처리함으로써 웨이퍼의 표면을 친수성으로 변화시켜 브러시에 의한 세정능력을 향상시킴으로써 후속공정을 용이하게 하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 반도체소자의 평탄화방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the entire surface of a wafer having hydrophobicity due to the polycrystalline silicon exposed to the cell region after the polysilicon planarization process has both a hydrophilic group and a hydrophobic group at the same time, It is provided with a method of planarization of a semiconductor device that facilitates subsequent processes by changing the surface of the wafer to hydrophilicity and improves the cleaning ability by a brush by treating with an amphoteric surfactant having the same. The purpose is.
도 1a 내지 도 1b는 본 발명의 제 1실시예에 따른 반도체소자의 제조방법을 도시한 단면도.1A to 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
도 2a 내지 도 2d는 본 발명의 제 2실시예에 따른 반도체소자의 제조방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
11, 21 : 웨이퍼 13 : 층간 절연막11, 21 wafer 13: interlayer insulating film
15 : 콘트홀 17, 23 : 다결정실리콘15: control hole 17, 23: polycrystalline silicon
19, 25 ; 입자 20, 27 : 미셀19, 25; Particles 20 and 27: micelles
22 : 대머신 공정을 위한 다결정실리콘 콘택22: Polysilicon Contact for Large Machine Process
30, 40 : 세정공정에 의해 입자가 제거된 계면30, 40: interface with particles removed by cleaning process
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 평탄화방법은, 웨이퍼 상부에 금속 배선 및 평탄화막을 형성하는 공정과, 상기 평탄화막의 상부를 CMP 처리하여 평탄화함으로서 금속배선의 일부가 드러나게 하는 공정과, 상기 웨이퍼를 양성 계면활성제로 처리하는 공정과, 상기 웨이퍼를 브러시 세정하는 공정을 포함하는 것을 특징으로 한다.In order to achieve the above object, the semiconductor device planarization method includes the steps of forming a metal wiring and a planarization film on the wafer, and a process of exposing a part of the metal wiring by CMP-processing the upper part of the planarization film; And a step of treating the wafer with an amphoteric surfactant and a step of brush cleaning the wafer.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는, 화학적 기계적 연마공정으로 다결정실리콘 평탄화 공정을 할 경우 많은 양의 입자가 발생하는데 상기 입자를 제거하기 위해 후속 공정으로 브러시 세정공정을 실시한다. 그래서, 상기 평탄화 공정으로 웨이퍼 표면에 드러난 다결정실리콘의 소수성 때문에 변화된 웨이퍼의 표면을 소수기 및 친수기를 가지며 친수기가 한 분자내에 음, 양이온을 함께 갖는 양성 계면활성제를 사용하여 처리함으로써 웨이퍼의 표면을 친수성으로 변화시켜 후속 세정공정에서 상기 입자들에 의해 소자들이 형성된 웨이퍼를 오염시키는 것을 방지하는 것이다.On the other hand, the principle of the present invention for achieving the above object, a large amount of particles are generated when the polysilicon planarization process by a chemical mechanical polishing process, the brush cleaning process is carried out in a subsequent process to remove the particles. Thus, the surface of the wafer is made hydrophilic by treating the surface of the changed wafer due to the hydrophobicity of the polycrystalline silicon exposed to the surface of the wafer by the planarization process using an amphoteric surfactant having a hydrophobic group and a hydrophilic group and a hydrophilic group together with negative and positive ions in one molecule. To prevent contamination of the wafer on which the devices are formed by the particles in a subsequent cleaning process.
이하에 첨부된 도면을 참조하여 본 발명을 상세하게 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명에 따른 제 1실시예에 따른 반도체 소자의 평탄화 방법을 나타낸 단면도로서, 다결정실리콘 평탄화 공정 후 셀 부분에 드러난 다결정실리콘으로 인해 소수성을 띠는 웨이퍼의 전면을 양성 계면 활성제로 처리하고, 브러시 세정하는 것을 나타낸다.1A to 1D are cross-sectional views illustrating a planarization method of a semiconductor device in accordance with a first embodiment of the present invention, wherein the front surface of a wafer having hydrophobicity due to polysilicon exposed to a cell portion after polysilicon planarization is formed on a positive surface active agent It is processed by and brush-washing.
도 1a에 도시된 바와 같이, 반도체 기판 상에 다결정실리콘 콘택 및 배선을 위한 다결정실리콘을 형성한다.As shown in FIG. 1A, polycrystalline silicon for polycrystalline silicon contact and wiring is formed on a semiconductor substrate.
먼저, 층간절연막(13) 및 콘택홀(15)을 구비하는 웨이퍼(11) 표면에 다결정실리콘(17)을 증착한다 (도 1a).First, polycrystalline silicon 17 is deposited on the surface of the wafer 11 including the interlayer insulating film 13 and the contact hole 15 (FIG. 1A).
다음, 상기 다결정실리콘(17)은 화학적 기계적 연마공정을 실시하여 평탄화시킨다.Next, the polysilicon 17 is planarized by performing a chemical mechanical polishing process.
그 다음, 상기 연마공정으로 인해 발생한 입자(19)를 제거하기 위해 세정공정을 실시한다. 이때, 상기 입자(19)는 완전히 제거되지 않고 잔류하게 된다 (도 1b).Then, a cleaning process is performed to remove the particles 19 generated by the polishing process. At this time, the particles 19 are not completely removed (Fig. 1b).
그 후, 상기 웨이퍼(11) 표면을 친수기와 소수기를 함께 가지면서 친수기로서 한개의 분자내에 음, 양의 양이온으로 하전된 양성 계면활성제로 처리한다. 여기서 소수기란 탄화수소기를 말하며, 친수기란 -OH, -COOH, -NO2, -NH2, -COONa, -OSO3Na를 말한다. 그리고, 상기 양성 계면활성제는 Am-1 Betain형, Am-3 Persistol KF형, Am-3 Tege형, 이외에 황산 에스테르형, 설포네이트(sulfonate) 형등을 사용하여 웨이퍼를 브러시 세정한다. 상기 세정공정은 양성 계면활성제에 연마소모제인 슬러리를 혼합하여 실시한다.Thereafter, the surface of the wafer 11 is treated with an amphoteric surfactant charged with negative and positive cations in one molecule as a hydrophilic group, with both hydrophilic and hydrophobic groups. Refers to a group wherein the hydrocarbon group refers to a small number, a hydrophilic group is -OH, -COOH, -NO 2, -NH 2, refers to a -COONa, -OSO 3 Na. In addition, the amphoteric surfactant is brush-cleaned using an Am-1 Betain type, an Am-3 Persistol KF type, an Am-3 Tege type, a sulfate ester type, a sulfonate type, or the like. The washing step is carried out by mixing a slurry of abrasive consumption with an amphoteric surfactant.
그 결과, 소수성을 갖는 웨이퍼 전면의 가장자리와 후면에서 소수기는 웨이퍼 계면으로 향하고 친수기는 웨이퍼 바깥쪽으로 배향하여 친수성 웨이퍼로 변화시키게 되고, 이와 같이 배향된 친수기 위에 입자를 중심으로 미셀을 형성함으로써 이후 브러시 세정능력을 향상시킨다.As a result, hydrophobic groups are directed toward the wafer interface and hydrophilic groups are oriented outwardly of the wafer to change into hydrophilic wafers at the edges and back sides of the hydrophobic wafer. Improve your skills
또한, 친수성을 띠는 웨이퍼(11) 중심부에서는 입자를 중심으로 미셀(20)이 형성됨으로써 브러시 세정을 원활하게 한다 (도 1c).In addition, at the center of the hydrophilic wafer 11, the micelle 20 is formed around the particles to smooth brush cleaning (FIG. 1C).
그 후, 상기 슬러리는 탈이온수와 양성 계면활성제를 혼합하여 소수성 웨이퍼의 전면을 처리함으로써 제거한다.The slurry is then removed by mixing the deionized water with the amphoteric surfactant to treat the entire surface of the hydrophobic wafer.
그리고, 연마된 상기 웨이퍼를 후세정장치로 이동대기할 때 양성 계면활성제를 분사하여 상기 소수성 웨이퍼의 후면을 처리하고, 후세정장치로 이동할 때 상기 양성 계면활성제를 분사하거나 상기 계면활성제가 있는 용기에 담궈서 상기 소수성 웨이퍼 전·후면을 처리한다. 그리고, 상기 계면활성제와 탈이온수를 혼합하여 상기 소수성 웨이퍼를 처리하는 방법도 있다.When the polished wafer is moved to the post-cleaning apparatus, the positive surfactant is sprayed to process the rear surface of the hydrophobic wafer, and when the wafer is moved to the post-cleaning apparatus, the positive surfactant is sprayed or the container containing the surfactant is sprayed. It is immersed to process the front and rear surfaces of the hydrophobic wafer. There is also a method of treating the hydrophobic wafer by mixing the surfactant and deionized water.
상기 양성 계면활성제를 사용하여 소수성 웨이퍼를 처리하는 시간은 10초 내지 10분 정도이다. 또한, 상기 양성 계면활성제를 사용하여 소수성 웨이퍼를 처리하는 온도는 10℃ 내지 100℃ 정도이다.The time for treating the hydrophobic wafer using the amphoteric surfactant is about 10 seconds to 10 minutes. In addition, the temperature which processes a hydrophobic wafer using the said amphoteric surfactant is about 10 degreeC-about 100 degreeC.
그 결과, 상기 웨이퍼(11) 표면의 입자는 완전히 제거된다 (도 1d).As a result, the particles on the surface of the wafer 11 are completely removed (FIG. 1D).
도 2a 내지 도 2d는 본 발명의 제 2실시예에 따른 반도체소자의 평탄화방법을 나타낸 단면도로서, 대머신 공정으로 형성된 다결정실리콘을 평탄화시키고, 양성 계면활성제를 이용하여 세정하는 것을 나타낸다.2A to 2D are cross-sectional views illustrating a planarization method of a semiconductor device according to a second exemplary embodiment of the present invention, in which a polysilicon formed by a damascene process is planarized and cleaned using an amphoteric surfactant.
먼저, 대머신 공정에 의해 형성된 다결정실리콘 콘택(6) 및 배선을 형성하기 위해 웨이퍼 표면에 다결정실리콘(23)을 증착한다 (도 2a).First, polycrystalline silicon 23 is deposited on the wafer surface to form the polycrystalline silicon contact 6 and wiring formed by the damascene process (FIG. 2A).
다음, 상기 다결정실리콘(23)은 화학적 기계적 연마공정을 실시하여 평탄화시킨다.Next, the polysilicon 23 is planarized by performing a chemical mechanical polishing process.
그 다음, 상기 연마공정으로 인해 발생한 입자를 입자를 제거하기 위해 세정공정을 실시한다. 이때, 상기 입자는 완전히 제거되지 않고 잔류하게 된다. (도 2b)Then, the cleaning process is performed to remove the particles generated by the polishing process. At this time, the particles remain without being completely removed. (FIG. 2B)
그 후, 상기 웨이퍼(21) 표면을 친수기와 소수기를 함께 가지면서 친수기로서 한개의 분자내에 음, 양의 양이온으로 하전된 양성 계면활성제로 처리한다.Thereafter, the surface of the wafer 21 is treated with an amphoteric surfactant charged with negative and positive cations in one molecule as a hydrophilic group, with both hydrophilic and hydrophobic groups.
그로 인해 소수성을 갖는 웨이퍼 전면의 가장자리와 후면에서 소수기는 웨이퍼 계면으로 향하고 친수기는 웨이퍼 바깥쪽으로 배향하여 친수성 웨이퍼로 변화시키게 되고, 이와 같이 배향된 친수기 위에 입자를 중심으로 미셀을 형성함으로써 이후 브러시 세정능력을 향상시킨다.As a result, hydrophobic groups are directed toward the wafer interface and hydrophilic groups are oriented outwardly to change the hydrophilic wafer from the edges and rear surfaces of the hydrophobic wafer. To improve.
또한, 친수성을 띠는 웨이퍼 중심부에서는 입자를 중심으로 미셀(27)이 형성됨으로써 브러시 세정을 원활하게 한다. (도 2c)In addition, at the center of the wafer having hydrophilicity, micelles 27 are formed around the particles to smooth brush cleaning. (FIG. 2C)
그 결과, 상기 웨이퍼 표면의 입자는 완전히 제거된다. (도 2d)As a result, the particles on the wafer surface are completely removed. (FIG. 2D)
상기한 바와 같이 본 발명에 따른 반도체 소자의 평탄화 방법은, 화학적 기계적 연마공정으로 드러난 다결정실리콘으로 인해 소수성을 띠는 반도체 기판의 전면을 친수기와 소수기를 함께 가지면서 친수기로서 한개의 분자내에 음, 양의 양이온으로 하전된 양성 계면활성제로 처리하여 반도체 기판의 특성을 친수성으로 변화시켜 후속 브러시에 의한 세정능력을 향상시킴으로써 반도체 기판 상부의 입자를 완전히 제거하여 별도의 세정공정을 하지 않으므로 공정을 간단하게 하고, 그에 따른 반도체 소자의 특성 및 신뢰성을 향상시킬 수 있다.As described above, the planarization method of a semiconductor device according to the present invention has a hydrophilic group with a hydrophilic group and a hydrophilic group in a single molecule as a hydrophilic group, with a hydrophilic group on the entire surface of a semiconductor substrate having hydrophobicity due to polycrystalline silicon revealed by chemical mechanical polishing. Treatment with an amphoteric surfactant charged with a cation of amines changes the properties of the semiconductor substrate to hydrophilicity and improves the cleaning ability with a subsequent brush, thus completely eliminating particles on top of the semiconductor substrate, thus simplifying the process. Therefore, the characteristics and reliability of the semiconductor device can be improved.
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