KR19990018366A - Manufacturing Method of Transistor for Semiconductor Memory Device - Google Patents
Manufacturing Method of Transistor for Semiconductor Memory Device Download PDFInfo
- Publication number
- KR19990018366A KR19990018366A KR1019970041542A KR19970041542A KR19990018366A KR 19990018366 A KR19990018366 A KR 19990018366A KR 1019970041542 A KR1019970041542 A KR 1019970041542A KR 19970041542 A KR19970041542 A KR 19970041542A KR 19990018366 A KR19990018366 A KR 19990018366A
- Authority
- KR
- South Korea
- Prior art keywords
- spacer insulating
- insulating film
- gate
- transistor
- memory device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 11
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims 4
- 239000000463 material Substances 0.000 claims 3
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 10
- 238000009792 diffusion process Methods 0.000 abstract 2
- 239000003990 capacitor Substances 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
반도체 장치의 제조 방법이 개시되어 있다. 반도체 장치에 있어 게이트와 확산 영역의 중첩으로 인해 불가피하게 생성되는 기생 캐패시턴스를 방지하기 위해서, 상기 게이트 측벽에 제1스페이서 절연막과 제2스페이서 절연막을 형성한 뒤, 상기 제1스페이서 절연막을 제거한다. 그 결과 상기 제2스페이서 절연막과 상기 게이트 영역 사이 즉, 상기 제1스페이서 절연막이 존재하던 공간에는 보다 유전율이 낮은 공기로 채워지거나 또는 진공상태가 된다. 이로써 게이트 측면과 확산 영역사이에 생성되는 기생 캐패시턴스를 감소시켜 반도체 장치의 속도를 증가시킬 수 있게 된다.A method for manufacturing a semiconductor device is disclosed. In order to prevent parasitic capacitance inevitably generated due to overlapping of the gate and the diffusion region in the semiconductor device, the first spacer insulating film and the second spacer insulating film are formed on the sidewall of the gate, and then the first spacer insulating film is removed. As a result, a space between the second spacer insulating film and the gate region, that is, the first spacer insulating film is filled with air having a lower dielectric constant or is in a vacuum state. This reduces the parasitic capacitance generated between the gate side and the diffusion region, thereby increasing the speed of the semiconductor device.
Description
본 발명은 반도체 메모리 장치용 트랜지스터의 제조 방법에 관한 것으로, 보다 상세하게는 트랜지스터의 게이트와 접합 영역간의 기생 캐패시턴스를 감소시키기 위한 반도체 메모리 장치용 트랜지스터의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor for a semiconductor memory device, and more particularly, to a method for manufacturing a transistor for a semiconductor memory device for reducing parasitic capacitance between a gate and a junction region of a transistor.
최근 반도체 메모리 장치에 있어, 제조 기술이 발달되고 응용분야가 확장됨에 따라 대용량의 메모리 장치의 개발이 활발히 진행되고 있다. 반도체 메모리 장치는 크게 휘발성과 비휘발성 메모리 장치로 분류되어진다. 휘발성 메모리 장치에 속하는 에스램(Static Random Access Memory ; 이하 SRAM 이라 칭함)이나 디램(Dynamic Random Access Memory ; 이하 DRAM 이라 칭함)등은 파워(power)의 오프(off)에 따라 데이터가 지워지는 특성이 있고, 롬(Read Only Memory ; 이하 ROM 이라 칭함), 이피롬(Erasable and Programmable ROM ; 이하 EPROM 이라 칭함), 이이피롬(Electrically Erasable and Programmable ROM ; 이하 EEPROM 이라 칭함)등은 일단 한번 입력된 데이터를 파워오프시에도 계속 유지하는 특성이 있다.Recently, in the semiconductor memory device, as the manufacturing technology is developed and the application field is expanded, the development of a large-capacity memory device is actively progressing. Semiconductor memory devices are classified into volatile and nonvolatile memory devices. Static random access memory (hereinafter referred to as SRAM) or DRAM (hereinafter referred to as DRAM) belonging to a volatile memory device has a characteristic in which data is erased when power is turned off. ROM (Read Only Memory; hereinafter referred to as ROM), Epyrom (Erasable and Programmable ROM; hereinafter referred to as EPROM), Epyrom (Electrically Erasable and Programmable ROM (hereinafter referred to as EEPROM)), etc. There is a characteristic that it continues to be maintained even at power off.
그 중에서도 특히 DRAM의 메모리 셀은 하나의 패스 트랜지스터와 하나의 캐패시터로 구성되는데, 상기 트랜지스터는 상기 캐패시터에 데이터를 입/출력시키는 스위치의 역할을 하고, 캐패시터는 데이터를 저장하는 창고와 같은 역할을 한다. 상기 트랜지스터의 구성중 게이트로서 사용되는 워드 라인(word line)의 선택신호를 통해 캐패시터에 데이터가 전달되거나 캐패시터에 저장된 데이터가 비트 라인으로 전달되므로 상기 워드 라인은 통해 인가되는 선택신호에 상기 트랜지스터가 응답되는 시간이 DRAM동작의 속도(speed)를 좌우하는 주요 요인이라 할 수 있다. 그런데 데이터가 트랜지스터로 전달되는 시간은 상기 게이트의 저항 용량 지연(Resistance Capacitance delay ; RC delay)에 의해 결정되어진다. 일반적인 저항 용량에는 게이트 자체의 저항에 의한 캐패시턴스나 게이트와 접합 영역이 중첩되는 부분에 존재하는 캐패시턴스등이 있다. 상기 게이트와 접합 영역이 중첩되는 부분에 존재하는 캐패시턴스는 크게 두가지로 나눌 수 있는데, 그 중 하나는 게이트 영역 하부와 접합 영역이 중첩되는 부분에 존재하는 캐패시턴스이고, 다른 하나는 게이트 측면과 접합 영역사이에 존재하는 캐패시턴스이다. 상기 기생 캐패시턴스들은 게이트의 저항 용량 지연을 증가시켜 반도체 장치의 속도를 감소시키는 바람직하지 못한 문제점을 초래한다.In particular, the memory cell of the DRAM is composed of one pass transistor and one capacitor, which acts as a switch for inputting / outputting data into the capacitor, and the capacitor serves as a warehouse for storing data. . Since the data is transferred to the capacitor through the selection signal of the word line used as a gate of the transistor, or the data stored in the capacitor is transferred to the bit line, the transistor responds to the selection signal applied through the word line. The time required is a major factor in determining the speed of DRAM operation. However, the time at which data is transferred to the transistor is determined by the resistance capacitance delay (RC delay) of the gate. Typical resistive capacitances include capacitance due to the resistance of the gate itself, capacitance present in the overlapping region of the gate and the junction region, and the like. The capacitance present in the overlapping portion of the gate and the junction region can be divided into two types, one of which is the capacitance present in the overlapping portion of the gate region and the junction region, and the other between the gate side and the junction region. The capacitance present in. The parasitic capacitances cause an undesirable problem of decreasing the speed of the semiconductor device by increasing the resistive capacitance delay of the gate.
도 1은 종래 방법에 따라 제조된 반도체 장치의 단면도를 나타낸다. 도 1을 참조하면, 반도체 기판(100)에 게이트 절연막(102)을 형성하고 게이트 전극(104)을 형성하여 게이트 영역을 형성한다. 그리고 이온주입을 실시하여 접합 영역(106)을 형성하고 이어서 스페이서 절연막(106)을 형성한 후, 상기 반도체 기판(100)전면에 텅스텐(W)이나 티타늄(Ti)등의 금속을 형성한다. 이어서 소위 살리사이드(salicide)이라 일컬어지는 열처리 공정을 실시하여 접합 영역과 게이트 전극(104)상에 각각 실리사이드(108)와 폴리사이드(110)를 형성한다. 그리고 도시하지는 않았으나 살리사이데이션(salicidation) 되지못한 부분의 상기 금속들은 제거한다. 상기 트랜지스터에는 비록 눈에 보이지는 않지만 게이트 영역에 기생 캐패시턴스들이 발생한다. 상기 기생 캐패시턴스들이 발생하는 영역들을 부호 a와 b로 나타내었다. 부호 a와 b는 게이트 영역 하부와 접합 영역이 중첩되는 부분에 존재하는 캐패시턴스와 게이트 측면과 접합 영역 사이에 존재하는 캐패시턴스를 나타낸다.1 shows a cross-sectional view of a semiconductor device manufactured according to a conventional method. Referring to FIG. 1, a gate insulating layer 102 is formed on a semiconductor substrate 100 and a gate electrode 104 is formed to form a gate region. After the ion implantation is performed to form the junction region 106 and then the spacer insulating layer 106, a metal such as tungsten (W) or titanium (Ti) is formed on the entire surface of the semiconductor substrate 100. Subsequently, a heat treatment process called a salicide is performed to form the silicide 108 and the polyside 110 on the junction region and the gate electrode 104, respectively. Although not shown in the drawing, the metals of the non-salicated portion are removed. Although not visible in the transistor, parasitic capacitances occur in the gate region. Areas in which the parasitic capacitances occur are denoted by symbols a and b. Reference numerals a and b denote capacitances existing at portions where the gate region and the junction region overlap, and capacitances existing between the gate side and the junction region.
상기한 종래 방법에 의하면 게이트 영역 하부와 접합 영역이 중첩되는 부분과 게이트 영역 측면과 접합 영역 사이에 캐패시턴스가 모두 존재하므로 게이트에 선택신호를 전달할 경우 많은 저항 용량 지연이 유발되어 동작 속도가 다소 느려지는 문제점이 있다. 따라서 상기 기생 캐패시턴스를 줄임으로써 반도체 장치의 특성을 개선할 수 있는 제조 기술이 본 분야에서 절실히 요구되어지고 있는 실정이다.According to the above-described conventional method, since both capacitances exist between the overlapped portion of the gate region and the junction region, and between the gate region side and the junction region, when the selection signal is transmitted to the gate, a large amount of resistive capacitance is delayed and the operation speed becomes slightly slower. There is a problem. Therefore, there is an urgent need in the art for a manufacturing technology capable of improving the characteristics of semiconductor devices by reducing the parasitic capacitance.
따라서 본 발명의 목적은, 게이트 영역 측면과 접합 영역 사이에 발생하는 기생 캐패시턴스를 줄임으로써 저항 용량 지연을 감소시켜 동작속도를 증가시킬 수 있는 개선된 반도체 메모리 장치용 트랜지스터의 제조 방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a method of manufacturing a transistor for a semiconductor memory device, which can increase the operation speed by reducing the resistance capacitance delay by reducing the parasitic capacitance occurring between the side of the gate region and the junction region.
도 1은 종래 방법에 따라 제조된 반도체 메모리 장치용 트랜지스터를 나타내는 단면도이다.1 is a cross-sectional view showing a transistor for a semiconductor memory device manufactured according to a conventional method.
도 2a 내지 도 2d는 본 발명의 일실시예에 따른 반도체 메모리 장치용 트랜지스터의 제조 방법을 순차적으로 나타낸 단면도들이다.2A through 2D are cross-sectional views sequentially illustrating a method of manufacturing a transistor for a semiconductor memory device according to an embodiment of the present invention.
상기의 목적을 달성하기 위해서 본 발명은, 게이트 영역 측면과 스페이서 사이에 일정 간격을 가짐으로써 기생 캐패시턴스가 줄어든 반도체 메모리 장치용 트랜지스터의 제조 방법을 제공한다.In order to achieve the above object, the present invention provides a method of manufacturing a transistor for a semiconductor memory device, the parasitic capacitance is reduced by having a predetermined interval between the gate region side and the spacer.
그러한 트랜지스터의 제조 방법은, 반도체 기판에 게이트 영역과 소오스/드레인으로 기능할 접합 영역을 형성하는 단계와; 제1스페이서 절연막과 제2스페이서 절연막을 차례로 형성하는 단계와; 상기 제1스페이서 절연막을 제거하는 단계와; 상기 게이트 영역과 접합 영역에 실리사이드 및 폴리사이드를 형성시키는 단계를 포함함을 특징한다.A method of manufacturing such a transistor includes forming a junction region in a semiconductor substrate to function as a gate region and a source / drain; Sequentially forming a first spacer insulating film and a second spacer insulating film; Removing the first spacer insulating film; And forming silicides and polysides in the gate region and the junction region.
이하, 본 발명의 바람직한 일실시예를 첨부한 도면을 참조하여 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a는 도 2d는 본 발명에 따른 반도체 메모리 장치용 트랜지스터의 제조 방법을 설명하기 위한 도면들이다.2A is a diagram for describing a method of manufacturing a transistor for a semiconductor memory device according to the present invention.
도 2a에는 스페이서 절연막의 제조 단계가 도시되어 있다. 반도체 기판(10)에 게이트 절연막으로 사용될 제1절연막(12)과, 게이트 전극으로 사용될 제1도전막(14)을 형성하여 게이트 영역(15)을 형성하고, 상기 반도체 기판(10)에 피(P)형 또는 엔(N)형의 이온을 주입하여 접합 영역(16)을 형성한다. 바람직하게는, 상기 제1절연막(12)은 100Å의 산화막(SiO2), 상기 제1도전막(14)은 2000Å의 폴리실리콘으로 각각 형성한다. 그리고 나서 상기 접합 영역(16)이 형성된 상기 반도체 기판(10) 전면에 제2절연막을, 바람직하게는 식각식각비가 우수한 SiN 이나 SiON을 약 500Å으로 형성하고 전면 에치백하여 상기 게이트 영역(15)측면에 제1스페이서 절연막(18)을 형성한다. 그리고 상기 제1스페이서 절연막(18)이 형성된 상기 반도체 기판(10)전면에 제3절연막을, 바람직하게는 1500Å의 고온산화막(high temperature oxide)을 형성하고 전면 에치백하여 상기 제1스페이서 절연막 측면에 제2스페이서 절연막(20)을 형성한다. 바람직하게는, 상기 제2스페이서 절연막은 상기 제1스페이서 절연막의 상부 일부가 노출되도록 상기 제1스페이서 절연막보다 약간 낮은 높이로 형성시킨다. 상기 제1스페이서 절연막의 일부 노출된 부분을 통해 후속의 습식식각공정에서 식각액이 침투된다.2A shows a manufacturing step of the spacer insulating film. The first insulating film 12 to be used as the gate insulating film 12 and the first conductive film 14 to be used as the gate electrode are formed on the semiconductor substrate 10 to form the gate region 15. A junction region 16 is formed by implanting ions of P) or N (N) type. Preferably, the first insulating film 12 is formed of an oxide film (SiO 2 ) of 100 GPa and the first conductive film 14 is formed of polysilicon of 2000 GPa, respectively. Then, a second insulating film is formed on the entire surface of the semiconductor substrate 10 on which the junction region 16 is formed, preferably SiN or SiON having an excellent etch ratio of about 500 GPa and the entire surface is etched back to the side of the gate region 15 The first spacer insulating film 18 is formed in the film. In addition, a third insulating film is formed on the entire surface of the semiconductor substrate 10 on which the first spacer insulating film 18 is formed, preferably a high temperature oxide of 1500 kV, and is etched back to the entire surface of the first spacer insulating film. The second spacer insulating film 20 is formed. Preferably, the second spacer insulating film is formed to have a height slightly lower than that of the first spacer insulating film so that an upper portion of the first spacer insulating film is exposed. The etching liquid penetrates through the partially exposed portion of the first spacer insulating layer in a subsequent wet etching process.
도 2b에는 상기 제1스페이서 절연막을 제거하는 단계가 도시되어 있다. 상기 제1/제2스페이서 절연막(18,20)이 형성된 상기 반도체 기판(10)에 제1스페이서 절연막(18)만을 선택적으로 제거하기 위해 인산등이 함유된 식각액을 사용하여 습식식각공정을 실시한다. 그 결과, 상기 게이트 영역(15)측면과 상기 제2스페이서 절연막(20) 사이, 즉 상기 제1스페이서 절연막(18)이 존재하였던 부분은 빈공간(19)으로 남게된다.2B illustrates a step of removing the first spacer insulating layer. A wet etching process is performed using an etchant containing phosphoric acid to selectively remove only the first spacer insulating film 18 from the semiconductor substrate 10 having the first and second spacer insulating films 18 and 20 formed thereon. . As a result, the space between the side of the gate region 15 and the second spacer insulating film 20, that is, the portion where the first spacer insulating film 18 existed, remains as the empty space 19.
도 2c에는 제2도전막(22)을 형성하는 단계가 도시되어 있다. 상기 제1스페이서(18)가 제거되고 빈공간(19)이 형성된 상기 반도체 기판(10)에 제2도전막(22)을 형성하기 위해, 예컨대 텅스텐(W), 티타늄(Ti), 몰리브덴(Mo)등의 고용융 물질을 약 500Å의 두께로 전면 형성시킨다. 이때, 상기 빈공간(19)이 도면상으로는 크게 형성되어 있지만, 이는 본 발명의 요지를 위해 크게 부각시킨 것으로서 실제로는 아주 미세한 틈이다. 게다가 상기 도전막(22)을 형성할 때, 상기 빈공간(19)의 윗부분은 더욱 좁기 때문에 상기 빈공간(19)으로는 도전막(22)이 침투되지 않고 막힘으로써 상기 빈공간(19)은 그대로 유지된다. 따라서 상기 비공간(19)에는 유전율이 보다 낮은 공기(air)로 채워지거나 진공상태로 존재하게 된다.In FIG. 2C, the step of forming the second conductive film 22 is illustrated. For example, tungsten (W), titanium (Ti), and molybdenum (Mo) are formed in order to form the second conductive film 22 on the semiconductor substrate 10 in which the first spacer 18 is removed and the empty space 19 is formed. Solid solution such as) is formed to a total thickness of about 500 mm 3. At this time, the empty space 19 is formed large in the drawing, but this is a very large gap in fact for the gist of the present invention is a very fine gap. In addition, when the conductive film 22 is formed, since the upper portion of the empty space 19 is narrower, the conductive film 22 does not penetrate into the empty space 19 so that the empty space 19 is blocked. It stays the same. Accordingly, the non-space 19 is filled with air having a lower dielectric constant or exists in a vacuum state.
도 2d에는 실리사이드(23) 및 폴리사이드(24)의 형성단계가 도시되어 있다. 상기 제2도전막(22)이 형성된 상기 반도체 기판(100)에 통상의 살리사이드 공정, 즉 약 600℃ 이상의 온도로 열처리를 실시하면, 상기 제2도전막(22)은 상기 접합 영역(16)의 실리콘 및 상기 게이트 전극(14)의 폴리실리콘과 반응하여 실리사이드(23) 및 폴리사이드(24)가 형성된다. 이로써 상기 빈공간(19)은 상기 게이트 영역(15), 제2스페이서 절연막(20), 폴리사이드(24), 그리고 접합 영역(16)으로 둘러싸인 사다리꼴 모양의 공간을 형성하게 된다. 상기 형성된 실리사이드(23) 및 폴리사이드(24)는 후속 공정에서 콘택에 의해 상부 전극과 연결되는 하부 전극으로서 기능하게 된다. 그리고 나서 살리사이데이션 되지 못한 일부 상기 제2도전막, 즉 상기 제2스페이서 절연막(18)상에 형성되었던 상기 제2도전막(22)은 제거한다.2D shows the formation of silicide 23 and polyside 24. When the semiconductor substrate 100 on which the second conductive film 22 is formed is heat-treated at a normal salicide process, that is, at a temperature of about 600 ° C. or more, the second conductive film 22 is bonded to the junction region 16. Reacts with silicon and polysilicon of the gate electrode 14 to form silicide 23 and polyside 24. As a result, the empty space 19 forms a trapezoidal space surrounded by the gate region 15, the second spacer insulating layer 20, the polyside 24, and the junction region 16. The formed silicides 23 and polysides 24 serve as bottom electrodes that are connected to the top electrodes by contacts in subsequent processes. Then, the second conductive film, which has not been salicided, that is, the second conductive film 22 formed on the second spacer insulating film 18 is removed.
상기와 같이 본 발명에 따라서 반도체 메모리 장치용 트랜지스터를 제조할 경우, 게이트 영역 측면과 제2스페이서 절연막 사이의 제1스페이서 절연막을 제거하여, 게이트 영역과 제2스페이서 사이에는 유전율이 보다 낮은 공기가 채워지거나 진공상태에 놓이게 된다. 이처럼 게이트 영역과 스페이서 절연막 사이에 빈공간이 형성되므로 게이트 영역의 측면 기생 캐패시턴스는 감소하여 반도체 메모리 장치용 트랜지스터의 특성은 보다 개선된다.As described above, when fabricating a transistor for a semiconductor memory device according to the present invention, the first spacer insulating film between the gate region side and the second spacer insulating film is removed, so that air having a lower dielectric constant is filled between the gate region and the second spacer insulating film. Or vacuumed. As such, a void space is formed between the gate region and the spacer insulating film, so that side parasitic capacitance of the gate region is reduced, thereby improving the characteristics of the transistor for the semiconductor memory device.
상술한 바와 같이 본 발명의 바람직한 실시예를 참조하여 설명하였지만 하기의 특허 청구 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위내에서 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.Although described with reference to the preferred embodiment of the present invention as described above, it will be understood that various modifications and changes can be made without departing from the spirit and scope of the present invention as set forth in the claims below.
Claims (12)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970041542A KR19990018366A (en) | 1997-08-27 | 1997-08-27 | Manufacturing Method of Transistor for Semiconductor Memory Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970041542A KR19990018366A (en) | 1997-08-27 | 1997-08-27 | Manufacturing Method of Transistor for Semiconductor Memory Device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19990018366A true KR19990018366A (en) | 1999-03-15 |
Family
ID=66046778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970041542A KR19990018366A (en) | 1997-08-27 | 1997-08-27 | Manufacturing Method of Transistor for Semiconductor Memory Device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR19990018366A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100546286B1 (en) * | 1999-03-26 | 2006-01-26 | 삼성전자주식회사 | Manufacturing method of SOI transistor |
| US9331072B2 (en) | 2014-01-28 | 2016-05-03 | Samsung Electronics Co., Ltd. | Integrated circuit devices having air-gap spacers defined by conductive patterns and methods of manufacturing the same |
-
1997
- 1997-08-27 KR KR1019970041542A patent/KR19990018366A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100546286B1 (en) * | 1999-03-26 | 2006-01-26 | 삼성전자주식회사 | Manufacturing method of SOI transistor |
| US9331072B2 (en) | 2014-01-28 | 2016-05-03 | Samsung Electronics Co., Ltd. | Integrated circuit devices having air-gap spacers defined by conductive patterns and methods of manufacturing the same |
| US9911851B2 (en) | 2014-01-28 | 2018-03-06 | Samsung Electronics Co., Ltd. | Integrated circuit devices having air-gap spacers above gate electrodes |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4907838B2 (en) | Memory device having a recessed gate structure | |
| US6787833B1 (en) | Integrated circuit having a barrier structure | |
| US11737257B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20210111177A1 (en) | Memory devices and methods of fabricating the same | |
| US5966612A (en) | Method of making a multiple mushroom shape capacitor for high density DRAMs | |
| US10529423B2 (en) | DRAM device with embedded flash memory for redundancy and fabrication method thereof | |
| US6329232B1 (en) | Method of manufacturing a semiconductor device | |
| KR19990045262A (en) | DRAM-cell device and manufacturing method thereof | |
| KR100545144B1 (en) | Reliable policide gate stack with reduced sheet resistance | |
| KR100309619B1 (en) | Spacers to block deep junction implants and silicide formation in integrated circuits | |
| KR0151385B1 (en) | Semiconductor memory device and its manufacturing method | |
| US6174762B1 (en) | Salicide device with borderless contact | |
| KR20050027294A (en) | Method for forming recess gate for use in semiconductor memory | |
| US6410399B1 (en) | Process to lower strap, wordline and bitline contact resistance in trench-based DRAMS by silicidization | |
| US7060575B2 (en) | Semiconductor device having transistor and method of manufacturing the same | |
| US6518613B2 (en) | Memory cell configuration with capacitor on opposite surface of substrate and method for fabricating the same | |
| US5736441A (en) | High-capacitance dynamic random access memory cell and method for fabricating the same | |
| US6555435B2 (en) | Method to eliminate shorts between adjacent contacts due to interlevel dielectric voids | |
| KR19990018366A (en) | Manufacturing Method of Transistor for Semiconductor Memory Device | |
| US6303433B1 (en) | Method of fabricating node contact | |
| US5851872A (en) | Method of fabricating dynamic random access memory | |
| US5902123A (en) | Method of fabricating a stacked capacitor of a dynamic random access memory | |
| US6483144B2 (en) | Semiconductor device having self-aligned contact and landing pad structure and method of forming same | |
| US6133090A (en) | Method of fabricating cylindrical capacitor | |
| KR100418090B1 (en) | Method for manufacturing a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |