KR19990016296A - Synchronous method of synchronous stream cipher and its apparatus - Google Patents

Abstract

The present invention relates to a synchronization method and apparatus for synchronous stream cryptography in which received data can be normally decoded by suppressing consecutive zeroes in received data by more than a predetermined number of bits to accurately recover a received clock. Generally, in order to encrypt a digital data signal, a binary random number sequence having a uniform probability distribution is mixed with digital data, and the output encrypted data has a randomness characteristic in which 1's and 0's are uniformly distributed. However, if the above encryption scheme is applied to the T1-PCM line, excessive continuous 0s may appear in the received data, which causes the reception clock reproduction to become unstable. Therefore, shall. Therefore, according to the present invention, a plaintext block is mixed with a random number sequence block, and when all the bits of the mixed block and all bits of the plaintext block are not 0, the mixed block is transmitted as a ciphertext block, If all the bits of the plaintext block are 0, the three mixed blocks including the previous and the next block are transmitted as a ciphertext block starting from the beginning of the previous plaintext block. And a bit of the plaintext block starting from 1, and transmits the ciphertext block to the ciphertext block. The received ciphertext block is received and mixed with the random number sequence block, and all bits of the mixed block and all of the ciphertext blocks If the bit is not 0, outputs the mixed block to the decoded block, and when all bits of the mixed block are 0, And outputs the ciphertext block corresponding to the ciphertext block as a decryption block instead of the sum block, and when all the bits of the ciphertext block are 0, It is possible to suppress the continuation of 0 for at least a predetermined number of bits even after encryption without requiring the assumption that all bits of the plaintext block are not 0, So that error diffusion can be minimized even if a channel error occurs.

Description

Synchronous method of synchronous stream cipher and its apparatus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous stream cipher method for encrypting and transmitting a digital data signal, and more particularly, To a synchronous stream cipher method and apparatus for synchronizing stream cipher.

In digital communication, the performance depends on how accurate the clock signal can be recovered from the receiver. Generally, the clock signal is recovered from the clock information according to the data transition using a phase locked loop do.

However, when there is no transition among the transmission data, that is, when 0 or 1 is continuous, clock recovery can not be performed on the receiving side. Therefore, in the PCM method, not only a special restriction is applied so that the number of zeros can be suppressed by 15 or more at the time of coding at the time of speech coding, but also the AMI (Alternate Marked Inversion) line line) coding, it can be said that countermeasures for perfect clock recovery are taken.

FIG. 1 is a block diagram of a conventional synchronous stream cipher transmission and reception system. As shown in FIG. 1, the random number sequence data generated from a transmission random number sequence generator 1 with a uniform probability distribution is added to a digital plaintext data, And transmits the ciphertext data thus received to the received ciphertext data by mixing the random number sequence data generated with the uniform probability distribution from the received random number sequence generator 3 through the summer 4, As shown in FIG. Therefore, the transmitted ciphertext data has a randomness characteristic in which 1 and 0 are uniformly distributed.

Applying this encryption scheme to the T1-PCM circuit, the probability that a K-bit continuous 0 phenomenon appears in the ciphertext data output is Thus, there is a problem that the clock regeneration becomes unstable when 0 of the received data continuously appears. For example, since the PCM repeater is designed to withstand up to 15 consecutive zeroes, a cryptosystem capable of suppressing zero or more than 15 consecutive ciphers after the ciphertext is required for stable clock regeneration.

Therefore, it is an object of the present invention to provide an apparatus and a method for restoring a received clock accurately by restoring a received clock accurately by not allowing consecutive 0s of K bits or more in a ciphertext data block even if the consecutive 0 suppression assumption is not satisfied in a plaintext data block, And to provide a synchronization method and apparatus for synchronous stream cryptography that can minimize error diffusion even when an error occurs.

1 is a schematic diagram of a conventional synchronous stream transmission and reception system.

2 is a schematic diagram of a synchronous stream cipher transmission and reception system according to the present invention;

3 is a block diagram of a synchronous stream cryptographic apparatus according to the present invention;

Description of the Related Art [0002]

1: transmitted random number sequence generator 2, 4: adder

3: Received Random Number Generator

501, 502, 505, 506, 601, 602, 605, 606:

503, 504, 603, and 604:

507, 607: central processing unit

508, 608: switch

It is an object of the present invention to provide a decoding apparatus and a decoding method and a decoding method thereof, in which a transmission random number sequence block is mixed with a plaintext block, and it is detected that all bits of the mixed block are 0 and all bits of the plaintext block are 0, If all the bits of the mixed block are not 0, the mixed block is normally transmitted as a ciphertext block. If all bits of the mixed block are 0, the plaintext block corresponding to the mixed block is transmitted to the ciphertext block If all the bits of the plaintext block are 0, the upper part of the plaintext block, the plaintext block, and the lower bits of the plaintext block are written into the ciphertext block. Alternately transmits the received ciphertext block to the received ciphertext block, mixes the received ciphertext block with the received ciphertext block, and detects whether all bits of the ciphertext block are 0 And if all bits of the received ciphertext block are 0, and if all the bits of the ciphertext block and the all bits of the ciphertext block are not 0, the ciphertext block is normally output as a deciphered sentence block, If all the bits of the ciphertext block are 0, the ciphertext block corresponding to the mixed block is replaced with a deciphered block, and if all bits of the ciphertext block are 0, The ciphertext block, and the lower part of the ciphertext block to which the 1 is started are replaced by a decipher block, which will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a synchronous stream cipher transmission and reception system according to the present invention. As shown in FIG. 2, a summator 2 for mixing a plaintext block with a random number sequence block of a transmission random number sequence generator 1, And detects whether all the bits of the mixed block are 0, and detects whether all bits of the plain block are 0, so that all bits of the mixed block and all bits of the plain block Is not 0, normally transmits the mixed block as a ciphertext block, and when all bits of the mixed block are 0, the plain text block corresponding to the mixed block is replaced with a ciphertext block and transmitted, If all the bits of the plaintext block are 0, the upper part of the bit of the previous plaintext block starting from 1, the plaintext block of the previous plaintext block, and the bit (4) for mixing the transmitted and received ciphertext block with a random number sequence block of the received random number sequence generator (3), and an adder Receives the mixed block of the summer 4 and the received ciphertext block and detects whether all bits of the ciphertext block are 0 and whether all bits of the ciphertext block are 0, If all the bits of the mixed block are not 0, the mixed block is normally output to the decoded block, and if all the bits of the mixed block are 0, the corresponding ciphertext block corresponding to the mixed block is decoded If all the bits of the ciphertext block are 0, an upper part from the bit where 1 of the previous ciphertext block starts, instead of the mixed block, Block and a 0-detecting and substituting unit 6 for outputting a lower-order part of the ciphertext block up to the bit at which the 1 starts.

For the sake of simplicity, n-bit plaintext blocks, random-numbered blocks, and ciphertext blocks are set as follows, where block size selection is n = [(k + 1) / 2] and [X] do.

1) th plaintext block Pi: (P _in , P _{in + 1} , ..., P _{in + n-1} )

(k _in , K _{in + 1} , ..., K _{in + n-1} )

1) th ciphertext block Ci (C _in , C _{in + 1} , ..., C _{in + n-1} )

i < th decrypted text block _{Qi: (Q in, Q in} + 1, ···, Q in + n-1)

Vector 0: (0,0, ..., 0)

Vector 1: (0, 0, ..., 1)

FIG. 3 is a block diagram of a synchronous stream cryptographic apparatus according to the present invention. As shown in FIG. 3A, the synchronous stream cryptographic apparatus comprises a summer 2 for mixing and outputting a plaintext block Pi with a random number A shift register 501 for storing and outputting Pi in synchronization with the system clock, A shift register 502 for storing the shift register 502 in synchronization with the system clock and a 0 detection unit 503 for detecting whether all the bits of the clear block Pi of the shift register 501 are 0, Mixing block A shift register 505 for storing and outputting the previous plaintext block Pi-1 output from the shift register 501 in synchronism with the system clock, The previous mixed block output from the shift register 502 A shift register 506 for storing and outputting the 0 detection signals DT1 and DT2 of the 0 detection units 503 and 504 synchronously with the system clock and outputs the zero detection signals DT1 and DT2 to the shift register 505 In a state in which none of the zero detection signals DT1 and DT2 is output in response to the stored plaintext block Pi-1, And sends it to the ciphertext block Ci-1 in a state in which only the zero detection signal DT2 is output, And transmits the selected plaintext block Pi to the ciphertext block Ci after selecting the plaintext block Pi stored in the shift register 505. In the state where the 0 detection signal DT1 is output The upper part of the previous plaintext block Pi-1 of the shift register 505 from the beginning of the 1 and the previous mixed block of the shift register 506 (Ci-1), selects a plaintext block Pi to be stored in the shift register 505, and transmits the selected plaintext block Pi to the ciphertext block Ci, Then, the lower part of the plaintext block Pi + 1 stored in the shift register 505 up to the bit at which 1 starts and the mixed block of the shift register 506 A central processing unit 507 and a switch 508 for selecting an upper part excluding the lower part and transmitting the upper part to the ciphertext block Ci + 1.

3B, the adder 4 for mixing the ciphertext block Ci with the random number generating block Ki and the adder 4 for combining the ciphertext block Ci and the summing block 4, (601) and (602) for storing and outputting a ciphertext block (Ci) of the shift registers (601) and (602) synchronously with the system clock, 0 detection sections 603 and 604 for detecting whether all the bits are 0 or not and a previous ciphertext block Ci-1 output from the shift registers 601 and 602 and a previous ciphertext block Ci- 602 and 604 for storing and outputting 0 detection signals DT1 and DT2 of the 0 detection units 603 and 604 in synchronism with the system clock, The crosstalk block Ci-1 stored in the register 605 is input and in a state in which none of the zero detection signals DT1 and DT2 is output, And outputs it to the decoded block Qi-1. In a state in which only the zero detection signal DT2 is output, the previous mixed block < RTI ID = 0.0 > And outputs the decrypted block Qi to the decryption block Qi-1 and then outputs the decrypted block Qi stored in the movement register 605 to the decryption block Qi. State from the bit at which 1 of the previous ciphertext block Ci-1 of the shift register 605 starts to the upper part and the previous mixed block of the shift register 606 (Qi-1), selects a ciphertext block Ci stored in the shift register 605 and outputs the selected ciphertext block Ci to the decipher block Qi, The lower part of the ciphertext block Ci + 1 stored in the shift register 605 up to the bit where 1 starts is stored in the shift register 605, A central processing unit 607 and a switch 608 for selecting an upper part excluding the lower part and outputting the upper part to a decipher block Qi + 1.

The zero detectors 503, 504, 603, and 604 correspond to the exclusive OR gates of the shift registers 501, 502, 503, The AND gate which inverts and receives the blocks of the blocks 502, 601 and 602 or the blocks of the shift registers 501, 502, 601, It is a gate.

The method and effect of the present invention will be described in detail as follows.

An arbitrary n-bit plain text block Pi is input to the summer 2 and mixed with an arbitrary n-bit random number sequence block Ki input from the transmission random number sequence generator 1, The plaintext block Pi is stored in the shift register 501 in synchronism with the system clock and is output to the shift register 501. The shift register 501 is connected to the shift register 501, The previous plaintext block Pi-1 output from the shift register 502 is stored in the shift register 505 in synchronization with the system clock, Is also stored in the shift register 506 in synchronization with the system clock and outputted. When the plaintext block Pi is stored in the shift register 501 as described above, the plaintext block Pi is input to the 0 detection unit 503, and when all the bits of the plaintext block Pi are 0 0 " detection signal DT1. That is, when all the bits of the plaintext block Pi are 0, all of the signals are inverted and received and combined to output 1, which is the zero detection signal DT1.

Likewise, Is stored in the shift register 502, Quot; 1 " which is the zero detection signal DT2 when all the bits of the " 0 "

As described above, the central processing unit 507 receives the zero detection signals DT1 and DT2 output from the zero detection units 503 and 504 and determines whether the zero detection signals DT1 and DT2 are input And controls the selection of the switch 508 to output the ciphertext block Ci-1. That is, under the condition that the zero detection signals DT1 and DT2 are not output, the switch 508 is turned on by the control of the central processing unit 507, And transmits it to the cipher text block Ci-1.

In the state in which the zero detection signal DT2 is output only from the 0 detection unit 504, the control signal from the switch 508 to the previous mixing block 504 of the shift register 506, under the control of the central processing unit 507, To select a ciphertext block And then stored in the mobility controller 505 in the switch 508. The plain- To select a ciphertext block . That is, When the zero detection signal DT2 is output, Instead, the corresponding plaintext block To select a ciphertext block .

In the state where the 0 detection signal DT1 is output from the 0 detection unit 503, the control unit 507 controls the switch 508 to select the previous plain- 1 < / RTI > from the beginning of the bit and the previous mix block of the shift register 506 The previous plaintext block A lower part excluding the upper part corresponding to the upper part of the ciphertext block Which is stored in the shift register 505 in the switch 508, To select a ciphertext block Which is stored in the shift register 505 in the switch 508, The lower portion of the bit to which < RTI ID = 0.0 > 1 < / RTI > The plaintext block The upper part excluding the lower part corresponding to the lower part of the ciphertext block . That is, When the zero detection signal DT1, in which all the bits of the previous mixed block are zero, Previous plaintext block The ciphertext block is partially replaced from the bit where the < RTI ID = 0.0 > 1 < / RTI & , And the mixed block The plaintext block The ciphertext block , And then the mixed block After the plaintext block The ciphertext block is partially replaced with the lower-order bits up to the bit at which the " 1 " .

On the other hand, the cipher text block Is inputted to the summer 4 and is inputted to the random number generator block 3 inputted from the received row number generator 3, And the ciphertext block And the mixed- Is stored in the shift registers 601 and 602 in synchronization with the system clock and output and stored in the shift registers 601 and 602, And mixing block Are respectively stored in the shift registers 605 and 606 in synchronization with the system clock and output. At this time, the 0 detection units 603 and 604 are operated in the same way as the 0 detection units 503 and 504 of the transmitter, The 0 detection signal DT1 of 1 is output when all the bits of the mixed block 602 are 0, The zero detection signals DT1 and DT2 are input to the central processing unit 607. The zero detection signals DT1 and DT2 are input to the central processing unit 607. [

Therefore, in a state where the zero detection signals DT1 and DT2 are not output from the 0 detection units 603 and 604, the control unit 607 controls the switch 608 to move the shift register 606 Old Mixed Block To select a decrypted sentence block .

In the state in which the zero detection signal DT2 is output only from the 0 detection unit 604, the control signal from the switch 608 to the previous mixing block 604 of the shift register 606, under the control of the central processing unit 607, To select a decrypted sentence block And then outputs the ciphertext block stored in the shift register 605 in the switch 608 To select a decrypted sentence block . That is, When the zero detection signal DT2 is output, Instead, To select a decrypted sentence block .

In the state where the 0 detection signal DT1 is output by the 0 detection unit 603, the control unit 607 controls the switch 608 to select the previous ciphertext block Lt; RTI ID = 0.0 > 606 < / RTI > The previous ciphertext block The lower part excluding the upper part corresponding to the upper part of the decrypted sentence block And then, in the switch 608, the cipher text block stored in the shift register 605 To select a decrypted sentence block And then outputs the ciphertext block stored in the shift register 605 in the switch 608 The lower portion of the bit to which < RTI ID = 0.0 > 1 < / RTI & The ciphertext block The upper part excluding the lower part corresponding to the lower part of the decrypted sentence block . That is, When the zero detection signal DT1, in which all the bits of the previous mixed block are zero, To the previous ciphertext block 1 < / RTI > from the beginning of the decoded block, And outputs the mixed block, Cryptographic block The decryption block And then outputs the mixed block After the ciphertext block 1 < / RTI > to the beginning of the decoded block < RTI ID = 0.0 > .

As a result, k-bit consecutive zeros are also suppressed in the cascade block output of the sender, assuming that k bits (k = 2n-1 or k = 2n) consecutive zeros in any n-bit plaintext block are suppressed, Is completely decoded as follows.

Without block replacement In the transmitting terminal, And Because of and Is transmitted, and at the receiving end Because of, and .

Also, if there is only one block replacement In the transmitting terminal, And Because of and Is transmitted, and at the receiving end And Because of, and .

Also, if there is a replacement of 3 blocks ( Quot;), Because of Partial substitution of, , Is transmitted at the receiving end Because of Partial substitution of = Partial substitution of = .

As described in detail above, according to the present invention, even if a channel error occurs in a middle block portion of three blocks, the error diffusion is not performed with 3n bits, and error diffusion of bits smaller than the 3n bits occurs. Can be minimized.

Claims (7)

A first step of detecting whether all bits of the plaintext block are 0, mixing the plaintext block with a random number sequence block to detect whether all bits of the mixed block are 0, And if all the bits of the mixed block are not 0, the mixed block is transmitted as a ciphertext block. If all bits of the mixed block are 0, the corresponding plain text block is transmitted as a ciphertext block instead of the mixed block, If all the bits of the plaintext block are 0, the three mixed blocks including the before and after blocks are partially replaced by the bits starting from 1 of the previous plaintext block to the bit beginning with 1 of the plaintext block, A second step of receiving the transmitted ciphertext block and detecting whether all bits of the ciphertext block are 0, A third step of detecting whether all bits of the mixed block are 0, and if all the bits of the ciphertext block and the mixed block are not 0 in the third step, the mixed block is output to the decryption block If all the bits of the ciphertext block are 0, the ciphertext block corresponding to the mixed block is output to the deciphertext block instead of the mixed block. If all the bits of the ciphertext block are 0, And outputting the block to a decryption block, the block being partially replaced with a bit from the beginning of 1 of the previous ciphertext block to the beginning of 1 of the subsequent ciphertext block. The method of claim 1, wherein mixing in the first and third steps is performed by exclusive OR combination for each bit. The synchronizing method of a synchronous stream cipher according to claim 1 or 2, wherein detection of all bits in the first and third processes is performed by inverting and receiving the data of the block. A first summing unit for mixing a plaintext block with a random number generating block generated by a transmission random number generator, a first shift register for storing and outputting the plain text block, a second shift register for storing and outputting a mixed block of the first summer, And a second 0 detection unit for detecting whether all the bits of the mixed block stored in the second shift register are 0, and a 0 < th > detection unit for detecting whether all the bits of the clear block stored in the first shift register are 0, A third shift register for storing and outputting a previous plain text block output from the first shift register, a fourth shift register for storing and outputting a previous mixed block output from the second shift register, The second 0 detection unit selects the mixed block of the fourth shift register in the state in which the first and second 0 detection signals are not outputted and outputs the mixed block to the ciphertext block, In a state in which only the second detection signal is output, the plaintext block stored in the third shift register is alternatively selected and transmitted as a ciphertext block, and when the first 0 detection signal is output, , And then sends the ciphertext selection block to the ciphertext block by partially replacing the three mixed blocks including the block from the bit of the first plaintext block of the third shift register to the bit of the subsequent plaintext block beginning with 1, A second summator for receiving the transmitted ciphertext block and mixing the received ciphertext block with a random number sequence generated by the received random number sequence generator, a fifth shift register for storing and outputting the ciphertext block, A sixth shift register for storing the mixed block and outputting the mixed block; A fourth detection section for detecting whether all the bits of the mixed block stored in the sixth shift register are 0 and a fourth detection section for detecting whether or not all bits of the mixed block stored in the sixth shift register are 0; An eighth shift register for storing and outputting a previous mixed block output from the sixth shift register, and a third shift register for outputting the third and fourth detection signals in the third and fourth detection units And outputs the selected block to the decryption block. In a state where only the fourth detection signal is output, the ciphertext block stored in the seventh shift register is alternatively selected and decrypted And outputs the third mixed block including the previous and subsequent blocks of the eighth shift register in the state where the third 0 detection signal is outputted to the seventh And a decryption instruction selecting and outputting means for selecting a partial substitution from the bit of the previous ciphertext block of the shift register to the bit of the subsequent ciphertext block starting at 1, Synchronization of stream ciphers. 5. The synchronous stream cipher of claim 4, wherein the first and second summers are comprised of exclusive OR gates that are exclusive-ORed for each bit. The synchronous stream cipher system according to claim 4 or 5, wherein the first, second, third, and fourth detection units are configured by AND gates for inverting and receiving data of the block. Device. 6. The synchronous stream cipher system according to claim 4 or 5, wherein the first, second, third, and fourth detection units are configured by a Noah gate for directly receiving data of the block and combining them with each other. Device.