KR19990015874A - A column selection line driving method, a column selection line driving signal control circuit used therefor, and a semiconductor memory device having the same - Google Patents

Abstract

A column selection line driving method, a column selection line driving signal control circuit used therefor, and a semiconductor memory device having the same. A column select line driving method according to the present invention is a method for driving a column select line driver during a read operation and a column select line driver during a read operation so as to drive an internal power supply voltage (V _INT ) By temporarily reducing the bit line voltage drop (dip) or rise (bump) generated by the supply voltage precharged to the input / output line pair and by driving with the external supply voltage (V _EXT ) The data stored in the line pair is quickly transferred to the bit line to prevent the write operation from being degraded.

Description

A column selection line driving method, a column selection line driving signal control circuit used therefor, and a semiconductor memory device having the same

The present invention relates to a semiconductor memory device and a driving method thereof, and more particularly, to a column selection line driving method capable of suppressing a temporary voltage decrease or a voltage increase occurring during bit line sensing, a driving signal control circuit To a semiconductor memory device.

[0003] Semiconductor memory devices are generally based on an operation of selecting and reading / writing a cell by a row address and a column address. The row address is the row address strobe ( ) Signal is transitioned from high to low, it is accepted into the semiconductor memory device, and the column address is transferred to the column address strobe ( ) Signal is transitioned from high to low, it is accepted into the semiconductor memory device.

The row address activates the word line by a decode circuit, and the column address activates the column select line. As described above, the memory cell is selected by the word line and the column selection line, and the BL / The signal level of the input / output line pair is placed on the input / output line pair, and the input / output line pair outputs the data to the outside via the sense amplifier. When writing data, the data on the input / output line pair is BL / And is stored in the cell capacitor.

A circuit diagram of a semiconductor memory device that performs this operation is schematically shown in Fig.

As shown in FIG. 1, a general semiconductor memory device includes a cell array unit 10 in which memory cells are arranged, a bit line sense amplifier 20 for sensing and amplifying data stored in the cell, The signal amplified by the amplifier is transferred to the input / output line pair, the data is received from the input / output line pair, and the BL / A column selection line driver 30 activated by a column address, and an input / output control unit 40 including input / output line pairs.

Here, the bit line sense amplifier 20 is driven by the internal power supply voltage V _INTA , and the column selection line CLS and the input / output control unit 40 are usually driven by the external power supply voltage V _EXT . 2, a deep or bump phenomenon occurs in which the bit line voltage read at the time of data reading is temporarily reduced or increased. This phenomenon occurs in the sense amplifier 20 ) Of the NMOS transistors 26 and 28 to lower the threshold voltage of the NMOS transistors 26 and 28 to increase the bit line sensing speed.

1 and 2, the BL / The BL dip and the Bump phenomenon will be briefly explained.

First, when the row address is input while the input / output line pairs are precharged to the power supply voltage level ( _Vcc ), the word line (W / L) is activated by the decoding circuit to select the cell transistor 12 , The PMOS and NMOS activation signals (PLAPG and PLANG) Is amplified. Thereafter, the column address is input to select the column selection line CSL, and the two NMOS transistors 32 and 34 in the column selection line driver 30 are activated and the BL / The read operation is completed when the data stored in the input / output line pair is loaded on the input / output line pair.

However, at this time, from the input / output line pair precharged to the power supply voltage level (V _CC ) (When high data is stored in BL) The voltage level of ( Bump). like this When the voltage level of the capacitor C is increased, The NMOS transistor 26 in the bit line sense amplifier 20 to which the gate is connected is turned on. Thereby, part of the charge of BL is transferred to the ground (V _SS ) by the two NMOS transistors 26 and 29, so that the voltage level of BL is reduced (BL dip). When the BL dip is generated, two PMOS transistors 22 and 24 in the bit line sense amplifier 20 must be operated to raise the voltage level of BL back to a high level, whereby the PMOS activation signal PLAPG and its The current of the internal power supply voltage (V _INTA ) is consumed through the PMOS transistor having the gate connected thereto.

The BL dip / If the data stored in the bump (BL) is low, the BL bump / As described above, an undesired current path is formed at the time of the lead-in operation of the semiconductor memory device to cause current consumption, which causes a decrease in the lead operation speed.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of driving a column selection line capable of reducing temporary bit line voltage drop (dip) or rise (bump) occurring during sensing data stored in a memory cell.

Another object of the present invention is to provide a column selection line driving signal control circuit suitable for the column selection line driving method.

Another object of the present invention is to provide a semiconductor memory device having the column select line drive signal control circuit.

1 is a schematic circuit diagram illustrating a data sensing method of a conventional semiconductor memory device.

Figure 2 is a block diagram of BL and < RTI ID = 0.0 > A graph showing a result of simulating a waveform using an HSPICE tool.

3 is a view for explaining a column select line driving voltage according to the present invention in read and write.

4 is a circuit diagram showing a semiconductor memory device having a column select line drive signal control circuit according to an embodiment of the present invention.

5 is a circuit diagram showing an example of the column select line drive signal control circuit shown in FIG.

Figure 6 is a block diagram of BL and < RTI ID = 0.0 > A graph showing a result of simulating a waveform using an HSPICE tool.

Column select line driving method according to the present invention for achieving the above object is, by using a drive signal of the read and write operation when column select line driver, otherwise, the driving by the internal supply voltage (V _INT) at the time of reading, the memory cell During sensing of the stored data, temporary bit line voltage drop (dip) or rise (bump) caused by the precharged power supply voltage on the input / output line pair is reduced and the external power voltage (V _EXT ) The data stored in the pair of input / output lines is quickly transferred to the bit line, thereby preventing a decrease in the write operation speed.

The internal power supply voltage (V _INTP ) used in the peripheral circuit part may be used as the internal power supply voltage (V _INT ) used at this time. By using different column select line driving signals applied in read and write, By controlling the gates of the transistors that make up the line driver, the voltage delivered from the input / output line pair to the bit line pair during read and write is controlled.

According to another aspect of the present invention, there is provided a column selection line driving signal control circuit for driving a column selection line in which a first voltage is outputted to a column selection line activated by a column address in response to a first signal inputted from the outside, (Or a source) connected to the column selection line and a source connected to the source of the first transistor and a drain connected to the column selection line, (Or a source) is connected to the column selection line, a second signal is input to the gate, a source (or drain) is connected to the second voltage, and a second transistor Respectively.

When the first signal and the second signal are signals in which the read and write commands are inverted, the first and second transistors comprise PMOS transistors. The first voltage may be an internal power supply voltage used in the peripheral circuit unit, and the second voltage may be an external power supply voltage.

According to another aspect of the present invention, there is provided a semiconductor memory device including: a cell array unit in which memory cells are arranged; a bit line sense amplifier for sensing and amplifying data stored in the memory cell; A column selection line driver which is activated by a column address and transfers the amplified signal to an input / output line pair or receives data from an input / output line pair and loads it on a bit line pair; And a column select line drive signal control circuit configured to output an internal supply voltage in response to a read command input from the outside and output an external supply voltage in response to a write command as a drive signal of the line driver.

Here, the column selection line driving signal control circuit may include a plurality of first PMOS transistors and second PMOS transistors connected in parallel. In this case, the first PMOS transistors are turned on by the inverted signal of the read command And a drain connected to the column select line, and the second PMOS transistors are connected to the inverted signal of the write command word (V _INTP ) ) As a gate input, a source connected to an external power supply voltage (V _EXT ), and a drain connected to a column select line.

By doing this, the BL / It is possible to reduce temporary voltage rise (bump) or voltage decrease (deep) phenomenon generally occurring in the conventional sensing, and to reduce the lead operation speed and unnecessary current consumption. Also, in the write operation, the data stored in the pair of input / output lines is rapidly BL / And the speed of the write operation can be prevented from being lowered

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings.

FIG. 3 is a diagram for explaining a driving voltage applied in driving the column selection line according to the present invention. In each of the conventional and the present invention, the column selection line driving voltage used in the read and write operations, And the driving voltage used in the input / output control unit are compared with each other.

As shown in FIG. 3, in the conventional case, one of the voltage sources, for example, the external power supply voltage V _EXT or the peripheral circuit internal power supply voltage V _INTP , However, in the case of the present invention, the column select line is driven by the internal supply voltage, for example, the internal supply voltage V _INTP supplied to the peripheral circuit during the read operation, and the external supply voltage V _EXT ).

4 is a circuit diagram for explaining a column select line driving method according to an embodiment of the present invention. In the case of DRAM, for example, memory cells composed of one transistor 52 and one capacitor 54 are arranged A bit line sense amplifier (60) for sensing and amplifying data stored in the memory cell, a sense amplifier (60) for sensing and amplifying the data stored in the memory cell, The bit-line sense amplifier 60 transfers the amplified signal to the input / output line pairs, receives the data from the input / output line pairs, and outputs the BL / A column selection line driver 70 activated by a column address, and an input / output control unit 80 including input / output line pairs.

The driving signal control circuit 100 for controlling the driving voltage supplied to the column selection line driver 70 is connected to the gate of the transistors 72 and 74 in the column selection line driver 70 . The column select line drive signal control circuit 100 may be configured to output the internal power supply voltage V _INTP or the external power supply voltage V _EXT in response to a read or write command.

3, the bit line sense amplifier 60 is a cell array internal power supply voltage V _INTA , and the input / output control unit 80 is connected to the external power supply is driven to a voltage (V _EXT), the column select line driver 70, a signal output from the column select line driving signal control circuit 100, for example, a read operation when there peripheral circuit inside the power source voltage (V _INTP ), And is driven by an external power supply voltage (V _EXT ) during a write operation.

Next, the operation principle of the present invention in which bit line bump or dip phenomenon, which has been a problem in the related art, is reduced by varying the driving voltage of the column selection line during the read operation and during the write operation will be described.

First, in the read operation, the separation signal PISO is activated so that the two transistors 56 and 58 connected thereto are turned on, and the input / output line pair is switched to the power supply voltage level _Vcc The word line W / L is activated by the decoding circuit, and the cell transistor 52 is selected. The BL voltage level is increased by charge sharing between the bit line BL and the cell capacitor 54, Voltage level. Next, the NMOS transistors 66 and 68 and the PMOS transistors 62 and 64 in the sense amplifier 60 are activated by the PMOS and NMOS activation signals (PLAPG and PLANG) And the higher voltage is sensed by the internal power supply voltage (V _INTA ).

Thereafter, the column address is input to select the column selection line CSL, and the first and second NMOS transistors 72 and 74 in the column selection line driver 70 are activated by the internal supply voltage V _INTP , BL and The read operation is completed.

At this time, as in the conventional case, when the first and second NMOS transistors 72 and 74 are activated, the input / output line pairs precharged to the power source voltage ( _Vcc ) level Cha Cha is transferred to So that the voltage level of the transistor Q1 increases. However, unlike the prior art in which the first and second NMOS transistors 72 and 74 are driven with the external power supply voltage V _EXT , since they are driven by the peripheral circuit internal power supply voltage V _INTP which is a lower voltage level, From the output line pair The signal level to be transmitted to the receiver becomes smaller than that of the conventional receiver, The bump is lower than the conventional one (see Fig. 6).

First When the voltage level of the capacitor C is increased, The NMOS transistor 66 in the bit line sense amplifier 60 whose gate is connected to the NMOS transistor 66 is turned on and the voltage level of BL is decreased as in the conventional case. However, As in the case of bumps, BL dip also occurs at a lower level than conventional, This is because the voltage level is lower than the conventional one (see Fig. 6).

As above Since the bump and the BL deep are generated at a lower level than the conventional one, the current consumption for raising the voltage level of the BL to the high level again is reduced and the speed reduction of the read operation can be reduced.

On the other hand, in the write operation, since the column select line driver is driven using the external supply voltage V _EXT output through the column select line drive signal control circuit 100, The data stored in the pair of input / output lines can be rapidly BL / . Therefore, the speed of the write operation can be prevented from lowering.

5 is a circuit diagram showing an example of the column select line drive signal control circuit 100 shown in FIG.

The column select line driving signal control circuit 100 according to an embodiment of the present invention may include a plurality of first PMOS transistors 102 and second PMOS transistors 104 connected in parallel. At this time, the plurality of first PMOS transistors 102 are turned on by the inverted signal of the read command word ) As a gate input, a source connected to the internal power supply voltage V _{INTP of the} peripheral circuit unit, and a drain connected to the column select line. The plurality of second PMOS transistors 104 may also include an inverted signal of the write command ( ) As a gate input, a source connected to an external power supply voltage (V _EXT ), and a drain connected to a column select line.

Accordingly, during the read operation, the first PMOS transistors 102 connected to the peripheral circuit internal power supply voltage V _INTP are turned on to supply the peripheral circuit internal power supply voltage V _INTP to the column select line, The second PMOS transistors 104 connected to the external power supply voltage V _EXT are turned on and the external power voltage V _EXT is supplied to the column select line.

FIG. 6 is a block diagram of a BL and a sense amplifier 5 shows a case of the present invention using a column selection line drive signal control circuit (see FIG. 5) as a graph showing a result of simulating a waveform using an HSPICE tool.

As shown in FIG. 6, when the column select line is driven by the peripheral circuit internal power supply voltage V _INTP of about 2.5 V through the column select line drive signal control circuit according to the present invention, Compared with the conventional case, It can be seen that the bump appears at a much smaller level.

As described above, the semiconductor memory device according to the present invention further comprises a column select line drive signal control circuit, through which the column select line is driven by the external supply voltage during a write operation, and the external supply voltage And is driven by an internal supply voltage of a lower level. By doing this, the BL / It is possible to reduce temporary voltage rise (bump) or voltage decrease (deep) phenomenon that has conventionally occurred at the time of sensing. Therefore, it is possible to reduce the read operation speed and reduce unnecessary current consumption. In the write operation, the column select line is driven by the external power supply voltage, and the data stored in the pair of input / output lines is quickly BL / . Therefore, it is possible to prevent the speed of the write operation from being lowered

Claims (9)

A column select line driver that is stored in the memory cell and transfers the data sensed and amplified by the bit line sense amplifier to the input / output line pair or receives the data from the input / output line pair and loads it on the bit line In a method of driving, The drive signal of the column select line driver is made different during read and write and is generated by the supply voltage precharged to the input / output line pair while sensing the data stored in the memory cell at the time of read (V _INT ) so as to reduce temporary bit line voltage drop (dip) or rise (bump), and data written in the input / output line pair is quickly transferred to the bit line (V _EXT ) so as to prevent the operation speed from being lowered. The method of claim 1, wherein the internal supply voltage (V _INT ) is an internal supply voltage (V _INTP ) used in a peripheral circuit. 2. The semiconductor memory device according to claim 1, wherein the gates of the transistors constituting the column select line driver are controlled by using different column select line drive signals applied at the time of read and write, Wherein a voltage to be applied to the column selection line is controlled by controlling the voltage supplied to the column selection line. A first signal is input to the gate, a first voltage is connected to the source (or drain), and a drain is connected to the drain of the first transistor, (Or a source) connected to the column selection line; And A second signal is input to the gate so that a second voltage is output to the column selection line in response to a second signal input from the outside, the source (or drain) is connected to the second voltage, and the drain And a plurality of second transistors connected to the column selection line. 5. The column select line driving signal control circuit according to claim 4, wherein the first signal and the second signal are signals in which the read and write commands are inverted, and the first and second transistors are PMOS transistors. The column select line driving signal control circuit according to claim 5, wherein the first voltage uses an internal power supply voltage (V _INTP ) used in a peripheral circuit unit and the second voltage uses an external power supply voltage (V _EXT ) . A cell array section in which memory cells are arranged; A bit line sense amplifier configured to sense and amplify data stored in the memory cell; A bit line sense amplifier for receiving a signal amplified by the bit line sense amplifier as a pair of input and output lines or receiving data from a pair of input and output lines and driving the bit line sense amplifier on a pair of bit lines, ; And And a column select line drive signal control circuit configured to output an internal supply voltage in response to a read command input from the outside and output an external supply voltage in response to a write command as a drive signal of the column select line driver . 8. The semiconductor memory device according to claim 7, wherein the column selection line drive signal control circuit comprises: A plurality of first PMOS transistors and second PMOS transistors connected in parallel, The first PMOS transistors are connected to the inverted signal of the read command ) As a gate input, a source connected to an internal power supply voltage V _{INTP of a} peripheral circuit unit, a drain connected to a column select line, The second PMOS transistors are connected to the inverted signal of the write command ) As a gate input, a source connected to an external power supply voltage (V _EXT ), and a drain connected to a column select line. 8. The semiconductor memory device of claim 7, wherein the bit line sense amplifier is driven by an internal power supply voltage of the cell array unit.