KR19990010623A - Word line control circuit - Google Patents

Abstract

The present invention relates to a word line control circuit, and the related art uses a large number of delay stages in timing between the word line enable signals WLEN0B and WLEN1B and the signal RDPRI for enabling the word line decoder. Unnecessarily, the design area becomes large, there is a difficulty in controlling accurate timing, and there is a problem in that an unwanted leakage current is generated during word line activation because the timing between the two signals cannot be adjusted.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and provides a circuit that eliminates unnecessary delay stages and directly controls a word line enable signal with a word line control signal, thereby providing a design area. This reduces and controls the enable and disable of the word line with accurate timing, thereby preventing leakage current during word line activation.

Description

Word line control circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to word line control circuits, and in particular, in memory, by eliminating unnecessary delay stages, the design area is reduced, enabling and disabling word lines with accurate timing. It relates to a word line control circuit for controlling (Disable).

FIG. 1 is a block diagram showing the structure of a conventional word line control circuit. As shown in FIG. 1, the signals PX0 and PX1 pre-decoded by receiving the least significant bit MSB of a row address and the bit line are equalized. A word line enable control unit (10) for controlling to select a final word line by a signal (BEQENJB) for disabling a later word line enable signal; A signal for enabling a word line decoder by a normal word line enable control signal RDENI for controlling whether the path is a normal path or a redundant path, and a redundant word line enable control signal RWLDENI and RWLDENK and a block coding signal PX1819F. Word line drive (RDPRI), a signal (WPCHB) for disabling word lines directly, a signal (RWPCHB) for disabling duplicate word lines, and a signal (RWLEN0, RWLEN1) for disabling duplicate word lines. A control unit 20; A normal path word line drive 30 which charges or discharges a word line to a peak voltage (Vpp: + 5V) level by a signal output from the word line enable control unit 10 and the word line drive control unit 20. And a redundant path word line drive 40.

FIG. 2 is a circuit diagram illustrating the configuration of the word line enable controller in FIG. 1, wherein one of the signals PX0 and PX1 pre-decoded by receiving the least significant bit of the row address when the word line is active is active high; When the signal BEQENJB is input low after equalizing the bit line and disabling the word line enable signal, the output of one of the NAND gates NG1 and NG2 is low. The low signal is a signal WLEN0B which enables the final word line via the NAND gates NG3 and NG4 of the inverter delay stages 11 and 12 and the selection delay stages 13 and 14. One of WLEN1B) is output as active low, and this signal WLEN0B (WLEN1B) is input to the normal / redundant wordline drives 30 and 40 to control the selection of the final wordline. At this time, the selection delay stages 13 and 14 do not generate a delay when the signals of 'node a' and 'node b' fall, but only when rising. That is, when 'node a' which is one input of NAND gate NG3 is low, only one gate delay occurs because high is output regardless of the other input, but 'node a which is one input terminal of NAND gate NG3'. When 'high' changes the output according to the other input terminal of the NAND gate NG3, 'node c' becomes low when it goes high through the inverter.

FIG. 3 is a circuit diagram showing the configuration of the word line drive controller in FIG. 1, as shown in FIG. 1, a normal word line enable control signal RDENI for controlling a normal path and a redundant word line enable control signal for controlling a redundant path. When (RWLDENI) (RWLDENK) is input and the normal path word line is active, the normal word line enable control signal RDENI is high and the redundant word line enable control signals RWLDENI, RWLDENK are low. When the block coding signal PX1819F is set to high, the output signal RDPRI WPCHB is input to the word line drive in a high state to control charging of the word line, and vice versa. When the PX1819F goes low, the output signal RDPRI WPCHB goes low to control the discharge of the word line. At this time, the signal (WPCHB) for directly disabling the word line and the signal (RWPCHB) for disabling the redundant word line go through the level shifter 21. If it is high, the peak voltage (Vpp: + 5V) level value Will have

FIG. 4 is a conventional word line control timing diagram. As shown therein, the delay values at the falling and rising times are varied by the inverter delay stages 11 and 12 and the selective delay stages 13 and 14. to be.

FIG. 5 is a circuit diagram showing the structure of a conventional word line drive. As shown therein, a signal of node g is made active high by a signal WRDPRI outputted from a word line control circuit, and then the word line is disabled. When the signal WPCHB goes high, when the node h goes low by the signal WLEN0B or WLEN1B, the N-MOS transistor NM20 is turned off. The MOS transistor PM13 is turned on to activate the word line WL (0) to a peak voltage (+ 5V) level.

At this time, after the signal WRDPRI output from the word line control circuit becomes high, the signal WWLHB for disabling the word line becomes high and the signal WLEN0B or WLEN1B for enabling the word line goes low. When activated, the signal is shorted with the signal WLEN0B or WLEN1B for enabling the word line WL (0) applied to the node h to generate a leakage current.

As described above, the conventional technique uses many delay stages to adjust the timing between the word line enable signal WLEN0B and WLEN1B and the signal RDPRI for enabling the word line decoder. In addition, there is a difficulty in controlling accurate timing, and there is a problem in that unwanted timing can be generated when the word line is active due to inaccurate timing between the two signals.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and provides a circuit that eliminates unnecessary delay stages and directly controls a word line enable signal with a word line control signal, thereby providing a design area. This reduces and controls the enable and disable of the word line with accurate timing, thereby preventing leakage current during word line activation.

1 is a block diagram showing the configuration of a conventional word line control circuit.

FIG. 2 is a circuit diagram showing the configuration of the word line enable control in FIG.

FIG. 3 is a circuit diagram showing the configuration of the word line drive controller in FIG.

4 is a conventional word line control timing diagram.

5 is a circuit diagram showing a configuration of a conventional word line drive.

Figure 6 is a circuit diagram showing the configuration of the word line control circuit of the present invention.

7 is a word line control timing diagram of the present invention.

Explanation of symbols for the main parts of the drawings

10, 50: word line enable control unit 20, 60: word line drive control unit

30: normal wordline drive 40: redundant path wordline drive

21: level shifter 51: latch portion

11, 12: inverter delay stage 13, 14: optional delay stage

I1 to I: Inverter NM1 to NM21: N-MOS transistor

NG1-NG10: NAND gate PM1-PM16: P-MOS transistor

AG1, AG2: Noah gate TG1, TG2: Transmission gate

The word line control circuit of the present invention for achieving the above object, the normal path enable signal, the redundant path enable signal and the block coded signal is input to control the word line drive to the normal or redundant path of the word line A word line drive control unit configured to control charging and discharging of the power supply and to generate a timing signal based on the normal path enable signal or the redundant path enable signal; The final word line is selected by receiving the least significant bit of the row address and latching the predecoded signal by equalizing the bit line and then disabling the word line enable signal and the timing signal output from the word line drive controller. Characterized in that it comprises a word line enable control unit for controlling.

The word line enable controller receives the least significant bit of the row address inverted by the first and second inverters, equalizes the pre-decoded signal to the one input terminal of the first NAND gate, and then applies the word line enable signal. And a latch unit configured to latch by a signal for disabling and a timing signal input to the other input terminal.

The word line drive controller may include: a second NAND gate configured to receive a word line enable control signal and a block coding signal by NAND-combining the output signal; Third and fourth NAND gates configured to receive NAND combinations of the redundant word line enable control signal and the block coding signal and output the result; A fifth NAND gate that receives the outputs of the third and fourth NAND gates and outputs the NAND combinations; A level shifter for shifting the output of the second NAND gate and the fifth NAND gate to a peak voltage level; And a sixth NAND gate configured to NAND-combine the outputs of the second NAND gate and the fifth NAND gate to output a timing signal to a word line enable controller.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 6 is a circuit diagram showing the structure of the word line control circuit of the present invention. As shown in FIG. A signal BEQENJB for equalizing the bit line input to one input terminal of the first NAND gate NG9 and disabling the word line enable signal, and a timing signal input to the other input terminal (PX1) and PX2. a latch portion 51 latched by ctr1; A second NAND gate NG4 that receives the normal word line enable control signal RDENI and the block coding signal PX1819F, and outputs the result of NAND combining; Third and fourth NAND gates NG5 and NG6 configured to receive a NAND combination of the redundant word line enable control signal RWLDENI and the block coded signal PX1819F, and output the result in NAND combination; A fifth NAND gate NG10 for receiving the outputs of the third and fourth NAND gates NG5 and NG6 and outputting the result of NAND combining; A level shifter (21) for shifting the outputs of the second NAND gate (NG4) and the fifth NAND gate (NG9) to a peak voltage (+ 5V) level; And a sixth NAND gate NG8 for NAND combining the outputs of the second NAND gate NG4 and the fifth NAND gate NG10 and outputting a timing signal ctr1 to the word line enable control unit 50. .

FIG. 7 is a timing diagram of the word line control according to the present invention. As shown in the drawing, the word line enable control unit 50 equalizes the bit line when the word line is active, and then disables the word line enable signal BEQENJB. Is activated on the bus BUS, the word line drive control unit 60 controls the signal of 'node d' controlled by the normal path word line enable signal RDENI and the block coding signal PX1819F, and the redundant path word line in. One of a signal of the node e, which is controlled by the enable signal RWLDENI and the block coding signal PX1819F, goes low, and the timing signal ctr1 that is the output of the sixth NAND gate NG8 is When the signal ctr1 is input to the first NAND gate NG10 of the word line enable controller 50, the latch unit 51 latches the address decoding signals PX1 and PX2. Word by this latched signal In which selects one of the enable signal (WLEN0B, WLEN1B).

That is, in selecting one of the word line enable signals WLEN0B and WLEN1B, a normal path or a redundant path word line enable signal is not dependent on only the selection delay terminals 13 and 14 as shown in FIG. One of the word line enable signals WLEN0B and WLEN1B is selected and controlled by a timing signal ctr1 controlled by (RDENI or RWLDENI, RWLDENK) and the block coding signal PX1819F.

Accordingly, the word line enable signals WLEN0B and WLEN1B are dependent on the word line drive controller 60.

The signal WRDPRI output from the word line control circuit activates the 'node g' signal high in FIG. 5, followed by the word line immediately following the timing when the signal WPCHB that disables the word line becomes high. Enable signal WLEN0B or WLEN1B to be low, so node h is low, which causes the N-MOS transistor NM20 to be turned off and the P-MOS transistor PM13. Is turned on to activate the word line to a peak voltage (+ 5V) level.

As described above, the word line control circuit of the present invention reduces the design area by eliminating unnecessary delay stages, and controls the enable and disable of the word line at the exact timing of the control signal to activate the word line. It is effective in preventing leakage current.

Claims (3)

Controls a word line drive by receiving a normal path enable signal, a redundant path enable signal, and a block coding signal to control charging and discharging of a word line of a normal path or a redundant path, and the normal path enable signal or a redundant path. A word line drive controller configured to generate a timing signal by the enable signal; The final word line is selected by receiving the least significant bit of the row address and latching the predecoded signal by equalizing the bit line and then disabling the word line enable signal and the timing signal output from the word line drive controller. And a word line enable control unit for controlling the control unit. The word line driver control unit of claim 1, further comprising: a second NAND gate configured to receive a word line enable control signal and a block coding signal by NAND; Third and fourth NAND gates configured to receive NAND combinations of the redundant word line enable control signal and the block coding signal and output the result; A fifth NAND gate that receives the outputs of the third and fourth NAND gates and outputs the NAND combinations; A level shifter for shifting the output of the second NAND gate and the fifth NAND gate to a peak voltage level; And a sixth NAND gate configured to NAND-combine the outputs of the second NAND gate and the fifth NAND gate to output a timing signal to a word line enable controller. The word line enable control unit of claim 1, wherein the word line enable control unit equalizes a bit line receiving the least significant bit of the row address inverted by the first and second inverters and inputs a pre-decoded signal to one input terminal of the first NAND gate. And a latch unit configured to latch by a signal for disabling the word line enable signal and a timing signal input to the other input terminal.