KR19990008826A - Semiconductor memory - Google Patents

Semiconductor memory Download PDF

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Publication number
KR19990008826A
KR19990008826A KR1019970030965A KR19970030965A KR19990008826A KR 19990008826 A KR19990008826 A KR 19990008826A KR 1019970030965 A KR1019970030965 A KR 1019970030965A KR 19970030965 A KR19970030965 A KR 19970030965A KR 19990008826 A KR19990008826 A KR 19990008826A
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South Korea
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memory cell
insulating layer
field oxide
oxide film
cell portion
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KR1019970030965A
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Korean (ko)
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연은숙
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문정환
엘지반도체 주식회사
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Priority to KR1019970030965A priority Critical patent/KR19990008826A/en
Publication of KR19990008826A publication Critical patent/KR19990008826A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체 메모리에 관한 것으로, 종래의 반도체 메모리는 다수의 셀을 동일한 평면상에 구성함으로써, 집적도가 감소하는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 기판(1)에 형성한 트랜치구조 내에 위치하는 CUB구조의 제 1메모리셀부(MC1)와; 그 제 1메모리셀부(MC1)의 절연층(4) 상부에 형성한 상부 기판(1')에 위치하는 CUB구조의 제 2메모리셀부(MC2)와; 상기 제 2메모리셀부(MC2)의 절연을 위한 필드산화막(2') 및 절연층(4')과; 일측이 상기 제 1메모리셀부(MC1)의 게이트(G1)에 접속되고, 제 1메모리셀부(MC1)의 절연층(4)과, 상기 상부 기판(1') 및 필드산화막(2')을 통해 그 타측이 절연층(4')의 중간에 위치하는 전극(3)과; 제 1메모리셀부(MC1)의 금속전극(ML1)에 일측이 접속되고 상기 상부기판(1'), 필드산화막(2') 및 절연층(4')을 통해 그 타측이 외부에 노출된 금속전극(ML2)으로 집적도를 향상시키는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and the conventional semiconductor memory has a problem that the degree of integration is reduced by configuring a plurality of cells on the same plane. In view of the above problems, the present invention includes a first memory cell portion MC1 having a CUB structure located in a trench structure formed in the substrate 1; A second memory cell portion MC2 having a CUB structure located on the upper substrate 1 'formed over the insulating layer 4 of the first memory cell portion MC1; A field oxide film 2 'and an insulating layer 4' for insulating the second memory cell portion MC2; One side is connected to the gate G1 of the first memory cell unit MC1, and is formed through the insulating layer 4 of the first memory cell unit MC1, the upper substrate 1 ′, and the field oxide layer 2 ′. An electrode 3 whose other side is located in the middle of the insulating layer 4 '; A metal electrode having one side connected to the metal electrode ML1 of the first memory cell unit MC1 and the other side exposed to the outside through the upper substrate 1 ', the field oxide film 2', and the insulating layer 4 '. ML2 has the effect of improving the degree of integration.

Description

반도체 메모리Semiconductor memory

본 발명은 반도체 메모리에 관한 것으로, 특히 메모리셀의 구조를 적층구조로하여 집적도를 향상시키는데 적당하도록 한 반도체 메모리에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory having a structure in which a memory cell is stacked in order to improve the degree of integration.

일반적으로, 반도체 메모리의 메모리셀은 모스 트랜지스터의 소스에 접속되는 캐패시터와 그 드레인에 접속되는 전극을 포함하여 이루어지며, 그 드레인에 접속되는 전극이 비트라인으로 사용되어 그 비트라인에 인가되는 신호와 모스 트랜지스터의 도통상태에 따라 데이터를 캐패시터에 저장 또는 캐패시터에 저장된 데이터를 비트라인을 통해 출력하는 동작을 한다. 또한, 캐패시터의 위치에 따라 캐패시터가 비트라인보다 낮은 위치에 형성된 메모리셀을 CUB(CAPACITER UNDER BITLINE)구조라고 하고, 캐패시터가 비트라인보다 높은 위치에 형성된 메모리셀을 COB(CAPACITER OVER BITLINE)구조라고 한다. 종래의 반도체 메모리는 동일 평면상에 상기 CUB 또는 COB구조의 메모리셀을 형성하였으며, 이와 같은 종래 반도체 메모리를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, a memory cell of a semiconductor memory includes a capacitor connected to a source of a MOS transistor and an electrode connected to a drain thereof, and an electrode connected to the drain thereof is used as a bit line to apply a signal applied to the bit line. The data is stored in the capacitor or the data stored in the capacitor is output through the bit line according to the conduction state of the MOS transistor. In addition, a memory cell formed at a position lower than the bit line according to the position of the capacitor is called a CUB (CAPACITER UNDER BITLINE) structure, and a memory cell formed at a position higher than the bit line is called a COB (CAPACITER OVER BITLINE) structure. . Conventional semiconductor memories have formed memory cells having the CUB or COB structure on the same plane, and will be described in detail with reference to the accompanying drawings.

도1은 종래 CUB구조 반도체 메모리의 단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 형성된 필드산화막(2)에 의해 각각 분리되는 두 메모리셀부(MC1),(MC2)로 구성되며, 각각의 메모리셀부(MC1),(MC2)는 게이트(G)와 소스(S) 및 드레인(D)을 포함하는 엔모스 트랜지스터와, 그 엔모스 트랜지스터의 소스(S)측에 접속된 캐패시터(C)와; 상기 엔모스 트랜지스터에 외부의 신호를 인가하는 금속전극(ML)과; 상기 엔모스 트랜지스터, 캐패시터(C), 금속전극(ML)을 절연하는 절연층(4)으로 구성된다.FIG. 1 is a cross-sectional view of a conventional CUB structure semiconductor memory. As shown in FIG. 1, two memory cell portions MC1 and MC2 are respectively separated by a field oxide film 2 formed on an upper portion of a substrate 1, respectively. The memory cell portions MC1 and MC2 of the NMOS transistors include an NMOS transistor including a gate G, a source S, and a drain D, and a capacitor C connected to the source S side of the NMOS transistor. Wow; A metal electrode ML for applying an external signal to the NMOS transistor; The insulating layer 4 insulates the NMOS transistor, the capacitor C, and the metal electrode ML.

또한, 도2는 종래 COB구조 메모리셀의 단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 증착된 필드산화막(2)에 의해 분리되는 메모리셀부(MC1),(MC2)로 구성되며, 각 메모리셀부(MC1),(MC2)는 게이트(G)와 소스(S) 및 드레인(D)을 포함하는 엔모스 트랜지스터와, 상기 엔모스 트랜지스터의 드레인(D)에 접속되어 외부의 신호를 인가받는 다결정실리콘전극(PL)과; 상기 엔모스 트랜지스터의 소스(S)에 접속된 캐패시터(C)와; 상기 엔모스 트랜지스터, 캐패시터(C) 및 다결정실리콘전극(PL)을 절연하는 절연층(4)으로 구성된다.2 is a cross-sectional view of a conventional COB structure memory cell, which is composed of memory cell portions MC1 and MC2 separated by a field oxide film 2 deposited on an upper portion of a substrate 1, as shown in FIG. Each of the memory cell units MC1 and MC2 is connected to an NMOS transistor including a gate G, a source S, and a drain D, and is connected to the drain D of the NMOS transistor to apply an external signal. A receiving polycrystalline silicon electrode PL; A capacitor C connected to the source S of the NMOS transistor; The insulating layer 4 is insulated from the NMOS transistor, the capacitor C, and the polysilicon electrode PL.

이때, 상기 캐패시터(C)는 다결정실리콘전극(PL)보다 높은 위치에 형성되며, 반도체 메모리는 상기와 같은 반도체 메모리셀을 다수개 포함하여 구성된다.In this case, the capacitor C is formed at a position higher than the polysilicon electrode PL, and the semiconductor memory includes a plurality of semiconductor memory cells as described above.

이하, 상기와 같이 구성되는 종래 메모리셀의 동작을 설명한다.Hereinafter, the operation of the conventional memory cell configured as described above will be described.

먼저, COB구조 메모리셀과 CUB구조 메모리셀에 포함된 엔모스 트랜지스터의 게이트(G)에 소정의 전압이 인가되어 그 엔모스 트랜지스터를 도통시킨다. 상기 엔모스 트랜지스터의 게이트는 반도체 메모리의 워드라인으로 사용되며, 그 워드라인에 인가되는 워드라인선택신호에 따라 각 메모리셀이 선택된다.First, a predetermined voltage is applied to the gate G of the NMOS transistor included in the COB structure memory cell and the CUB structure memory cell to conduct the NMOS transistor. The gate of the NMOS transistor is used as a word line of a semiconductor memory, and each memory cell is selected according to a word line selection signal applied to the word line.

그 다음, 상기 COB구조 메모리셀과 CUB구조 메모리셀에 포함된 금속전극(ML)과 다결정실리콘전극(PL), 즉 비트라인의 상태에 따라 각 캐패시터(C)에 신호가 충전 또는 방전되고, 이는 전체적으로 데이터의 저장 또는 읽기동작으로 표현된다.Then, a signal is charged or discharged to each capacitor C according to the state of the metal electrode ML and the polysilicon electrode PL, that is, the bit line included in the COB structure memory cell and the CUB structure memory cell. It is expressed as the operation of storing or reading data as a whole.

그러나, 상기와 같은 종래 반도체 메모리는 동일 평면상에 각 메모리셀들을 형성하여 메모리셀의 수가 증가할수록 반도체 메모리의 크기가 커져 집적도가 감소하는 문제점이 있었다.However, in the conventional semiconductor memory as described above, each memory cell is formed on the same plane, and as the number of memory cells increases, the size of the semiconductor memory increases, thereby reducing the degree of integration.

이와 같은 문제점을 감안한 본 발명은 집적도를 향상시킨 반도체 메모리의 제공에 그 목적이 있다.In view of the above problems, the present invention has an object to provide a semiconductor memory having improved integration.

도1은 종래 CUB구조 메모리셀의 단면도.1 is a cross-sectional view of a conventional CUB structure memory cell.

도2는 종래 COB구조 메모리셀의 단면도.2 is a cross-sectional view of a conventional COB structure memory cell.

도3은 본 발명에 의한 CUB구조 메모리셀의 단면도.3 is a cross-sectional view of a CUB structure memory cell according to the present invention.

도4는 본 발명에 의한 COB구조 메모리셀의 단면도.4 is a cross-sectional view of a COB structure memory cell according to the present invention.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

1,1':기판 2,2':필드산화막1,1 ': substrate 2,2': field oxide film

3:전극 4,4':절연층3: electrode 4,4 ': insulating layer

상기와 같은 목적은 기판에 트랜치구조를 형성하고, 그 트랜치구조 내에 제 1메모리셀부를 형성하며, 그 제 1메모리셀부의 상부에 다시 실리콘을 성장시킨 후, 그 성장된 실리콘의 상부에 제 2메모리셀부를 구성하는 적층구조로 메모리셀을 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The purpose is to form a trench structure in a substrate, to form a first memory cell portion in the trench structure, to grow silicon on top of the first memory cell portion, and then to a second memory on top of the grown silicon. It is achieved by configuring a memory cell in a stacked structure constituting the cell portion, described in detail with reference to the accompanying drawings, the present invention as follows.

도3은 본 발명에 의한 CUB구조 반도체 메모리셀의 단면도로서, 이에 도시한 바와 같이 메모리셀의 기본적인 구성은 종래와 동일하며, 기판(1)에 형성한 트랜치구조 내에 위치하는 제 1메모리셀부(MC1)와, 그 제 1메모리셀부(MC1)의 절연층(4) 상부에 형성한 상부 기판(1')에 위치하는 제 2메모리셀부(MC2)와, 상기 제 2메모리셀부(MC2)의 절연을 위한 필드산화막(2') 및 절연층(4')과; 일측이 상기 제 1메모리셀부(MC1)의 게이트(G1)에 접속되고, 제 1메모리셀부(MC1)의 절연층(4)과, 상기 상부 기판(1') 및 필드산화막(2')을 통해 그 타측이 절연층(4')의 중간에 위치하는 전극(3)과; 제 1메모리셀부(MC1)의 금속전극(ML1)에 일측이 접속되고 상기 상부기판(1'), 필드산화막(2') 및 절연층(4')을 통해 그 타측이 외부에 노출된 금속전극(ML2)으로 구성된다.FIG. 3 is a cross-sectional view of a CUB structure semiconductor memory cell according to the present invention. As shown in FIG. 3, the basic structure of the memory cell is the same as that of the related art, and the first memory cell portion MC1 positioned in the trench structure formed on the substrate 1 is shown. ), Insulation between the second memory cell portion MC2 and the second memory cell portion MC2 positioned on the upper substrate 1 'formed on the insulating layer 4 of the first memory cell portion MC1. A field oxide film 2 'and an insulating layer 4' for insulating; One side is connected to the gate G1 of the first memory cell unit MC1, and is formed through the insulating layer 4 of the first memory cell unit MC1, the upper substrate 1 ′, and the field oxide layer 2 ′. An electrode 3 whose other side is located in the middle of the insulating layer 4 '; A metal electrode having one side connected to the metal electrode ML1 of the first memory cell unit MC1 and the other side exposed to the outside through the upper substrate 1 ', the field oxide film 2', and the insulating layer 4 '. It consists of (ML2).

또한, 도4는 본 발명에 의한 COB구조 반도체 메모리셀의 단면도로서, 이에 도시한 바와 같이 기판(1)에 형성한 트랜치구조 내에 위치하는 제 1메모리셀부(MC1)와; 그 제 1메모리셀부(MC1)의 절연층(4) 상부에 형성한 상부 기판(1')에 위치하는 제 2메모리셀부(MC2)와; 상기 제 2메모리셀부(MC2)의 절연을 위해 형성한 필드산화막(2') 및 절연층(4')과; 상기 제 1메모리셀부(MC1)의 게이트(G1)에 일측이 접속되며 제 1메모리셀부(MC1)의 절연층(4)과 필드산화막(2') 및 절연층(4')를 통해 외부에 노출된 금속전극(ML2)과; 일측이 상기 제 1메모리셀부(MC1)의 다결정실리콘전극(PL1)의 상부에 접속되며, 절연층(4)과, 상부 기판(1'), 필드산화막(2')를 통해 상기 절연층(4')의 중앙에 위치하는 전극(3)으로 구성된다.4 is a cross-sectional view of a COB structure semiconductor memory cell according to the present invention, and as shown therein, a first memory cell portion MC1 located in a trench structure formed in the substrate 1; A second memory cell portion MC2 positioned on the upper substrate 1 'formed over the insulating layer 4 of the first memory cell portion MC1; A field oxide film 2 'and an insulating layer 4' formed to insulate the second memory cell portion MC2; One side is connected to the gate G1 of the first memory cell unit MC1 and exposed to the outside through the insulating layer 4, the field oxide film 2 ′, and the insulating layer 4 ′ of the first memory cell unit MC1. A metal electrode ML2; One side is connected to the upper portion of the polysilicon electrode PL1 of the first memory cell unit MC1, and the insulating layer 4 is formed through the insulating layer 4, the upper substrate 1 ′, and the field oxide film 2 ′. It consists of an electrode 3 located at the center of ').

이하, 상기와 같이 구성된 본 발명 반도체 메모리의 CUB구조 메모리셀 동작을 설명한다.Hereinafter, the CUB structure memory cell operation of the semiconductor memory of the present invention configured as described above will be described.

먼저, 각 메모리셀부(MC1),(MC2)의 게이트(G1),(G2)에 워드라인신호를 인가한다. 이때 하부에 위치하는 제 1메모리셀부(MC1)의 게이트(G1)에는 전극(3)을 통해 워드라인 신호를 인가한다.First, a word line signal is applied to the gates G1 and G2 of the memory cell units MC1 and MC2. In this case, a word line signal is applied to the gate G1 of the first memory cell unit MC1 disposed below the electrode 3 through the electrode 3.

그 다음, 각 메모리셀부(MC1),(MC2)의 비트라인인 금속전극(ML2),(ML3)의 상태에 따라 캐패시터(C1),(C2)에 데이터가 저장 또는 저장된 데이터가 출력된다. 이때, 제 1메모리셀부(MC1)의 비트라인은 금속전극(ML1),(ML3)이며, 이를 통해 데이터가 출력또는 입력된다.Then, data is stored or stored in the capacitors C1 and C2 according to the states of the metal electrodes ML2 and ML3 which are bit lines of the memory cell units MC1 and MC2. In this case, the bit lines of the first memory cell unit MC1 are metal electrodes ML1 and ML3, and data is output or input through the bit lines.

그리고, COB구조 메모리셀의 동작은 각 메모리셀부(MC1),(MC2)의 게이트(G1),(G2)에 워드라인신호를 인가하여 동작시킬 메모리셀부를 선택한다. 이때, 제 1메모리셀부(MC1)의 게이트(G1)에는 금속전극(ML2)를 통해 워드라인신호가 인가된다.The operation of the COB structure memory cell selects the memory cell unit to be operated by applying a word line signal to the gates G1 and G2 of the memory cell units MC1 and MC2. In this case, a word line signal is applied to the gate G1 of the first memory cell unit MC1 through the metal electrode ML2.

그 다음, 각 메모리셀부(MC1),(MC2)의 비트라인인 다결정실리콘전극(PL1),(PL2)의 상태에 따라 각 캐패시터(C1),(C2)에 데이터가 저장되거나, 저장된 데이터가 다결정실리콘전극(PL1),(PL2)을 통해 출력된다. 이때, 제 1메모리셀부(MC1)의 데이터는 다결정실리콘전극(PL1)과 전극(3)을 통해 입출력된다.Then, data is stored in each of the capacitors C1 and C2 or the stored data is polycrystalline depending on the states of the polysilicon electrodes PL1 and PL2 which are bit lines of the memory cell units MC1 and MC2. It is output through the silicon electrodes PL1 and PL2. In this case, data of the first memory cell unit MC1 is input / output through the polysilicon electrode PL1 and the electrode 3.

상기한 바와 같이 본 발명 반도체 메모리는 그 메모리셀을 적층구조로 형성하여 집적도를 향상시키는 효과가 있다.As described above, the semiconductor memory of the present invention has the effect of improving the degree of integration by forming the memory cells in a stacked structure.

Claims (2)

기판(1)에 형성한 트랜치구조 내에 위치하는 CUB구조의 제 1메모리셀부(MC1)와; 그 제 1메모리셀부(MC1)의 절연층(4) 상부에 형성한 상부 기판(1')에 위치하는 CUB구조의 제 2메모리셀부(MC2)와; 상기 제 2메모리셀부(MC2)의 절연을 위한 필드산화막(2') 및 절연층(4')과; 일측이 상기 제 1메모리셀부(MC1)의 게이트(G1)에 접속되고, 제 1메모리셀부(MC1)의 절연층(4)과 상기 상부 기판(1') 및 필드산화막(2')을 통해 그 타측이 절연층(4')의 중간에 위치하는 전극(3)과; 제 1메모리셀부(MC1)의 금속전극(ML1)에 일측이 접속되고 상기 상부기판(1'), 필드산화막(2') 및 절연층(4')을 통해 그 타측이 외부에 노출된 금속전극(ML2)으로 구성된 메모리셀을 다수개 포함하여 된 것을 특징으로 하는 반도체 메모리.A first memory cell portion MC1 having a CUB structure located in the trench structure formed in the substrate 1; A second memory cell portion MC2 having a CUB structure located on the upper substrate 1 'formed over the insulating layer 4 of the first memory cell portion MC1; A field oxide film 2 'and an insulating layer 4' for insulating the second memory cell portion MC2; One side is connected to the gate G1 of the first memory cell unit MC1, and is connected to the insulating layer 4 of the first memory cell unit MC1 through the upper substrate 1 ′ and the field oxide film 2 ′. An electrode 3 whose other side is positioned in the middle of the insulating layer 4 '; A metal electrode having one side connected to the metal electrode ML1 of the first memory cell unit MC1 and the other side exposed to the outside through the upper substrate 1 ', the field oxide film 2', and the insulating layer 4 '. And a plurality of memory cells composed of ML2. 기판(1)에 형성한 트랜치구조 내에 위치하는 COB구조의 제 1메모리셀부(MC1)와; 그 제 1메모리셀부(MC1)의 절연층(4) 상부에 형성한 상부 기판(1')에 위치하는 COB구조의 제 2메모리셀부(MC2)와; 상기 제 2메모리셀부(MC2)의 절연을 위해 형성한 필드산화막(2') 및 절연층(4')과; 상기 제 1메모리셀부(MC1)의 게이트(G1)에 일측이 접속되며 제 1메모리셀부(MC1)의 절연층(4)과 필드산화막(2') 및 절연층(4')를 통해 외부에 노출된 금속전극(ML2)과; 일측이 상기 제 1메모리셀부(MC1)의 다결정실리콘전극(PL1)의 상부에 접속되며, 절연층(4)과, 상부 기판(1'), 필드산화막(2')를 통해 상기 절연층(4')의 중앙에 위치하는 전극(3)으로 구성되는 메모리셀을 다수개 포함하여 된 것을 특징으로 하는 반도체 메모리.A first memory cell portion MC1 having a COB structure located in a trench structure formed in the substrate 1; A second memory cell portion MC2 having a COB structure located on the upper substrate 1 'formed over the insulating layer 4 of the first memory cell portion MC1; A field oxide film 2 'and an insulating layer 4' formed to insulate the second memory cell portion MC2; One side is connected to the gate G1 of the first memory cell unit MC1 and exposed to the outside through the insulating layer 4, the field oxide film 2 ′, and the insulating layer 4 ′ of the first memory cell unit MC1. A metal electrode ML2; One side is connected to the upper portion of the polysilicon electrode PL1 of the first memory cell unit MC1, and the insulating layer 4 is formed through the insulating layer 4, the upper substrate 1 ′, and the field oxide film 2 ′. A semiconductor memory comprising a plurality of memory cells composed of electrodes (3) located at the center of ').
KR1019970030965A 1997-07-04 1997-07-04 Semiconductor memory KR19990008826A (en)

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