KR19990005453A - Register File with Multiple Read / Write and Bypass Paths - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Semiconductor circuit design

2. Technical problem to be solved by the invention

To provide a register file with multiple read / write and bypass paths with low power, high speed operation and small footprint.

3. Summary of the Solution of the Invention

We want to provide a register file with multiple read / write and bypass paths that consists of a simple CMOS logic circuit containing a multiplexer, a flip-flop, and a demultiplexer.

4. Important uses of the invention

Applicable to all chips requiring fast, low power register files.

Description

Register File with Multiple Read / Write and Bypass Paths

The present invention relates to a register file having multiple reads / writes and bypasses, and is applicable to any chip requiring a high speed and low power register file such as a microprocessor, a microcontroller, and a digital signal processor.

1 is a block diagram of a conventional SRAM type register file, which includes a control block 12 for receiving a write enable signal, a clock signal, a necessary control signal, etc. of a memory and generating various control signals for an operation; A first multiplexer 14 that selects and outputs one of a plurality of input data DA ... DL input corresponding to a control signal input from the control block, and a plurality of inputs corresponding to a control signal input from the control block The second multiplexer 11 which selects and outputs one of the two input addresses AA… AN, and one input data output from the first multiplexer 14 and output from the second multiplexer 11 SRAM array 10 for storing at one input address to the SRAM array 17 in response to the control signal output from the control block Emitter of selecting data to be output and the input data output from the first multiplexer 14 when the bypass is constituted by a third multiplexer (13) for outputting a plurality of pieces of output (OA ... OM). Referring to FIG. 1, the operation of a conventional register file is described. First, the write path outputs control signals for controlling the second multiplexer 11 and the first multiplexer 14 in the control block 12, and the second multiplexer 11 outputs the control signal. A plurality of input addresses AA… After selecting one of the ANs and outputs to the SRAM array 10, the first multiplexer 14 receives the control signal and receives a plurality of input data DA. One of the DLs is selected and output to the SRAM array 10. At this time, the write operation is performed by the SRAM control signal 18 output from the control block 12. Next, referring to the read path, as in the write operation, the read operation is performed by the SRAM control signal 18 outputted from the control block 12. In this case, since the read operation is performed, input data is not required, and data to be read is selected using only the input address. , Through the third multiplexer 13 receiving the output of the SRAM array 10 in response to the control signal output from the control block 12. Selected from OM, read data is output. Next, the bypass path operates such that the SRAM array 10 does not operate and the input data selected through the first multiplexer 14 is selected by the third multiplexer 13 and output directly in response to the control signal output from the control block 12. .

The above-described conventional register file is suitable for a large-scale low-speed register file, but when used in a small high-speed register file by a basic configuration, high-speed operation is realized by operations such as word line driving and bit line sensing of SRAM. It is impossible, and the area is increased because the decoder and the peripheral circuit as described above are added. In addition, there is a problem that the configuration of the low-power register file is not easy due to the current consumed by the sense amplifier.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a register file having multiple read / write and bypass paths capable of low power and high speed operation and having a small area.

1 is a block diagram of a conventional SRAM type register file;

2 is a register file block diagram of the present invention;

FIG. 3 illustrates one embodiment of a register file having a 2-lead / 2-write and bypass path implemented with Complementary Metal-Oxide Semiconductor (CMOS). FIG.

According to an aspect of the present invention, a register file having multiple read, write, and bypass paths may be configured to receive one of a plurality of data input signals and select one of the input data signals corresponding to the plurality of first control signals. Input selection means for outputting; Storage means for storing a signal output from the input selection means in correspondence to a clock signal and outputting a signal stored in correspondence to a clock signal to an input of the input selection means; And a register file having multiple read / write and bypass paths, including output selection means for outputting a signal output from the input selection means to one of a plurality of outputs in response to a plurality of second control signals. It is done by

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing a register file of the present invention composed of one multiplexer 101, one flip-flop 103, and one demultiplexer 102. As shown in FIG. Multiple data input signals D1... DN 201 is an input of input multiplexer 101 to select signal SI1... Selected by SI (N + 1) 203 and output to output signal 301, which is selected by output demultiplexer 102 and select signal SO1... A plurality of outputs O1... Configure a read path or a bypass path to one of the OMs 202. The flip-flop 103 inputs the output 301 of the input multiplexer 101 by the clock signal 205 to latch the signal to form a write path. At this time, the flip-flop 103 maintains one of the input signals 201 stored in the flip-flop 103 or previously held data one cycle before, and configures the read path by the demultiplexer 102.

3 is a diagram illustrating a register file having a 2-lead / 2-write and bypass path implemented by a complementary metal-oxide semiconductor (CMOS), and receiving selection signals SEL3, SEL2, and SEL1 as control signals and corresponding thereto. The input 3x1 multiplexer 101 consisting of the first, second, and third CMOS-transmission gates 501, 502, 503, which pass the input data DI1, DI2 and the data stored in the previous cycle, as the control signal. In response to this, the output 1 × 2 demultiplexer 102 comprising the fourth and fifth CMOS-transmission gates 504 and 505 which receive and pass the signal output from the multiplexer 203 and the clock output from the multiplexer 203 is received. A sixth CMOS transmission gate 506 configured to pass in response to the signal, and two signals storing the signals outputted from the sixth CMOS transmission gate 506. A first latch including butters 601 and 602, a seventh CMOS transmission gate 507 for passing a signal output from the latch in response to a clock signal, and two storing the signals output from the seven CMOS transmission gate 507 And a flip-flop 103 composed of a second latch composed of two inverters 603 and 604. First, the bypass path will be described. The input signal DI1 801 or DI2 802 passes through the inverter 401 or 402 by the selection signal SEL1 or SEL2 of the first transmission gate 501 or the second transmission gate 502 in the multiplexer 101. Then, the inverter 404 arrives at the output 702 of the input multiplexer 101 through the inverter 404 via 701 which is a common output of the first transmission gate 501 or the second transmission gate 502. This signal is bypassed to the output OUT1 804 or the output OUT2 805 by the fourth transmission gate 504 or the fifth transmission gate 505 inside the demultiplexer 102. At this time, the inverters 601, 602, 604, and 605 are used to turn on or off the PMOS transistors of the first, second, fourth, and fifth transmission gates.

Next, when the signal is transmitted to the output 702 node of the input multiplexer 101 by the selection signals SEL1 and SEL2 as described above, the input signal passing through the inverter 405 is the sixth and seventh transmission gates 506 and 507 by the clock signal. And a flip-flop 103 composed of a first latch composed of inverters 601 and 602 and a second latch composed of inverters 603,604. After that, the selection signal SEL3 goes high, and SEL1 and SEL2 go low, so that the stored input signal is kept and stored in the flip-flop 103. When the selection signal SEL4 or SEL5 becomes high, a read path is formed in which data stored in the previous cycle passes through the fourth or fifth transmission gates 504 and 505 and outputs to the output OUT1 or the output OUT2.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The present invention made as described above eliminates the sense amplifier of the conventional SRAM type register file, which consumes a lot of power, and is composed of CMOS logic circuits to operate at low power, and is realized by simple connection of a multiplexer and a flip-flop to achieve high speed operation and small size. Since it can be implemented in the area, there is an effect that brings a better performance than the conventional method.

Claims (5)

A register file having multiple read, write and bypass paths, comprising: input selection means for receiving a plurality of data input signals and selecting and outputting one of the input data signals corresponding to the plurality of first control signals; Storage means for storing a signal output from the input selection means in correspondence to a clock signal and outputting a signal stored in correspondence to a clock signal to an input of the input selection means; And output selection means for outputting the signal output from the input selection means to one of the plurality of outputs in correspondence with the plurality of second control signals. 2. The multiple read / write and bypass paths of claim 1, wherein the input selection means selects and outputs one of the signals output from the storage means and the plurality of data input signals in response to the first control signal. Register file with. The method of claim 1, wherein one of a plurality of data input signals input to the input selection means is output in response to the first control signal, and the output signal is transmitted to the second control signal by the output selection means. Register file with multiple read / write and bypass paths with corresponding bypass outputs. The method of claim 1, wherein one of a plurality of data input signals input to the input selection means and a signal output from the storage means is selected and output in response to the first control signal, and corresponding to the clock. A register file having multiple read / write and bypass paths with write paths for storing in storage. The method of claim 1, wherein the input selection means selects and outputs a signal output from the storage means in response to the first control signal, and outputs the output signal from the output selection means to the second control signal. Register file with multiple read / write and bypass paths with corresponding output paths.