KR19990000780A - Redundancy Control Unit of ATM Switch - Google Patents

Abstract

The present invention relates to a redundancy control device for an ATM switch in the field of high speed ATM switch network. In the present invention, each ATM switch and the input / output link of the switch are duplexed in full duplex, and a circuit for redundancy control is added to the existing buffer control circuit so that the redundancy switching of the ATM switch is performed in the state of buffer synchronization. It was. The added redundancy control circuit is relatively a register for reading and writing the address buffer write pointer value from the master ATM switch and the comparator for comparing this value with the current read pointer. Less additional circuitry is required. The two ATM switches configured in this way are redundant in both the link and the switch, so the minimum unit redundancy can be switched, and buffer synchronization is performed when operating in the operating state. Allows operation as a master ATM switch immediately after transition to state.

Description

Redundancy Control Unit of ATM Switch

The present invention relates to a redundancy control device for ATM switches used in the field of high speed ATM switch networks.

The public switching system shall operate without interruption of service for the entire operating time. However, since any element constituting the switch has a probability of failure, the system must be configured to provide reliable and stable service even if a failure occurs. In general, in order to satisfy these conditions, the switch is operated in a redundant configuration.

1 is a redundant control apparatus for an ATM switch according to the prior art, and shows a configuration diagram of a conventional ATM switch switching method (registration number: 特 開平 4-276941) which performs a redundant transfer when a failure is detected.

As shown in Fig. 1, reference numeral '1' represents an interface, '2' represents a valid cell accumulation buffer, '3' represents an invalid cell insertion circuit, '4', '5' represents an ATM switch, '6', ' 7 'represents an invalid cell detection circuit,' 8 'represents a selector,' 9 'represents an invalid cell removal circuit, and' 10 'represents an interface.

In the above ATM switch switching method, a cell input through the interface 1 is normally passed through the valid cell accumulation buffer 2 or the invalid cell insertion circuit 3, and the valid cell is valid when a transfer request occurs. Accumulation is performed in the cell accumulation buffer 2, and at the same time, the invalid cell is inserted by the invalid cell insertion circuit 3 and input to the redundant ATM switches 4 and 5. Then, the valid cells inputted before the invalid cells are inserted from the ATM switches 4 and 5 are outputted and the invalid cells inserted by the invalid cell detection circuits 6 and 7 are detected. ) Performs the redundancy switchover of the ATM switches 4 and 5. The cells output from the selector 8 are again removed by the invalid cell removal circuit 9 and output through the interface 10.

Since the above technique must have a valid cell accumulation buffer (2), an invalid cell insertion circuit (3), an invalid cell detection circuit (6, 7), and an invalid cell removal circuit (9) for each input / output port of an ATM switch, A proportional additional circuit is required, and if a failure occurs in an interface corresponding to an input / output port or a valid cell or invalid cell processing circuit, service using the port is stopped. In addition, in an ATM exchange in which two ATM switches are duplexed, the two ATM switches must have the same operating state. Suppose two redundant ATM switches SW0 and SW1 are operating in master mode and slave mode, respectively. If a defect is detected in the master mode SW0 during operation, SW1 in the slave mode is switched to the master mode and SW0 in which the defect is detected is put into an operation stop state to start the identification and removal of the defect element. Then, when the defective element is removed from SW0, SW0 switches from the operation stop state to the operation state and operates in slave mode. As soon as SW0 changes to slave mode, it is assumed that for some reason, SW1 currently operating in master mode is changed to slave mode and SW0 is changed to master mode. In this state, since the contents of the cell stored in SW0 and the contents of the cell stored in SW1 are different, cells to be stored and serviced in SW1 are lost because SW0 is a master mode.

Accordingly, in the present invention proposed to solve the above problems of the prior art, each ATM switch and the input / output link of the switch are duplexed in a full duplex manner, and the redundant switching of the ATM switch is performed in a buffer synchronization state. To achieve this, a circuit for redundancy control has been added to the existing buffer control circuit. The additional redundancy control circuit is a relatively small register that reads and writes the address buffer's write pointer value from the master ATM switch by the data information to and from the control period, and a comparator for comparing this value with the current read pointer. Additional circuitry is required. The two ATM switches configured in this way are redundant in both the link and the switch, so the minimum unit duplication is possible. When operating in the operating state, the buffer is always synchronized so that the switch can operate as the master ATM switch immediately after switching to the operating state. Its purpose is to.

1 is a block diagram of a redundant control device of an ATM switch according to the prior art.

2 is a block diagram of an apparatus for controlling redundancy of an ATM switch according to the present invention;

3 is a structural diagram of a shared memory ATM switch to which the present invention is applied;

4A and 4B are state diagrams of address buffers when buffer synchronization is not considered.

5 is an address buffer control block diagram for achieving buffer synchronization.

6A to 6E are state diagrams of address buffers in consideration of buffer synchronization.

〈Description of the symbols for the main parts of the drawings〉

10a: input multiplexer 11a: shared memory

12a: output demultiplexer 13a: header converter

14a: memory address interface unit

15a, ..., 16a: address buffer 17a: idle address pool

130a, 130b: ATM Switch

110a, 120a, 110b, 120b: receive interface

140a, 140b: transmission interface

150a, 150b: controller

Referring to the redundant control device of the ATM switch applied to the shared memory ATM switch of the present invention for achieving the above object is as follows.

The ATM switch and the link are duplexed in full duplex. The input of the ATM switch is selected by inputting the data of the master ATM switch from the data received from the two redundant links, and the output of each ATM switch is the same data. Are output simultaneously on two redundant links.

NXN shared memory ATM switch outputs address from IAP (Idle address pool) where available address of shared memory is stored in address buffer (ABUF # N) corresponding to output port N by information included in header when valid cell is input. Store the valid cells in shared memory using this address. In addition, an address stored in an address buffer for outputting a valid cell stored in the shared memory is output in a round-robin manner and provided to the shared memory after time division multiplexing, and the used address is returned to the IAP again.

At this time, the write operation of the address buffer stores the address by a write enable (WE) signal in which the routing control signal and the duplication control signal are combined, and a write pointer indicating a point where the address is to be stored. The read operation is performed by periodically repeating the read enable (RE) signal of the N address buffers combined with the redundancy control signal and sequentially increasing the read pointer of each address buffer.

When a fault is detected during operation, the write and read operations of the address buffer are disabled and in a suspended state. When the fault is removed, the controller in the inactive ATM switch network is removed from the controller in the active ATM switch network. Receives the current write pointer value and sets the same, and then writes and reads the address buffer. After that, the value of the write pointer is sequentially increased from the set value and the value of the read pointer is increased from the initial value to the set value of the write pointer for the valid cell input. Since read enable is disabled and the read address is not output to the shared memory until the value of the read pointer is equal to the set value, the output terminal generates and outputs an idle cell. When the value of the read pointer is equal to the set value, the read address is output and the state is restored. After restoring from inoperational state, the state of the address buffer is the same for the two ATM switches, but the state of the IAP is different from the active master ATM switch. This problem occurs when there are no addresses stored in all address buffers. This is solved by waiting for when there are no valid cells to service and regenerating and using the IAP.

Accordingly, in the present invention, when one of the two ATM switches is switched from the suspended state to the operational state, the buffer is switched in the synchronized state, so that it can immediately operate as the master ATM switch.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As an embodiment of the present invention, the principle of a redundant shared memory ATM switch will be described with reference to FIGS. 2 and 3.

2 is an overall structure of an ATM switch network according to the present invention.

In FIG. 2, reference numerals '100A' and '100B' are redundant ATM switch networks, and will be described below based on '100A'. Reference numerals '110a' and '120a' denote receiving interfaces, '130a' denotes an ATM switch, '140a' denotes a transmission interface, and '150a' denotes a controller.

The ATM switch network redundancy control according to the present invention receives the cell information input through the redundant link at the receiving interface 110a and 120a, respectively. In the receiving interface that is duplicated by input port, if the fault on the path is detected by hardware, redundancy switching is performed on the receiving interface by putting the receiving interface of the defective path into the active mode and the receiving interface of the defective path into the inactive mode. If both paths are normal, the master ATM switch is selected and output. In this case, information on which path received from the master ATM switch includes switching path control (3 bytes) and synchronous control (8 bytes) except for 53 bytes of basic ATM cells among 64 byte internal cell formats. Included in 11 bytes added to The two outputs are wired-or to convey cell information to the ATM switch 130a. At this time, the redundancy switching in the receiving interface is performed based on the internal cell synchronization signal to maintain the integrity of the cell information. The ATM switch 130a performs the routing according to the information contained in the cell in synchronization with the internal cell synchronization signal, and outputs the cell to the transmission interface 140a. When a hardware defect is found in the ATM switch, the ATM switch 130a transmits a separate alarm signal. And mask the output. The cell information output from the transmission interface 140a is transmitted to the ATM switch network of the next stage through a redundant path. The receiving interface of the next stage receiving the transmitted cell from the redundant ATM switch network operates the receiving interface connected to the faultless ATM switch network in the active mode.

On the other hand, the controller 150a and the controller 150b monitor for defect detection at the receiving interface, the ATM unit switch, and the transmitting interface of each ATM switch network, and switch from the operation stop state to the slave mode after the redundancy switching due to the defect. It manages the status control and failure of each part so that the status information of ATM switch can be matched with the status information of master ATM switch.

3 is an internal configuration diagram of an N X N shared memory ATM switch having a limited number of address buffers for each output port to which the present invention is applied.

The configuration includes an input multiplexer (IMUX) 10a for receiving input cells and multiplexing them with serial / parallel conversion, a shared memory unit 11a for storing input cells, and demultiplexing a cell output from the memory. An output demultiplexer (OMUX) 12a for serially converting and outputting, a header converter (CHT) 13a for receiving priority control and routing by receiving a header of a cell from the input multiplexer 10a, and an input cell A certain number of address buffers () for recording the address of the stored shared memory 11a, an idle address pool (IAP 17a) in which the available address of the shared memory capable of storing input cells is recorded, and idle Memory address interface (MAI) 14a for interfacing the address output from address pool 17a and address buffers 15a,..., 16a to shared memory 11a.

Referring to the operation based on the configuration of such an ATM switch 130a as follows.

Cells arriving at each input port are serialized / parallel converted and multiplexed by the input multiplexer 10a and output. The header part of the cell is input to the header converting part 13a to perform priority control, and records the address of the shared memory in which the input cell is stored in the corresponding output address buffer ABUF by the routing information included in the header. . In this way the input cell is stored.

Looking at the process of reading the stored input cells, the contents stored in the N address buffers 15a, ..., 16a are enabled in the form of round-robin, and the output value is read from the shared memory. It is used. The cell data of the shared memory corresponding to the generated address is output through demultiplexing and parallel / serial conversion by the output demultiplexer 12a, and the address used as the read address of the shared memory 11a is used to store the next cell. Is stored back into the idle address pool 17a.

ATM switches employing a common shared memory ATM switch have two identical ATM switches that operate in the same way. When two ATM switches 130a and 130b are operating in an operational state, one of the two ATM switches acts as the master ATM switch and the other acts as the slave ATM switch. The actual data transfer is the master ATM switch and the output of the slave ATM switch is not used.

4A and 4B illustrate a case in which buffer synchronization is not taken into consideration when switching between two redundant ATM switches 130a and 130b.

When the two ATM switches 130a and 130b operate normally, as shown in FIG. 4A, four addresses A, B, C, and D are stored in the address buffers 21a and 21b in the same manner, and the write pointer value at this time. Becomes four. The process of outputting the data output from the shared memory via the transmission interface in a redundant path is omitted in the drawing. Therefore, the data output from the shared memories 20a and 20b are selected from the redundant receiving interfaces 23 and 24 located in the switch network of the next stage. When two ATM switches operate as masters and the other as slaves, the selector 8 selects a cell output from the master ATM switch. Assuming that the ATM switch 130a is a master ATM switch, the cell is output from the slave ATM switch 130b at the same time that the cell is output from the master ATM switch, but the cell output from the slave ATM switch is not selected. As such, the two ATM switches 130a and 130b have the same contents and operate in the same manner. Therefore, if a failure occurs in the master ATM switch 130a, it is possible for the slave ATM switch 130b to operate in the master mode instead of the master ATM switch 130a.

However, the redundant ATM switch structure described above has the following problems. In other words, if it is assumed that a fault has occurred in the ATM switch 130b, the 130b goes into a suspended state and the fault that has occurred is detected and removed. 130b then transitions from the suspended state to the operated state and operates as a slave ATM switch. However, in this case, since the number of addresses in the address buffer of the ATM switch 130a and the number of addresses in the address buffer of 130b are different, there is a problem that the number of cells stored in the ATM switch is different. This problem is illustrated in Figure 4b.

4B shows the state as soon as the ATM switch 130b is changed from the operation stop state to the slave state. All of the cells in 130b were cleared when they went into a suspended state, and the address D stored in the address buffer 21b was written after 130b went into slave mode. In this case, when 130b is switched to the master, 130a is switched to the slave and the A, B, and C addresses stored in the address buffer 21a are lost. The loss of the A, B, and C addresses means that the cells stored in the common memory have been lost. The present invention mainly proposes a method for solving this problem.

Fig. 5 shows a method of controlling any one of the address buffers of the shared memory ATM switch duplexed to solve the above problem.

If the ATM switches 130a and 130b are redundant and 130a is operated as a master ATM switch, 130b is operated as a slave ATM switch, and a failure occurs at 130a, 130b is switched to the master ATM switch and 130a goes into an inoperative state. When the defect is removed from the operation stop state 130a, the controller 150a reads the write pointer value of the 130b currently in operation and writes it to the relative write pointer setting unit 33a. At this time, the timing of reading the write pointer value of the write pointer 31b and writing it to the write pointer setting unit 33b should be performed in a period of providing N read addresses to the shared memory. This is because, if this operation is performed at the time of inputting the cell, the write pointer is operated before the value of the write pointer is converted to the set value, and thus there is a high probability that the write pointer is different from the write pointer value of the master ATM switch in operation. Therefore, the write pointer generator 31a avoids the timing of storing the write address to store the input cell in the shared memory and reads the value written to the write pointer generator 31b at the timing at which the read operation is being performed. When the write address is stored by writing to the relative write pointer setting section 33a, the write pointer is incremented after that value. The read pointer generator 32a sequentially increases from 0 and disables the read enable signal until the read pointer generator 32a is equal to the value recorded in the relative write pointer setter 33a. Since the read address of the shared memory is not output from the address buffer while the read enable signal is disabled, the shared memory does not output valid cells and generates idle cells after the shared memory. Once the value of the read pointer is equal to the relative write pointer setting, the address is output by the read enable and a valid cell is output from the switch.

The operation of the redundant ATM switch shown in FIG. 5 is shown in FIGS. 6A-6E. It is assumed here that the ATM switch 130a operates in master mode and 130b operates in slave mode.

In this case, as shown in Fig. 6A, the address buffers 41a and 41b have the same addresses A, B, C, and D, and the values 42a and 42b of the write pointer both have four. By the way, suppose that the ATM switch 130b in slave mode has been changed to a suspended state due to a defect. Then, as shown in Fig. 6B, all addresses A, B, C, and D in the address buffer 41b are erased. At this time, if all addresses in the address buffer 41b are not erased, it is impossible to determine which address is stored in the address buffer 41b. Therefore, the number of addresses in the address buffer 41b cannot be defined. Therefore, the ATM switch 130b, which was in the suspended state, must reset the address buffer, the write pointer, and the read pointer before synchronizing to the slave mode, and synchronize the address buffer with the master ATM switch. Then, as shown in Fig. 6C, the write pointer 42b of the ATM switch 130b reads the value 9 from the write pointer 42a operated by the master ATM switch and sets it to the same value. Since the storage of the address is disabled until the value of the write pointer 42b becomes the set value, no address is stored in the address buffer 41b. Next, as illustrated in FIG. 6D, addresses J, K, L, and M, in which the write pointer value is input after 9, are equally stored in the address buffers 41a and 41b, and the value of the write pointer is increased to 13. . However, since the value of the read pointer still in the ATM switch 130b is smaller than the value 9 of the initially set write pointer, the read address of the shared memory is not output from the address buffer 41b. Therefore, the cell output from the ATM switch 130b is a dormant cell and the ATM switch 130b is still in the stopped state. In the last step of FIG. 6E, the state of the address buffers 42a and 42b of the ATM switches 130a and 130b is completely the same, and the value of the read pointer 44b also has a value 10 greater than nine. At this time, since the read address is output from the address buffer 41b and the read enable signal is enabled, the ATM switch 130b should be first switched to the slave mode in an operational state, and the master mode can be set immediately thereafter.

The present invention made as described above has the following effects.

First, the present invention allows redundant switching with fewer additional circuits than when using an effective cell accumulation buffer, an invalid cell insertion circuit, an invalid cell detection circuit, and an invalid cell removal circuit.

Second, duplex switching is performed by configuring the ATM switch and the receiving interface in full-duplex mode, which prevents the entire ATM switch network from being suspended due to partial defects, and enables switching by input / output ports by switching the receiving interface. It was.

Third, cell loss does not occur due to address buffer synchronization during redundant switching.

Claims (6)

In a full duplex ATM switch network Receives data input from two redundant paths and selects the data input from the master ATM switch if the path is normal, and selects and outputs the data input from the path without defects if a hardware fault is detected in the path. Redundant receiving interface; An ATM switch configured to be redundant and process data input from a receiving interface by routing information, and having a control circuit for buffer synchronization during redundancy switching; A transmission interface which duplicates the data input from the ATM switch in the same manner and masks the output according to the fault condition of the ATM switch or outputs it normally through two paths; A controller which performs control to match the state information of the ATM switch to be restored with the currently operating ATM switch to recover the ATM switch in the suspended state to the operational state after the redundant switchover due to a fault; An address buffer for storing an address for storing the cell in the shared memory in the ATM switch and outputting the address at the time the cell is output; A write pointer generation unit generating a pointer value for storing an address of a shared memory in which a cell is to be stored in an address buffer; A read pointer generator for generating a pointer value for outputting an address stored in an address buffer to output a cell stored in a shared memory; A read enable generator configured to generate an enable signal such that an address is output in a round-robin form from an address buffer according to a pointer value generated by the read pointer generator; A redundancy control device for an ATM switch, comprising a relative write pointer setting unit that reads and writes a write pointer value of a counterpart ATM switch to return to an operational state after a switchover due to a fault. The method of claim 1, wherein the receiving interface is It accepts data from the redundant path, selects the data output from the master ATM switch if the path is normal, and selects the data received on the normal path if one of the two paths is abnormal, and outputs the outputs of the two receiving interfaces. A redundancy control device for an ATM switch, characterized in that redundancy control is performed by wired-or-outputting. The method of claim 1, wherein the controller If one of the redundant ATM switches goes into a suspended state due to a fault during operation, a relative write of an ATM switch to be returned by reading a write pointer value from another ATM switch that is currently in operation to return to the operational state after the fault is removed. The redundancy control device of an ATM switch characterized by being recorded in a pointer setting part. The method of claim 1, wherein the write pointer generator A redundancy control device for an ATM switch which provides a value for storing an address in a designated place of the address buffer, and updates a value with a write pointer of an ATM switch in an operation state from an ATM switch in an operation stop state after redundancy switching. The method of claim 1, wherein the relative write pointer setting unit A redundancy control device for an ATM switch, characterized in that a write pointer value of an ATM switch in an operational state is read out and recorded for use by an ATM switch in an inactive state in which a defective element is removed after a redundant switching by a fault. The method of claim 1, wherein the read enable generator In order to provide a read address to the shared memory of the ATM switch, N read enable operations normally operate in a round-robin form, and an ATM switch which is in a suspended state in which a faulty element is removed after a redundancy switchover by a fault is operated. And a read enable signal generated by reading a write pointer value from an ATM switch and comparing the value with a read pointer value sequentially increasing from an initial value to generate a read enable signal.