KR19990000720A - Data Partitioning and Reassembly Using Dual Port RAM and Its Control Method - Google Patents

Abstract

The present invention relates to a data partitioning and reassembly apparatus in a set-top-unit connected to a subscriber side of a set-top-box and performing data communication, and a method of controlling the same. Glue logic to perform smooth data partitioning and reassembly operation, Local memory for storing data to be transmitted and receiving the received data, Central processing unit connected to the local memory to control the transmission and reception of data, The data partitioning and reassembly device was configured to include the glue logic and a dual port RAM that temporarily stores data transmitted and received simultaneously with the central processing unit.

In particular, the present invention has an effect of enabling the central processing unit to perform software division and reassembly (data registration) of data.

Description

Data Partitioning and Reassembly Using Dual Port RAM and Its Control Method

The present invention relates to a set-top-unit (SET-TOP-UNIT) is connected to the subscriber side in the SET-TOP-BOX and performs data communication. Data segmentation and reassembly device and control method using dual port RAM, which is configured to process and transfer data faster by using software when transferring data between network interface units. It is about.

The current broadcasting service is focused on providing comprehensive cable broadcasting service, satellite broadcasting service, and video on demand service. In order to perform such a broadcast service, an apparatus capable of receiving each broadcast service to a subscriber and transmitting data requesting a service to a provider that provides a broadcast service is required. The most common type of device as described above is the set-top box.

A configuration of a set-top box that is generally used is composed of a network interface unit for interface with a network and a set-top-unit for interface with a subscriber, as shown in FIG. 1.

The set-top unit is connected via a universal bus dedicated to the network interface unit and the M-Pak 2 transport stream and the control RS232C, and is connected via the system bus with other devices of the set-top unit. A MAIN central processing unit for overall control of the box system; MCU which is connected to the main central processing unit through RS232C and assists the main central processing unit, and performs an operation control mainly by signals transmitted from a remote controller and a key matrix (MATRIX CONTROL UNIT). Called MCU); An MPEG-2 decoder for decoding data transmitted from an encoded service provider through a network interface unit; An audio DAC (digital analog converter: hereinafter referred to as DAC) for converting the digital audio data decoded and output by the MPEG-2 decoder into analog audio data; A graphic processor configured to process a video signal decoded and output by the MPEG-2 decoder; Encodes the video signal processed by the graphic processor to be NTSC signal (NATIONAL TELEVISON STANDARDS COMMITTEE SIGNAL) and ARM signal (PHASE ALTERNATING BY LINE SIGNAL: color TV signal system developed in Germany) An encoder; It includes a plurality of memories to facilitate data processing in each of the blocks.

In the set-top unit configured as described above, when the video and audio data received from the network interface unit is transmitted to the MPEG-2 decoder as an MPEG transport stream, and a control signal is transmitted to the main central processing unit, the MPEG-2 decoder is connected to the network. Decodes video and audio data input from the interface unit, and transmits the audio data to the audio DAC. The video data is transmitted to the graphics processor. The audio DAC converts the digital audio signal input from the MPEG2 decoder into an analog audio signal and outputs the analog audio signal. In the graphics processor, the image data input from the MPEG-2 decoder is processed by the graphic and transmitted to the encoder. The encoder encodes and outputs the data transmitted from the graphics processor into a signal (NTSC or ARM signal) that conforms to each television specification. The main central processing unit is a system server By a control signal transmitted from the network interface unit via controlling the MPEG1 decoder 2 and the graphics processor and the MCU, MCU analyzes the signal input from the remote control and the key matrix to assist the operation of the main CPU.

The set-top unit of the set-top box is composed of an M-pack 2 transport stream bus and an RS232C control bus between the network interface unit and the main CPU of the set-top unit. It does not comply with the Digital Conference (DAVIC: DIGITAL AUDIO VISUAL COUNCIL) standard. In the DAVIC standard, the high speed downstream bus for M-Pak 2 transmission and the non-directional bus for control (BI-DIRECTIONAL BUS: ATM) are referred to as ASYNCHRONOUS TRANSRER MODE (hereinafter referred to as ATM). Bus is transmitted and received in the form of a cell.

As shown in FIG. 2, the ATM cell data format includes a 5-byte header portion containing data information such as a virtual channel / path identifier and error identification information, and a 48-byte data portion carrying actual data. One ATM cell has a total length of 53 bytes.

The ATM cell data is transmitted through the A0 interface (interface standard in the set-top box established by DAVIC). The A0 interface between the set-top unit and the network interface unit is shown in FIG. As shown, high speed data (HS_DATA), clock (HS_CLK) and synchronization (HS_SYNC) signals are transmitted from the network interface unit to the set-top unit via the HIGH SPEED DOWNSTREAM BUS. Transmit data (TX-DATA) from the set-top-unit to the network interface unit via the non-directional bus (BI-DIRECTIONAL BUS), receive data (RX_DATA) from the network interface unit to the set-top-unit, Transmit (TX_CTL) and receive (RX_CTL) control signals in both directions, send serial data (SDA) and clock (SCL) signals in both directions via LOCAL CONTROL BUS, and reset bus Through The transmitter transmits the reset signal (RESET) in both directions and transmits the analog audio (A_AUDIO) and video (A_VIDEO) signals from the network interface unit to the set-top unit through the analog pass-throw bus. In addition, digital and analog power (DIGITAL_POWER, ANALOG_POWER) and ground (DIGITAL_GRD, ANALOG_GRD) signals are transmitted from the set-top unit to the network interface unit through the NETWORK INTERFACE UNIT POWER CONNECTIONS.

The communication of the control data (ATM cell data) for implementing the actual broadcast service is a data communication performed through a non-directional bus called a UTOPIA INTERFACE.

The A0 interface configured as described above is performed separately by configuring hardware corresponding to each characteristic for each data communication through each data bus. In this case, the M-Pak 2 high speed downstream bus that requires real-time transmission of data is generally used. In the case of low-speed data transmission, the hardware configuration is complicated and the system becomes bulky and expensive.

The present invention is to solve the above problems, to provide a data partitioning and reassembly apparatus configured using the dual port RAM and glue logic that is the basis of data processing in order to control the utopia interface in the A0 interface. It is characterized by.

That is, by configuring the data partitioning and reassembly apparatus using the dual port RAM, ATM cell communication for low speed control is possible, and the memory area of the dual port RAM is composed of the transmission data, the reception data, and the signal area. In this way, data communication is performed by the setting state of the signal region, so that data processing can be performed in a software manner during data communication.

The data partitioning and reassembly device configured using the dual port RAM is connected to the network interface unit to store the data to be transmitted and the glue logic to perform the smooth data partitioning and reassembly operation at the utopia interface. A local memory configured to receive and store data, a central processor connected to the local memory to control data transmission and reception, and a dual port RAM configured to temporarily store data transmitted and received simultaneously to the glue logic and the central processing unit. It is done by

The configuration of the memory area of the dual port RAM used above includes a transmission data area consisting of n segments storing data to be transmitted, a receiving data area consisting of n segments storing data to be received, and a signal indicating a data state. The signal area includes a transmission interrupt signal area for generating an interrupt when data is transmitted, a reception interrupt signal area for generating an interrupt when data is received, information on received data, and the like. A reception signal area (RESERVED) for storing and indicating that data has been received, and a reception segment signal area (RxSI) for storing information on the usable area of the reception data area.

In the control process of the data segmentation and reassembly apparatus constructed using the dual port RAM as described above, when the control user information (CONTROL USER DATA: refers to data to be transmitted) occurs during data transmission, The length of the data to be transmitted to the end address (END ADDRESS) of the dual port RAM after combining the user information with the header information, matching the data into ATM cell unit data, storing it in the transmission data area of the dual port RAM. Save it. As described above, when data is stored in the dual port RAM, a transmission interrupt occurs from the dual port RAM to the glue logic. When the transmission interrupt occurs, the glue logic causes the transmission data stored in the end address (transmission interrupt signal area) of the dual port RAM to occur. It reads the length information, reads the data as much as the length information from the transmission data area of the dual port RAM and sends it to the network interface unit.

The operation at the time of data reception is that if the received data is input into glue logic through the network interface unit, the glue logic stores the input data in the reception data area consisting of n segments of the dual port RAM, and then receives the reception segment signal area. To set the location where the currently received data is stored, and to receive the received data from the central processing unit, set the data to the END ADDRESS-1 address of the dual port RAM. Sets DUMMY data that informs the receipt of a message. As described above, when the virtual data is set in the dual port RAM, a reception interrupt occurs in the dual port RAM to the central processing unit. When the reception interrupt occurs, the central processing unit reads the data in the reception segment signal area of the dual port RAM to present the data. Recognizes the position where the received data exists, reads the data from the recognized position, stores the data in the local memory, matches the data, and processes the information.

When the data division and reassembly apparatus is configured using the dual RAM as described above, the central processing unit can perform the data division and reassembly operation in software.

1 is a view showing the configuration of a typical set-top-box,

2 is a view showing the structure of a typical ATM cell;

3 shows a typical A0 interface,

4 is a view showing the configuration of a data partitioning and reassembly apparatus implemented by the present invention;

5 is a diagram illustrating a configuration of a memory area of a dual port RAM used in the present invention;

6 is a view showing a control method of a data partitioning and reassembly apparatus implemented in the present invention,

a is a diagram showing a process during data transmission;

b is a view showing a process at the time of data reception.

* Description of the symbols for the main parts of the drawings *

1 network interface unit 2 set-top unit

10: Glue Logic 20: Dual Port RAM

30 central processing unit 40 local memory

11 timing / synchronization processing unit 12 dual port RAM interface unit

13: Dual Port RAM Interrupt Handler

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

EXAMPLE

4 is a diagram illustrating a configuration of a data partitioning and reassembly apparatus implemented by the present invention, and includes a glue logic connected to the network interface unit 1 to perform a smooth data partitioning and reassembly operation at a utopia interface. 10), a local memory (40) storing data to be transmitted and receiving and storing the received data, a central processing unit (30) connected to the local memory (40) to control transmission and reception equalization of data, and And dual port RAM 20 for temporarily storing data transmitted and received simultaneously with the glue logic 10 and the central processing unit 30.

The glue logic 10 is connected to the dual port RAM 20, the dual port RAM interface unit 12 for transmitting and receiving data and interrupt generation, and the transmission interrupt generation stage of the dual port RAM 20 A dual port RAM interrupt handler 13 connected to the dual port RAM interface unit 12 to control interrupt processing in the dual port RAM 20, a network interface unit 1 and a dual port RAM interface unit ( And a timing / synchronization processing section 11 which is simultaneously connected to 12) and processes timing and synchronization at the time of the utopia interface.

For reference, such a data partitioning and reassembly apparatus is a configuration between the network interface unit 1 and the main central processing unit of the set-top unit 2 in FIG. 1. That is, the central processing unit 30 described above refers to the main central processing unit in FIG. 1.

The configuration of the memory area of the dual port RAM 20 used above is a setting of a transmission data area consisting of n segments, a receiving data area consisting of n segments, and a signal representing a data state as shown in FIG. The signal area includes a transmission interrupt signal area for generating an interrupt when data is transmitted, a reception interrupt signal area for generating an interrupt when data is received, information on received data, and the like. And a reception segment signal area for storing information on the usable area of the reception data area.

In this case, one segment is composed of 53 bytes in order to store one ATM cell data, and the division of the receiving data area into n segments is a sequence of continuous data (or data) arriving from the network interface unit 1. It is for processing burst, and also for enabling a mixing process of cells constituting several messages.

In the above continuous data processing, the received data is 53 bytes of ATM cell unit and one segment is composed of 53 bytes, one received data is stored in one segment, and the received data area is divided into n segments. Since a plurality of pieces of data are continuously received, it is possible to store the received data in a receiving data area and then process them sequentially. Mixing of cells constituting the plurality of messages is performed in the central processing unit 30. After recognizing the header information of the data stored in each segment, it is possible to classify and match the segment data having the same header information, and even if multiple message data are received at the same time, different data are not mixed.

As shown in FIG. 6, the control process of the data partitioning and reassembly apparatus having the above-described configuration is performed by the central processing unit 30 to check whether or not control user information has occurred during data transmission (see FIG. 6A). A first step S1; When the control user information is generated in the first step S1, the data is matched and stored in the transmission data area of the dual port RAM 20, and the length information about the data stored in the transmission data area of the dual port RAM 20. A second step (S2) of storing the data in an end address (transmission interrupt signal region) of the dual port RAM 20; A third step S3 in which a transmission interrupt occurs after the second step S2; A fourth step S4 of reading data length information from the end address (transmission interrupt signal region) region of the dual port RAM 20 in the glue logic 10 after the third step S3; A fifth step S5 of reading data stored in the transmission data area of the dual port RAM 20 after the fourth step S4; After the fifth step S5, it is checked whether the length of data read from the transmission data area of the dual port RAM 20 is equal to the length information read from the end address (transmission interrupt signal area) of the dual port RAM 20. Otherwise, the operation of the fifth step (S5) is repeated, and if the same, the sixth step (S6) of transmitting data to the network interface unit 1 is performed sequentially, and the second step in the first step (S1) Operation S100 until step S2 is performed between the central processing unit 30 and the dual port RAM 20, and operation of the third step S3 is performed by the central processing unit 30 and the dual port RAM 20. ) And the glue logic 10, and the operation S200 from the fourth step S4 to the sixth step S6 is performed between the dual port RAM 20 and the glue logic 10.

Upon receiving data (see FIG. 6B), the first step T1 of receiving data from the network interface until the data received by the glue logic 10 becomes a predetermined value or more; A second step (T2) of storing the received data in the reception data area of the dual port RAM 20 and setting a reception segment signal area when the data received in the first step T1 is greater than or equal to a predetermined value; After the second step T2, it is checked whether the data stored in the dual port RAM 20 is greater than or equal to a predetermined value, or if the data of the second port T2 is repeatedly performed, the dual port RAM 20 is repeatedly performed. A third step (T3) of setting virtual data at the end address-1 address (receive interrupt signal region) of the " A fourth step T4 in which a reception interrupt occurs after the third step T3; After the fourth step T4, the central processing unit 30 reads the data stored in the reception segment signal area of the dual port RAM 20 to determine the address of the reception data area of the dual port RAM 20 to start data reading. Recognizing a fifth step (T5); The sixth step T6 is performed to read data stored in the reception data area of the dual port RAM 20 based on the recognized address after the fifth step T5, store the data in the local memory 40, and match the data. Sequential operation, the first step (T1) to the third step (T3) (T100) is made between the glue logic 10 and the dual port RAM 20, the fourth step (T4) is a glue logic ( 10) and the dual port RAM 20 and the central processing unit 30, the fifth step (T5) to the sixth step (T6) (T200) is the dual port RAM 20 and the central processing unit 30 Takes place).

The operation of the data segmentation and reassembly apparatus as described above will be described first with the flow of data transmission.

The central processing unit 30 reads the control user information stored in the local memory 40 and combines the header information to create 53-byte ATM cell data (data partitioning process). The transmission data of the dual port RAM 20 After storing in the area, the length information of the data to be transmitted is written to the end address (transmission interrupt signal area) of the dual port RAM 20, and the transmission interrupt signal area is set to generate a transmission interrupt. When the transmission interrupt occurs, the glue logic 10 reads the transmission data length information stored in the end address (transmission interrupt signal area) of the dual port RAM 20, and then transmits data in the transmission data area of the dual port RAM 20. Data is read by the length and transmitted to the network interface unit 1 through the utopia interface. When the data transmission is completed through the above process, the dual logic (RAM) to inform the processor (central processing unit 30) that the transmission data region of the dual port RAM 20 can be reused in the glue logic 10. A specific value indicating reuse is stored in the end address-1 address (receive interrupt signal area) of 20) and a receive interrupt is generated. When a receive interrupt occurs, the central processing unit 30 of the dual port RAM 20 The contents stored in the end address-1 address (receive interrupt signal area) are read, and the reuse of the transmission data area of the dual port RAM 20 is confirmed.

The flow when receiving data is as follows.

First, the glue logic 10 periodically reads data in the reception segment signal area of the dual port RAM 20 to check whether an ad segment is available in the current reception data area, and starts the start address of the available segment in the local memory ( Not shown). When the received data is input to the glue logic 10 through the network interface unit 1, the glue logic 10 receives the dual port RAM 20 from the start address of the available segment of the received data area identified above. After the data is written, the data in the receiving segment signal area is updated (UP-DATE), and the virtual data is written to the end address-1 address (receive interrupt signal area) of the dual port RAM 20. When the virtual data is written to the end address-1 address (receive interrupt signal region) of the dual port RAM 20 through the above process, a reception interrupt occurs from the dual port RAM 20 to the central processing unit 30, and the reception is performed. When an interrupt occurs, the central processing unit 30 reads the data of the receiving segment signal area, recognizes the start address of the receiving data area segment in which the currently received data is written, and then starts the data from the recognized receiving data area segment address. Reads and writes the data to the local memory 40 and then processes the received information.

In the above process, the interrupt is generated in the dual port RAM 20 by the setting state of two interrupt signal regions (send and receive) of the dual port RAM 20, and the central processing unit 30 and the glue logic ( In 10), the interrupt generation state is recognized by continuously reading the states of the two interrupt regions of the dual port RAM 20.

In the above process, if the count of the received bytes exceeds a certain threshold within the predetermined time, the glue logic 10 writes the received data to the receiving data area and then updates the data of the receiving segment signal area. When the number of segments occupied by the data stored in the receive data area of the port RAM 20 becomes greater than a certain number, the virtual data is written to the end address-1 address (receive interrupt signal area) of the dual port RAM 20 to receive the interrupt. When the reception interrupt occurs, the CPU 30 checks the reception segment signal area, reads data stored in all valid segments, and has the same header information by the header information of the data stored in each segment. Match the data to form a message (data reassembly process), Performs processing on the information.

Through the above process, not only the buffering effect of ATM cells arriving in bursts can be obtained, but also the interruption of frequent interrupts to the central processing unit 30 can be achieved, thereby reducing the overload. .

As described above, the present invention, in particular, by transmitting the ATM data that is transmitted between the network interface unit and the set-top unit by using a dual port RAM, the division and reassembly of data (data reconstruction) Matching) can be performed in software on the central processing unit.

Claims (9)

In the data partitioning and reassembly apparatus of the set-top unit, Glue logic for smooth data partitioning and reassembly operations in the Utopia interface connected to the network interface unit, Local memory for storing the data to be transmitted and receiving the received data, and Local memory for accessing the data Central processing unit for controlling the transmission and reception operation, and data partitioning and reassembly using dual port RAM, characterized in that it comprises a dual port RAM for temporarily storing data transmitted and received simultaneously connected to the glue logic and the central processing unit . The method of claim 1, Glue logic is connected to dual port RAM to handle data transmission and interrupt generation, and dual port RAM interface part to connect interrupt generation terminal of dual port RAM and dual port RAM interface part to dual port RAM Dual port RAM interrupt handler for controlling interrupt processing in the network and a timing / synchronization processor for timing and synchronization during the utopia interface simultaneously connected to the network interface unit and the dual port RAM interface unit Data partitioning and reassembly using RAM. The method of claim 1, The configuration of the memory area of the dual port RAM includes setting of a transmission data area consisting of n segments storing data to be transmitted, a receiving data area consisting of n segments storing data to be received, and a signal representing a data state. Data segmentation and reassembly device using dual port RAM, characterized in that the signal area for. The method of claim 3, wherein The signal area includes a transmission interrupt signal area for generating an interrupt when data is transmitted, a reception interrupt signal area for generating an interrupt when data is received, a reception signal area for storing the information of the received data, and the like to indicate that data has been received. RESERVED) and a reception segment signal area (RxSI) that stores information on the usable area of the reception data area. The method of claim 3, wherein Data segmentation and reassembly device using dual port RAM, characterized in that one segment consists of 53 bytes. In the control method of the data partitioning and reassembly device configured using the dual port RAM, In data transmission, the central processing unit reads the control user information stored in the local memory, combines the header information, creates 53-byte ATM cell data, stores the data in the dual port RAM transmission data area, and then stores the dual port RAM. When the length information of the data to be transmitted is written to the end address (send interrupt signal area) of the transmitter, a transmission interrupt occurs. When the transmission interrupt occurs, the transmission logic stores the transmission data stored in the end address (transmission interrupt signal area) of the dual port RAM. After reading the length information, the data is read as much as the transmission data length in the transmission data area of the dual port RAM and transmitted to the network interface unit through the utopia interface. Reusing the transmission data area of the port RAM In order to inform the processor (central processing unit), a specific value (virtual data) indicating a reusability is stored in the end address-1 address (receive interrupt signal area) of the dual port RAM and a receive interrupt is generated. Occurs, the central processing unit reads the contents stored in the end address-1 (receive interrupt signal area) of the dual port RAM, and confirms that the receive data area of the dual port RAM can be reused. Control method of data segmentation and reassembly apparatus using. The method of claim 6, When receiving data, the glue logic periodically reads data in the receive segment signal area of the dual port RAM, checks whether the available segment is available in the current receive data area, and starts the start address of the available segment in local memory (in the drawing). (Not shown), when the received data is input to the glue logic through the network interface unit, the glue logic sends the received data from the start address of the available segment of the received data area to the dual port RAM. After writing, the data of the receiving segment signal area is updated (UP-DATE), and virtual data is written to the end address-1 address (receive interrupt signal area) of the dual port RAM. When the virtual data is written to the end address-1 address (receive interrupt signal area) of the dual port RAM through the above process, a receive interrupt is generated from the dual port RAM to the central processing unit. When the receiving interrupt occurs, the central processing unit Reads the data of the received segment signal area, recognizes the start address of the received data area segment to which the currently received data is written, reads the data from the recognized received data area segment address, writes the data to the local memory, and then matches the data. And controlling the received information by using the dual port RAM. The method according to claim 6 and 7, The interrupt is generated by the setting status of the two interrupt signal areas (send and receive) of the dual port RAM, and the two interrupt signal areas (send and receive interrupt signal area of the dual port RAM continuously in the central processing unit and glue logic. The method of controlling a data partitioning and reassembly device using a dual port RAM, comprising: reading a state of a terminal) and recognizing an interrupt occurrence state. The method of claim 7, wherein In the central processing unit, the received data matching process uses the dual port RAM, wherein the central processing unit recognizes the header information of the data stored in each segment, and classifies and classifies the segment data having the same header information. Method for controlling data partitioning and reassembly.