KR19980086694A - Reversible Embedded Wavelet System - Google Patents

Abstract

Compression, and / or restoration of an image. In one embodiment, the present invention includes a system having a buffer, a wavelet transform unit, and a coder. The wavelet transform unit has an input connected to the buffer, performs wavelet transform on the pixels stored in the buffer, and generates coefficients on the output. The coder is connected to the wavelet transform unit to encode the transformed pixel received from the buffer.

Description

Reversible Embedded Wavelet System

The present invention relates to a data compression and decompression system, and more particularly, to an apparatus and method for encoding and decoding lossless and lossy data in a compression / decompression system.

This application is a continuation-in-part (CIP) application number 08 / 643,268, entitled Compression / Decompression Using Reversible Embedded Wavelet, filed May 3, 1996, which is incorporated herein by reference in its entirety for Reversible Wavelet No. 08 / 498,036, entitled Transform and Embedded Codestream Manipulation, which is the CIP of Application No. 08 / 310,146, entitled Apparatus for Compression Using Reversible Embedded Wavelets, filed September 20, 1994.

Data compression is a very useful tool for storing and transmitting large amounts of data. For example, the time required for image transmission such as facsimile transmission of manuscripts decreases sharply when the number of bits required to reproduce an image is reduced using compression.

There have been many data compression techniques in the past. Compression techniques can be divided into two categories: lossless coding and lossy coding. Lossy coding is concerned with lossy coding and thus does not guarantee complete reconstruction of the original data. The purpose of lossy coding is to convert the original data so that it can be recognized without being rejected. In lossless coding, all information is retained and the data is compressed so that it can be completely reconstructed.

In lossless coding, the input symbols or density data are converted into output code words (cordwords). The input may be an image, a voice, a one-dimensional (e.g., spatially or temporally varying) data, a two-dimensional (e.g. data that changes in two spatial directions (one spatial direction and one time direction) / Multi-spectral data. If the compression is successful, the codeword is represented by bits less than the number of bits required for the unencoded input symbol (or density data). The lossless coding method includes a dictionary coding method (e.g., Lempel-Ziv), run-length coding, enumerative coding, and entropy coding. In lossless image compression, compression is based on prediction or context and coding. The JBIG standard for facsimile compression (ISO / IEC 11544) and the DPCM for continuous-tone images (option of the differential pulse code modulation-JPEG standard (ISO / IEC 10918)) are examples of lossless compression of images. In lossy compression, the input symbol or density data is quantized before being converted to an output code word. Quantization removes non-critical characteristics while preserving meaningful characteristics of the data. Before quantization, lossy compression systems sometimes use transforms to densify energy. JPEG is an example of a lossy coding method of image data.

Recent developments in image signal processing have focused attention on the need for efficient and accurate forms of data compression coding. Various types of transformation or pyramidal signal processing have been proposed, including multi-resolution pyramid processing and wavelet pyramid processing. This form is also referred to as subband processing and hierarchical processing. The wavelet pyramid processing of image data is a specific form of a multi-resolution pyramidal process using quadrature mirror filters (QMFs) that produce subband decomposition of the original image. There are other types of non-QMF wavelets. For more information on wavelet processing, see Antonini, M., et al., Image Coding Using Wavelet Transform, IEEE Transaction on Image Processing, Vol. 1, No. 2, April 1992; Shapino, J., An Embedded Hierarchical Image Coder Using Zerotrees of Wavelet Coefficient, Proc. IEEE Data Compression Conference, pgs. 214-223, 1993. For information on reversible transforms, see Said, A. and Pearlman, W. Reversible Image Compression via Multiresolution Representation and Predictive Coding, Dept. of Electrical, Computer and Systems Engineering, Renssealaer Polytechnic Institute, Troy, NY 1993.

Compression is sometimes time consuming and requires memory. It is desirable to have as little memory as possible and / or to perform fast compression. In some applications, compression is not used because quality can not be guaranteed and the compression ratio is not sufficiently high or the data rate can not be controlled. However, it is desirable to use compression to reduce the amount of information to be transmitted and / or stored.

Digital copiers, printers, scanners, and multifunction machines have made great strides in frame stores. Compressed frame stores reduce memory and reduce the cost of the product's frame store. However, many frame stores are implemented as RAMs. Ram is fast, but usually expensive. Hard disks can be used as memory and are generally considered cheap (or generally less expensive than RAM). Thus, system manufacturers have the advantage that they can produce less expensive systems using hard disks instead of RAM for purposes such as frame stores.

The problem with using a hard disk in time sensitive applications is that it is difficult to access information from the hard disk as quickly as the same information can be accessed from the RAM. In addition, many hard disks use compression when storing information on a disk to increase the amount of information stored on the disk. The time required to perform the compression also hinders the use of the hard disk in time sensitive applications. The use of low speed and compression in the use of hard disks makes it difficult to implement hard disk usage in time sensitive applications.

The present invention provides fast lossy / lossless compression. The present invention implements a system that can use cheap hard disk technology instead of expensive RAM. The present invention is also intended to match a hard disk to a bandwidth and to bandwidth of another part that implements a system such as a print engine. The present invention is also intended to use RAM so that the compression and decompression times are not much slower than the RAM speed. In this way, the present invention performs ratio matching to RAM.

Figure 1 shows a context-dependent relationship. Children are controlled by their parents.

2A illustrates an order similar to a raster order.

Figure 2b illustrates another embodiment of the order, herein referred to as a short seam order.

Fig. 2C illustrates another shot shim order.

Figs. 3A to 3H show results of application of TS-conversion for 4-level conversion to the wavelet tree of the present invention.

Figure 4 (A) is a block diagram of one embodiment of a forward / inverse filter unit for use in implementing a one-dimensional filter.

FIG. 4B is a block diagram of one embodiment of a first level positive transform according to the present invention.

Figure 5 is a block diagram of one embodiment of a full-scale transform according to the present invention.

6 is a timing diagram for outputting the coefficient.

Figures 7A-7H show the results (output) of each one-dimensional filtering operation of the TT-transform.

8 is a block diagram of a 10-tap forward / reverse filter unit.

9 is a block diagram of one embodiment of an overlay unit for the forward / inverse filter of FIG.

Figure 10 illustrates the ordering of a code stream and the ordering in a coding unit.

Fig. 11 illustrates the bit depths of various coefficients in two-level TT-transform and TS-transform decomposition of an input image having b bits per pixel.

12 is an embodiment of a frequency band multiplier used in coefficient alignment in the present invention.

13A shows the coefficients partitioned into the most important data and the less important data.

13B shows a case of lossless data in which data is not discarded.

Fig. 13C shows the case where a 1-bit plane of data is discarded (i.e., Q = 2), as discarding the bit plane is like dividing by 2.

14 is a flowchart illustrating one embodiment of the operation of the compression / decompression system.

15 shows an embodiment in which 6 bits are used in each tree.

16 is a flowchart for coding the most important chunks.

Figure 17 is a block diagram of one embodiment of a formatting unit and context model used during the coding pass of the most important data.

Figure 18 illustrates one embodiment of the first bit plane.

19 is a flowchart illustrating one embodiment of a process for coding an LIC bit plane

Figure 20 is a block diagram of one embodiment of a preview and context model for less important data.

Figure 21 is a block diagram of one embodiment of a context model that provides adjustment for head bits.

Figure 22 illustrates memory usage for one embodiment of a context model with adjustments to all neighbors and parents.

23 is a block diagram of one embodiment of a context model for sign bits.

Figure 24 illustrates one embodiment of parallel coding for an LIC.

25 is a block diagram of an embodiment of the printer front end.

26 is a block diagram of an embodiment of the printer rear end.

27 is a block diagram of another embodiment of the printer rear end.

28 is a block diagram of one embodiment of an integrated circuit (IC) chip including printer compression / decompression.

Figure 29 illustrates the basic timing of the system during printing.

30 illustrates a page buffer of a page.

31 shows the bandwidth buffer of the page

Figure 32 shows a timing diagram of the encoding describing the requirements of concurrent memory access.

Figure 33 shows how circular addressing can be used to handle write data larger than the read data.

Figure 34 shows a pair of encoder and decoder.

35 shows an embodiment of a binary context model.

36 shows another embodiment of the binary context model.

Figure 37 shows neighboring coefficients of all coefficients of a coding unit.

Figure 38 shows a pyramid alignment based on MSE alignment.

Figure 39 shows the MSE alignment of the wavelet coefficients.

DESCRIPTION OF THE REFERENCE NUMERALS

4001, 4002, 4007, 4008, 4009, 4010, 4011:

4003, 4004, 4006: Mux

4005: Register file

401, 402: filter unit

403, 404, 405, 406:

407, 408: Mux

The present invention discloses a method and apparatus for performing compression and / or reconstruction. In one embodiment, the invention includes a system having a buffer, a wavelet transform unit, and a coder. The wavelet transform unit has an input coupled to the buffer for performing wavelet transform on the pixels stored in the buffer and for generating coefficients on the output. The coder is connected to the wavelet transform unit to encode the transformed pixel received from the buffer.

Methods and apparatus for compression and reconstruction are described. In the following description, various details such as the type of delay, the bit rate, the form of the filter, and the like will be described. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail in order to avoid obscuring the invention.

Portions of the following detailed description are provided in terms of algorithms and code representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which one of ordinary skill in the art of data processing techniques will best convey to others skilled in the art the nature of their work. Where the algorithm is generally thought of as a consistent sequence of steps leading to the desired result. The steps require physically treating the physical quantity. Although not usually inevitable, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise processed. Primarily for reasons of universal use, these signals are sometimes referred to as bits, values, elements, symbols, letters, terms, and numbers.

However, it should be borne in mind that these terms and similar terms relate to appropriate physical quantities and are merely convenient labels applied to these quantities. The discussion using terms such as processing, computing, computing, or determining or indicating through the present invention, unless explicitly stated otherwise specifically in the following discussion, Related to the operation and processing of an in-memory computer system or similar electronic computing device that processes and transforms the data being processed into other data similarly represented in physical quantities within the memory or registers of the computer system or other information storage, .

The invention also relates to an apparatus for performing the operations herein. The apparatus includes a general purpose computer specifically configured for the required purpose or selectively operated and reconfigured by a computer program stored in the computer. Such computer programs include, but are not limited to, floppy disks, optical disks, CD-ROMs, magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, Stored in readable computer storage media, such as any type of media suitable for storage, each coupled to a computer system bus. The algorithms and indications provided herein are not inherently related to any particular computer or other device. Many general purpose machines can be used as a program as disclosed herein, or more conveniently configured to perform the steps of a required method. The structures required for many such machines come from the following description. In addition, the present invention does not describe any particular programming language. Many programming languages may be used to implement the invention described herein.

The following terms are used in the following description. Definitions of these various terms are included. However, the definitions provided are not limited in scope to what is known in the art. These definitions are provided to aid in understanding the present invention.

ABS coding: A parallel entropy coding method that uses simple code (e.g., executable code) for bit generation and probability prediction (e.g., probability prediction table) based on the codeword used. In one embodiment, the ABS coding also includes a method for multiplexing and demultiplexing streams from several coders.

Alignment: The degree of shifting of the transform coefficients of one frequency band for the remaining frequency bands.

Arithmetic coding: Shannon / Elias coding with limited precision, but not necessarily binary coder.

B-Coding: Binary entropy coder using finite state machine for compression. Unlike Hopper only coding, finite state machines are used to handle binary symbols well, and are useful for a range of input probabilities.

Binary entropy coder: A noise-free coder that is sometimes represented by the most probable symbol (mps) and the least likely symbol (lps), and performs a binary (yes / no) decision.

Binary-style: A coding form with edge-fill gray encoding for a particular context model and pixel.

Binary-type Context Model: Context model for 2-level and limited-level image data.

Bit-significance: A representation of a number, similar to a code size, comprising a head bit, if any, followed by a sign bit, followed by a tail bit.

Child-based order: scan order for two-dimensional images. This is similar to the raster order except for scanning for 2 * 2 blocks. Consider scanning for the parent frequency band in the raster sequence. Each coefficient will include four children. These children can be from top-left, top-right, bottom-left, bottom-right to the next parent and the next four children (children) set, and so forth, are ordered to the end of the line. The process then returns to the next two lines and ends at the bottom right corner. The line is not skipped. The child-based order is also referred to as the 2 * 2 block order.

Coefficient: Component after conversion

Components: Parts of a picture. This component constitutes a pixel. For example, the red, green, and blue bands are band components. Each individual pixel consists of red, green, and blue components. The component and component bands may contain some form of information with a spatial mapping to the image.

Context model: Conditionally probable information for entropy coding, enabling causal information about the current bit to be coded that provides time-thermally-learned information about the current bit. In a binary image, the possible context for a pixel is two pixels from the first two pixels in the same row and three pixels from the preceding row.

Disassembly level: Located in wavelet decomposition pyramid. This is directly related to resolution.

Efficient conversion: A transform that achieves the best energy compaction into a coefficient, using the smallest number of bits to represent the coefficients.

Embedded context model: A context model that separates context bins and generates levels of importance in a way that effective lossy compression is obtained when more important values are maintained.

Embedded with ordering: A special case for an embedded context model that orders compressed data with the most important data, without explicit labeling of importance.

Embedded Quantization: Quantization implied by a code stream. For example, if an important level is placed in order, from the most important to the least important, then the quantization is performed by a simple truncation of the code stream. The same function can be taken with tags, markers, pointers, or other signals. Multiple quantization may be performed on the picture at the decoding time, but only one embedded quantization may be performed at the encoding time.

Entropy Coder: An apparatus for encoding and decoding a current bit based on a probability estimate. An entropy coder can also be referred to as a multi-context binary entropy coder here. The context of the current bit is several configurations selected from the nearby bits and allows probability prediction for optimal representation of the current bit (or multi-bit). In one embodiment, the entropy coder may include a binary coder, a parallel run-length coder, or a hopper only coder.

Entropy point: A point in the coded data that begins with a known coding state. The decoder can begin decoding at this point without decoding the previous data. In most cases, this requires the context and the binary entropy coder to be reset to the initial state. The coded data for each coding unit starts at an entropy point.

Fixed-Length: A device that transforms a specific block of data into a specific block of compressed data, for example, block truncation coding (BTC) and some form of vector quantization (VQ). Fixed-length codes provide fixed-rate and fixed-size applications, but ratio-distortion performance is not as good as a variable-rate system.

Fixed-Rate: An application or system with a channel of limited bandwidth while maintaining a certain pixel ratio. In one embodiment, to achieve this goal, local average compression is performed rather than overall average compression. For example, MPEG requires a fixed-ratio.

Fixed-size: An application or system with a buffer of limited size. In one embodiment, to achieve this objective, an overall average compression is achieved. For example, it is a print buffer. (Applications can be fixed rate, fixed size, or both.)

Frequency band: Each frequency band describes a set of coefficients originating from the same sequence of filtering operations.

Head bit: In the bit-importance representation, the head bit is the size bit of the most significant bit to the first non-zero bit (including the first non-zero bit).

Hopper only coder: A fixed-length code that typically produces an integer bit for each symbol.

Priority level: A unit of coded data corresponding to the full bit-plane of the embedded data before compression. The importance level includes all the appropriate bit planes from the different coefficient frequency bands.

Least probable symbol (LPS): the result of a binary decision with a probability of less than 50%. When the two results are equal, it does not matter which one is indicated as mps or lps, as long as the encoder and decoder indicate the same.

Lossless / Noise / Reversible Coding: Compress data in a way that allows for complete reconstruction of the original data.

Lossy coding: coding of data that does not guarantee complete reconstruction of the original data. Changes to the original data may be performed in a manner that is either invisible or undetectable. Sometimes a fixed ratio is possible.

Most probable symbol (MPS): The result of a binary decision with a probability of more than 50%.

Nested transformations: Transforms where a single source sample point contributes to multiple coefficients at the same frequency. The samples include multiple wavelets and a Lapped Orthogonal Transform.

Parent coefficient: a coefficient or pixel in the next higher pyramid level that covers the current coefficient or a picture space of the same kind as a pixel. For example, the parent of one SD coefficient is the 2SD coefficient which is the parent of 3SD in Fig.

Probability estimation machine / module: part of a coding system that follows probability in context.

Progressive pixel depth A code stream that is ordered by deepening the bit-planes of the data at full image resolution.

Progressive pyramidal: A continuous resolution in which a lower angular resolution becomes two linear factors within each dimension (four factors in the region).

Q-coder; A binary arithmetic coder that can use additions instead of multiplications limited to discrete values and update the probabilities and probabilities limited to discrete values as the bits are output.

Raster order; The scan order for the entire two-dimensional image. Starting from the upper left corner, moving from left to right, then returning to the left of the next line, and finally ending at the lower right corner. The line is not skipped.

Reversible Transformation: In one embodiment, the variable transformation is an efficient transformation consisting of integer arithmetic in which the compression result of integer arithmetic can be reconstructed as an original.

For tail-bits or tail: bit-significance representation, tail bits are size bits that are less significant than the most significant non-zero bits.

Tile data segment: A portion of the code stream that fully describes one coding unit.

TS-conversion: a specific reversible wavelet filter pair with 2-6 conversions, a two-tap low-pass analysis filter and a six-tap high-pass analysis filter. The synthesis filter is a quadratic mirror of the analysis filter.

TT-Conversion: A specific reversible wavelet filter pair with 2-10 conversions, a two-tap low pass analysis filter and a 10-tap high pass analysis filter. The synthesis filter is a quadratic mirror of the analysis filter.

Integrated lossless / lossy: The same compression system provides a lossless or lossy reconfigurable code stream. In one embodiment of the present invention, this code stream is both possible with or without an encoder.

Wavelet filter: High and low pass synthesis and decomposition filters used in wavelet transform.

Wavelet transform: A transform that has both a frequency domain and a time (or space) domain constraint. In one embodiment, it is a transform with a high pass filter and a low pass filter. The resulting coefficients are extracted (strictly filtered) by two factors and the filter is applied to the low-pass coefficients.

Wavelet trees: coefficients associated with a single coefficient in the SS section of the highest-level decomposition, and pixel. The coefficient number is a function of the level number. Figure 1 shows the coefficients included in the wavelet tree. The length of the wavelet depends on the number of decomposition levels. For example, with one decomposition level, the wavelet tree spans four pixels, with two decomposition levels, to sixteen pixels. Table 1 below shows the number of pixels affected by wavelets for different levels. For two dimensions, each wavelet tree forms a subtree named SD, DD, and DS.

The span of the wavelet tree for different levels of decomposition. Width Height Total Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 2 2 44 4 168 8 6416 16 25632 32 102464 64 4096

[Outline of the present invention]

The present invention provides a compression / decompression system having an encoding unit and a decoding unit. The encoding unit encodes the input data to generate compressed data, while the decoding unit first decodes the encoded data to reconstruct the original input data. The input data includes various types of data such as an image (or video), audio, and the like. In one embodiment, the data is digital signal data, but digitized analog data, text data format, and other formats are possible. The source of the data may be a memory or channel of the encoding and / or decoding unit.

In the present invention, elements of the encoding unit and / or decoding unit may be implemented in hardware or software used on a computer system. The present invention provides a lossless compression / decompression system. The present invention can also be configured to perform lossy compression / decompression.

The system of the present invention employs fast lossy / lossless compression by a reversible wavelet described in more detail below. The system includes a printer, such as, for example, a laser printer. In one embodiment, the printer uses an inexpensive hard disk that stores a page, thereby reducing the amount of expensive RAM required. Compression matches the limited bandwidth of the hard disk or other storage device to the larger bandwidth required by the print engine. The coding technique of the present invention satisfies the high-speed, real-time requirements of printers and the present invention provides superior lossless or lossy compression as required by image characteristics and bursty nature of the hard disk.

The following detailed description shows a general overview of compression by the implementation of reversible wavelets, compressed frame store applications, color laser printers, and printer chips. The printer's rendering engine uses a hard disk for storage. Since the hard disk is later than the print engine, compression is used to provide rate matching. The display list description is also used to reduce the memory required for rendering. The rendering engine based on the display-list allows the compression system to handle the bandwidth of the picture independently. Although the present invention is described in terms of a printing system, the present invention is applicable to other systems in which compression and / or restoration are included as a part.

We also discuss the embedded uni-lossless / lossy compression system. The embedded nature of the system allows the quality to be determined by the transfer rate of the disk. For lossless compression, for an easily compressed image (e.g., most of the original in text and / or lines). A high-quality oil-loss compression is performed for an image that is hard to compress (for example, a natural image with noise and / or a halftone original).

A description of a system for lossless compression of color images and high quality lossy compression is provided in U.S. Patent Application Serial No. 08 / 642,518, filed May 3, 1996, entitled Compression and decompression with Wavelet Style and Binary Style Including Quantization by the Device-Dependent Parser And U.S. Patent Application Number Method and Apparatus for Reversible Color Conversion, filed on May 8, 1995.

[Reversible wavelet]

The present invention employs compression by reversible wavelets.

Wavelet decomposition

The present invention decomposes an image (in the form of image data) or other data signals initially using a reversible wavelet. In the present invention, the reversible wavelet transform involves implementing an accurate reconstruction system of integer arithmetic in which the signal of integer coefficients is reproduced without loss. The coefficient reversible transformation is that the determinant of the transformation matrix is 1 (or almost 1).

Using reversible wavelets, the present invention can provide finite precision arithmetic for lossless compression. The result generated by applying the reversible wavelet transform to the image data is a row of coefficients.

The reversible wavelet transform of the present invention can be implemented using a set of filters. In one embodiment, the filter implements a transform, referred to herein as a TS transform or a 2, 6 transform, as a two-tap lowpass filter and a six-tap highpass filter. In another embodiment, the filter implements a transform, referred to herein as a TT transform or a 2, 10 transform, as a two-tap low pass filter and a 10-tap high pass filter. These filters can be implemented using only add and subtract operations (plus hard wire bit shift).

The TT-transform has at least one advantage and at least one drawback to the TS transform. One advantage is that it provides better compression than TS conversion. The drawback of TT conversion is that longer 10-tap filters require higher hardware costs.

2D wavelet decomposition

Using the low-pass filter and the high-pass filter of the present invention, multi-resolution decomposition is performed. The number of configuration levels may vary and may be any number. However, the number of current decomposition levels is 2 to 8. The maximum number of levels is the log ₂ of the maximum value of the length or width of the input.

The most common way to perform a transformation on two-dimensional data, such as an image, is to separate the one-dimensional filter, that is, along the rows and then along the rows. The first level of decomposition is here the four different coefficient bands SS, DS, SD, and DD. The letters indicate the smooth (S) and detail (D) filters defined above, which correspond to the low (L) and high (H) pass filters, respectively. Thus, the SS band consists of the coefficients of the S filter in the row and column directions.

Each frequency subband of wavelet decomposition can be further decomposed. The most common is to further decompose only the SS frequency subbands and further include decomposition of the SS frequency subbands at each generated decomposition level. Such multiple decomposition is called pyramidal decomposition. SS, SD, DS, DD and the number of decomposition levels indicate each decomposition.

With the TS or TT transform of the present invention, pyramidal decomposition does not increase the coefficient magnitude.

When a reversible wavelet transform is applied to an image recursively, the first level of decomposition operates at the finest degree or resolution. At the first level, the picture is decomposed into four sub-pictures (e.g., sub-bands). Each subband represents a spatial frequency band. The first level subband is denoted as 1SS, 1SD, 1DS, 1DD. The process of decomposing the original image involves subsampling by two of the horizontal and vertical directions. Each of the first-level sub-bands 1SS, 1SD, 1DS, 1DD has a coefficient of 1/4 of the pixel (or coefficient) of the picture of the input.

The subband 1SS simultaneously includes low frequency horizontal information and low frequency vertical information. Typically, much of the image energy is concentrated in this subband. The subband 1SD includes low frequency horizontal information and high frequency vertical information (e.g., horizontal edge information). The subband 1DS includes high frequency horizontal information and low frequency vertical information (e.g., vertical edge information). The subband 1DD includes high frequency horizontal information and high frequency vertical information (e.g., texture or diagonal edge information).

Each of the subsequent second, third, and fourth sub-decomposition levels is generated by decomposing the low-frequency SS sub-band of the proceeding level. This first level subband 1SS is decomposed to produce the appropriate detailed second level subband 2SS, 2SD, 2DS, 2DD. Similarly, the subband 2SS is decomposed to generate the third level of detailed detailed levels 3SS, 3SD, 3DS, 3DD. The subband SS ₂ is also decomposed to produce the more detailed level 4SS, 4SD, 4DS, 4DD of the third level. Due to the two subsampling, each second level subband is 1/16 the size of the original image. At this level, each sample (e.g., pixel) shows the appropriate detail in the original image of the same location. Similarly, each third level subband is 1/64 the size of the original picture. At this level, each pixel corresponds to relatively detailed detail in the original image of the same place. And each third level subband is 1/256 of the original image.

The decomposed image is physically smaller than the original image due to sampling, so the same memory used to store the original image can be used to store all decomposed subbands. In other words, the original picture and the decomposed sub-bands 1SS and 2SS are discarded and not stored in the three-level decomposition.

Although only four subband decomposition levels are described, additional levels may be developed depending on the needs of a particular system. Other transforms, such as DCT or linearly arranged subbands, may also define different parent-child relationships.

Pyramidal decomposition does not increase the coefficient magnitude with the wavelet filter of the present invention.

In other embodiments, other subbands other than SS may also be decomposed.

Structure of wavelet

There is a natural and useful tree structure for the wavelet coefficients of the pyramidal decomposition. The decomposition result of the subband is a single SS frequency subband corresponding to the last level of decomposition. On the other hand, there are as many SD, DS, and DD bands as there are levels. The tree structure defines the parent of the coefficient of the frequency band as a coefficient related to the same spatial position in the same frequency band of lower resolution.

In the present invention, each tree includes SS coefficients and three subtrees: DS, SD, and DD subtrees. The processing of the present invention is typically performed on three subtrees. The root of each tree is a very smooth coefficient. For a two-dimensional signal such as an image, there are three subtrees, each with four children. The tree is not limited to a two-dimensional signal hierarchically. For example, for a one-dimensional signal, each subtree has one child. The higher dimension follows from the first dimension and the second dimension.

The processing of the multi-resolution decomposition is performed using a filtering system. An example of a two-dimensional, two-level transformation implemented using a typical one-dimensional filter is disclosed in US patent application Ser. No. 08 / / RTI > and U.S. Patent Application Serial No. 08 / 498,036 entitled Reversible Wavelet Transform and an Embedded Codestream Manipulation, filed June 30,

Performing a constant wavelet transform

In the present invention, the wavelet transform is performed in two 1-D operations, horizontal and vertical. In one embodiment, four level decomposition is performed using TT transforms in the horizontal and vertical directions. In another embodiment, four level decomposition is performed using TS transforms instead.

The transformation of the present invention is computationally very efficient. In one embodiment, the invention directs on-chip and off-chip memory and computation performed by the transform to reduce the amount of bandwidth required.

Calculation sequence and data flow of the transformation

As discussed above in the present invention, the basic unit for calculating transforms is a wavelet tree. Assuming a four level translation, each wavelet tree is a 16 * 16 pixel block. The 16 * 16 pixel block (the four components of all CMYK pictures) is the input of the transform of the present invention and all possible calculations for generating coefficients are performed. (The inverse is similar. A 16 * 16 block of coefficients for each component is an input and all possible calculations are performed). Since the present invention employs nested transforms, neighboring trees are stored and used for computation. The boundary between the current wavelet tree and the previous neighboring information is called a seam here. The information that exists across the shim to perform the transform of the present invention is described in detail below.

Ordering the wavelet tree

In some applications (e.g., printing), since the coding unit of the present invention has a large width and a small height, the ordering of the wavelet tree for calculating the transform is important. In one embodiment, each coding unit includes 4096 * 256 pixels.

In the following discussion, each coding unit includes 4096 * 256 pixels. However, the ordering described below can be applied to other sizes of coding. 2A illustrates an order similar to a raster order. Here, this order is called the long seam transfer order. According to FIG. 2A, the thick line represents the amount of data that exists across the shim and shows how much storage is needed to calculate the transform. This data is proportional to one wavelet tree for horizontal conversion, but not to the width of the image for vertical conversion (4096 in this example). The use of demand memory is required to store this data. However, since it is close to the raster order, during the inverse transformation, as soon as the horizontal row of the wavelet tree is converted to a pixel, the data can be output from the transform (e.g., from the printer application to the printer).

Figure 2B illustrates another embodiment of an order referred to herein as a short seam order. Sim storage is proportional to the height of the coding unit for horizontal transform (256 in this example) and one wavelet tree for vertical transform. This greatly reduces the amount of memory required and allows on-chip storage to be realized.

FIG. 2C illustrates another shot order. With a storage cost proportional to one or more wavelet trees, the number of consecutive pixels processed in the raster order increases. This or a similar example allows efficient use of the EDO RAM and fast page mode of the band buffer at little or no extra cost in the sim memory. Efficiency is obtained by the fact that most memory is optimized to access neighboring memory locations. Thus, any increase in the use of neighboring memory access due to the SIMOORD results in more efficient memory usage.

Calculation of 1 Wavelet

The following equations define TS-transform and TT-transform. For the x (n) input, the output of the low pass filter, the smooth signal s (n), the high pass filter, and the detail signal d (n) are calculated as shown in equation (1).

The inverse transformation is shown in Equation (2) below.

Where p (n) is Lt; / RTI >

The TS-transform and the TT-transform are different in the definition of t (n).

About TS-conversion

Lt; / RTI >

About TT-Conversion

.

In the following discussion, the notation [.] Means to discard the finite number and is sometimes called the floor function.

TS-conversion

The effect of using a 6-tap filter and a 2-tap filter at even positions is that 3 pieces of information should be stored. The 6-tap filter requires 2 delays. The two-tap filter requires one delay, so the results can be centered on the result of the six-tap filter. Specifically, the partial results of 2 s (·) and 1 d (·) values or d (·) calculations should be stored. The storage of these values is the same regardless of whether the particular filtering operation is shim or not.

3A to 3H show the results of applying the TS conversion to the four-level conversion of the wavelet tree of the present invention, respectively. In these figures, the output of the low-pass filter is denoted by s (smooth). The output of the high-pass filter is denoted by d (detail). B represents the median value used to calculate d, which is the value of x (2n) -x (2n + 1). The B value is used during the constant transformation. For inverse transforms, the d value that is not used in any computation is stored in that location. sd indicates that the coefficient is first the result of a horizontal low-pass filter followed by a vertical high-pass filter. The meanings of ds, dd, ss, dB, sB are similar. The thick square corresponds to 256 input pixels. The shaded s, ds, ss values are calculated as the previous wavelet tree and stored for use in the current wavelet tree.

For the positive conversion, the inputs of the levels 2, 3 and 4 of the conversion are the ss coefficients of the previous level. The sd, ds, and dd coefficients are over, so they can be output when calculated. The inverse transform performs all calculations in the reverse order for the level (first level, then 3, 2, and finally 1), and for vertical (first) and horizontal (second). During the conversion, the flow of data in the positive and negative directions is the same and only the calculations are different.

TS-conversion hardware

4A is a block diagram of one embodiment of a forward / inverse filter unit used to implement a one-dimensional filter. It only shows the memory and the calculation unit and hardwired shift is not shown. According to Fig. 4A, the filter unit 400 processes both positive and inverse transforms. Other embodiments may use separate units for positive and inverse transformation. For the constant conversion, the magnitude n input is used and the s and d outputs are generated. For the inverse transform, the s and d inputs are used and another output is generated.

An adder 4001 is coupled to receive an n-bit input and adds it to produce an output of x (2n + 2) + x (2n + 3). The adder 4002 subtracts one n-bit input from the other n-bit inputs and outputs the amount of x (2n + 2) -x (2n + 3). The outputs of adders 4001 and 4002 are connected to one input of multiplexers 4003 and 4004, respectively. The other inputs of mux 4003 and 4004 are connected to receive s and d inputs, respectively. In one embodiment, the s input is n bits, while the d input is greater than n bits.

The outputs of MUX 4003 and 4004 are controlled by a forward / reverse control signal indicating whether the filter is in the forward or reverse mode. In positive or inverse mode, the output of Mux 4003 is equal to s (n + 1). On the other hand, the output of the Mux 4004 is equal to p (n + 1) in the normal mode and d (n + 1) in the inverse mode. The outputs of muxes 4003 and 4004 are coupled to the input of register file 4005 along with the feedback of s (n) output at mux 4006. The register file 4005 contains an entry for each component of the length of one wavelet tree. The data typically passes through the register file 4005. Based on the spatial position, the input of register file 4005 is delayed until output. The address input controls the output of the register file 4005. In one embodiment, the register file 4005 includes two memory banks, has one port per bank, and is used for back-and-forth access in a ping-pong format between two memory banks.

The output of the MUX 4003 is also the s output of the filter unit.

The output of the register file 4005 is coupled to the input of the MUX 4006 along with the data of the external seam buffer in 4020. Output 4006A includes s (n-1) where the output of mux 4003 is delayed twice. Output 4006B includes s (n) delayed by s (n + 1). Output 4006C includes p (n) for positive mode and d (n) for inverse mode. The Mux 4006 is also controlled to provide the seam buffered 4021 buffer data that is buffered.

Output 4006C is connected to one input of adders 4008 and 4009. The other inputs of the adders 4008 and 4009 are the outputs of the MUX 4015. Mux 4015 handles boundary conditions. At the boundary, MUX 4015 outputs 0 wired to one input of it. Wired zeros may be converted to use different values in other embodiments. (N + 1) of one input by subtracting s (n-1) from s (n + 1) To be added to s (n-1) of the input.

The adder 4008 adds the output 4006C of the mux 4006 to the output of the mux 4015 to generate the d output of the filter unit.

The adder 4009 subtracts the output 4006C of the mux 4006 from the output of the mux 4015. [ The output of adder 4009 is added to s (n) on output 4006B of mux 4006 by adder 4010 to produce an n-bit output of the filter unit. The output of the adder 4009 is also subtracted from s (n) of the output 4006B of the mux 4006 by the adder 4011 to output another n-bit output of the filter unit in the reverse direction.

For a shim longer than one wavelet tree, the shim data is stored in the on-chip SRAM (static RAM) or external memory instead of the register file 4005. The Mux 4006 provides access to and from this additional memory.

Most of the hardware cost of the filter unit 4000 is due to the register file 4005. The total amount of memory required depends on the number of filtering units. In one embodiment, a total of 60 positions are required to store three values (s, s, d or ss, ss, sd). When more filter units are required, less memory is required for each. Thus, the hardware cost of using multiple filter units is low.

Fast inverse conversions reduce latency between the end of decoding and the start of data output operations such as printing. This reduces the amount of space memory required for reconstruction and enables large coding units. Quick Conversion allows the filter to handle bursts of data when greater bandwidth is available and allows the conversion context model to be updated more quickly when the context model expedites data with look- Provide a lot of data. If the regular transform can not keep up with the context model during encoding, the disk bandwidth being coded will be wasted and the time to start printing will be delayed. Control and data flow are simplified by having multiple filters.

4B is a block diagram of one embodiment of a first level correct transform according to the present invention. According to FIG. 4B, two filter units 401 and 402 as shown in FIG. 4A perform the first level of translation. The filter unit 401 performs a level 1 horizontal conversion, while the filter unit 402 performs a level 1 vertical conversion. In one embodiment, the first level of translation operates on 2 * 2 blocks of input. 4 registers 403-406 operate as a delay unit for delaying the output of the filter unit 401. [ This is called a child-based order. Register 403 receives the S output of filter unit 401, while registers 404 and 405 receive the d output. The output of register 404 is connected to the input of register 406. The outputs of registers 403 and 406 are connected to the inputs of mux 407, while the s output of filter unit 401 and the output of register 405 are connected to the inputs of mux 408. The two muxes 407 and 408 select the input of the filter unit 402 from the delayed coefficient outputs of the filter unit 401.

The filter unit 401 operates continuously for two vertically adjacent input pairs. This produces the coefficients input to filter unit 402 with the appropriate delays provided by registers 403-406 for each component. Three of the four results are output immediately, and the ss output is further processed.

The first level positive transmission operates on a group of four pixels that are 2 * 2 grouped. For discussion, the first row contains pixels a and b, while the second row contains pixels c and d. The operation of the first level 4 conversion of FIG. 4B is as follows. During the first cycle, the horizontal transform is applied to the a and b pixels processed by the filter unit 401. The filter unit 401 generates S _ab stored in the register 403 and D _ab stored in the registers 404 and 405. In the next cycle, pixels c and d are processed by filter unit 401 to perform the horizontal conversion. The result of applying the filter unit is to generate S _cd stored in the register 403 and D _cd stored in the registers 404 and 405. In this cycle, S _{cd in} register 403 and D _cd in register 405 are processed by a filter unit 402 that performs a vertical pass of the transform and generates SS and SD. Further, during the second cycle, the value of D _ab shifts from register 404 to register 406. In the next cycle, the D _ab value of the register 406 and the D _cd value of the register 405 are processed by the filter unit 402 and generate the DS and DD outputs. In the same cycle, the filter unit 401 processes the a and b pixels of the next 2 * 2 block.

5 is a block diagram of one embodiment of a constant transform according to the present invention. According to Fig. 5, level 1 conversion 502 performs level 1 conversion. In one embodiment, the level 1 conversion performs the level 1 conversion of FIG. 4B. The filter unit 505 processes the 2, 3, and 4 levels of the conversion. The memory 503 stores the ss coefficient until a sufficient coefficient is obtained to perform the conversion. The number of coefficients that need to be stored is shown in Table 2 below (each location stores the coefficients of each part).

ss delay memory Between levels Required memory 1 and 22 and 33 and 4 9 position 8 position 4 position

The order unit 504 multiplexes appropriate inputs to the filter unit 505. The input buffer 501 and the output buffer 506 are required to match between the transmission order required by the conversion and the order required by the bandwidth buffer or context model.

For the inverse transform, the flow of data is reversed so that a level 4 inverse transform is performed and performed in the order of level 3, level 2, and level 1 transform. The output of the level 2 transform is applied to the first level translating hardware of level 1 transform 502. Vertical filtering is also performed before horizontal filtering. Since the horizontal and vertical filtering is the same except that one direction needs access to the shim side memory, reversing the data flow can be done with a small amount of multiplexing. Before the inverse transform, the two-byte coefficient needs to be converted to the usual two's complement numbers in the embedded form with two signal bits.

The elements shown in Figures 4B and 5 can also be used for TT-transform.

Conversion timing

The conversion timing of the constant conversion in Fig. 5 is based on the timing of the individual filter units. The first filter unit, filter unit 401, calculates a horizontal level 1 conversion, while the second filter unit, filter unit 402, calculates a vertical level 1 conversion. The third filter unit, filter unit 505, computes or is idle in conversions of levels 2 to 4.

In one embodiment, the third filter unit 505 computes the horizontal shift for even clock cycles when no idle and calculates the vertical shift for odd clock cycles. The timing of the inverse transform is similar (but reversed).

In the following example, 2 * 2 blocks in the wavelet tree are processed in the raster order transpose. If 2 * 2 blocks in the wavelet tree are processed as raster orders, less input / output (I / O) buffering may be required to support fast page mode / extended data output (EDO) DRAM.

6 is a timing diagram when coefficients are output. The next timing is for each pixel. There are four components for each pixel.

TT-conversion

Figures 7A-7H show the results of each one-dimensional filtering operation of the TT-transform. The square represents the coefficient of the single wavelet tree corresponding to the currently processed input pixel and the shaded portion represents the stored coefficient from the previous tree. The value marked B is the stored intermediate value (and is different between adjacent samples). TT-conversion is similar to TS-conversion but requires more storage.

8 is a block diagram of a 10-tap forward / reverse filter unit. Wired shifts and rounding offsets are not shown to avoid obscuring the present invention. The Mux 806 of FIG. 8 may also be used for mirroring at the transformation boundary. To implement mirroring, it is also necessary to zero the d input and multiplex the s (n + 2) inputs of the overlapping units.

According to FIG. 8, adders 801 and 802 are connected to receive 2 n bit inputs during a full pass of the filter unit. The adder 801 adds the 2 n bit input and outputs the value connected to the input of the Mux 803. An adder 802 subtracts one input from the other and generates an output at one input of the multiplexer 804. Muxes 803 and 804 are also coupled to receive the s and d inputs, respectively, for inverse mode operation of the filter unit. The output of mux 803 is an n-bit input such as s (n + 2) while the output of mux 804 is n + 1 bits for p (n + 2) Input.

The two outputs of MUX 803 and 804 are connected to the input of memory 805. Outputs 806A and 806D-F of mux 806 are also connected to inputs of memory 805. [ In one embodiment, the memory 805 includes a register file or SRAM operating in a ping-pong fashion with two banks and one port per bank. An address is coupled to the input of the memory to control the output generated by the MUX 806. In one embodiment, the address stores 16 or 28 positions per component.

The output of memory 805 is coupled to the input of mux 806 along with the external buffer data received from shim buffer 820. The output 806A of the mux 806 includes s (n + 1) which is a delayed version of s (n + 2) output from the mux 803. Output 806B of the Mux 806 includes s (n), which is a delayed version of the output of the Mux 803 twice for the positive pass. The output 806C of the Mux 806 includes p (n), which is a delayed version of the output of the Mux 806 twice for a positive pass, and d (n), which is a delayed version of the output of the Mux 804 for the reverse pass. Output 806D includes s (n-2), which is the four-delayed version of the output of the Mux 803. Output 806E of mux 806 includes s (n-1) which is a delayed version of mux 803 output three times. Finally, output 806F contains a delayed version of p (n + 1) for the output of the mux 804 for the forward pass and d (n + 1) of the delayed version of the output of the mux 804 for the reverse pass .

The overlap unit 807 is coupled to receive the output of the multiplexer 803 along with the outputs 806A, D, and E of the multiplexer 806. [ In response to this input, the superposition unit 807 generates t (n). One embodiment of the overlapping unit is shown in Fig.

The output t (n) of the superposition unit 807 is connected to the inputs of the adders 808 and 809. An adder 808 adds t (n) to the output 806C of the multiplexer 806 to generate the D output of the filter unit. The adder 809 subtracts the output 806C of the mux 806 from t (n). The output of the adder 809 is connected to the respective inputs of the adders 810 and 811. The adder 810 adds the output of the adder 809 to the output 806B of the mux 806 to produce one of the n-bit outputs of the filter when operating as an inverse filter unit. An adder 811 subtracts the output of the adder 809 from the output 806B of the mux 806 to produce another output of the filter unit when operating as an inverse filter unit.

Figure 9 is a block diagram of one embodiment of an overlay unit for the forward / inverse filter of Figure 8; 9, the overlapping unit includes adders 901-906, multiplexers 907-909, and a divider 910. [ Multiplexers and partitions can be hardwired shifted.

The overlap unit of FIG. 9 calculates t (n) for the TT transformation described above. 9, adder 901 is coupled to receive an input of s (n + 2) and subtracts it from the input of s (n-2) to generate an output coupled to one input of adder 903. An adder 902 is connected to receive the s (n-1) input and subtracts the s (n + 1) input therefrom. The output of the adder 902 is connected to the inputs of a multiplier 907 and a multiplier 908. The multiplier 907 multiplies its input by two. In one embodiment, the multiplication is performed by shifting the input bits one position to the left. The output of the multiplier 907 is connected to the other input of the adder 903.

The multiplier 908 multiplies the output of the adder 902 by 16. In one embodiment, the multiplication is performed by shifting the bits outputted from the adder 902 to the left by 4 bits. The output of multiplier 908 is connected to one input of adder 905. The output of adder 903 is coupled to one input of adder 904 and to the input of multiplier 909.

The multiplier 909 multiplies the output of the adder 903 by 2. In one embodiment, this multiplication is performed by shifting the bits output from the adder 903 by one bit to the left. The output of multiplier 909 is coupled to another input of adder 904. The output of adder 904 is coupled to another input of adder 905. The output of the adder 905 is connected to the input of the adder 906 and the adder 906 adds the wired input 32 thereto. The output of adder 906 is connected to the input of divider 910. Divider 910 divides the input by 64. In one embodiment, this division is performed by shifting the input bits to the right by 6 bits. The output of divider 910 includes a t (n) output. Figure 9 also shows the current value of each output on the line.

In both the reversible TS-transform and the TT-transform, as in the S-transform, the low-pass filter is implemented such that the range of the input signal x (n) is equal to the output signal s (n). That is, there is no growth in the soft output. If the input signal is b bits deep, the soft output is also b bits. For example, if the signal is an 8-bit image, the output of the low-pass filter is also 8 bits. This is an important property of pyramidal systems in which the soft output is also restored by, for example, continuously applying a low-pass filter. In prior art systems, the range of the output signal is greater than the range of the input signal, making it difficult to apply the filter successively. Also, since there is no system error due to rounding in the integer implementation of the transformation, all errors in the lossy system can be controlled by quantization. In addition, the low-pass filter has only two taps and therefore becomes a non-overlapping filter. This property is important for hardware implementation.

[Embedded Ordering]

In the present invention, coefficients generated as a result of wavelet decomposition are entropy-coded. In the present invention, the coefficients are initially subjected to embedded ordering, where the coefficients are arranged in a visually important order or, more generally, are arranged for certain error metrics (e.g., distortion metrics). The error or distortion metrics include, for example, peak error and mean square error (MSE). In addition, the ordering can be performed to give a choice of bit-significance spatial locations, relationships to database queries, directionality (vertical, horizontal, diagonal, etc.).

Ordering of the data is performed to generate an embedded quantization of the code stream. In the present invention, a two ordering system is used. The first is for ordering the coefficients, and the second is for ordering the binary values in the coefficients. The ordering of the present invention then generates a bitstream to be encoded with a binary entropy coder.

Bit-importance representation

If the original component is unsigned (the coefficients output from at least one detail filter are signed), most transform coefficients are signed numbers. In one embodiment, the embedded order used for the binary value in the coefficients depends on the bit plane. The coefficients are expressed in bit-importance expressions before coding. The bit-significance is a sign-magnitude representation in which the sign bit is encoded with the first non-zero size bit rather than the most significant bit (MSB). That is, the sign bit follows the first non-zero size bit rather than proceeding through all size bits. The sign bit is also considered to be in the same bit plane as the most significant non-zero size bit.

The bit-significance format represents a number using three sets of bits: head, tail, and sign. The head bits are all zero bits from the MSB to the first non-zero size bits, including the first non-zero size bits. The bit-plane where the first nonzero magnitude bit occurs defines the significance of the coefficient. The tail bit set includes size bits from after the first non-zero size bit to the LSB. The sign bit only represents a sign, where 0 represents a positive sign and 1 represents a negative sign. A number with non-zero bits as MSB, such as +/- 2 ⁿ , has only one head bit. The zero coefficient has no tail and no sign bit. Table 3 shows all possible values of the bit coefficients ranging from -7 to 8. [

Bitwise significance representation of 4-bit values Decimal 2's complement sign size bit-significance -8-7-6-5-4-3-2-101234567 10001001 1111 11 1 11010 1110 11 1 01011 1101 11 0 11100 1100 11 0 01101 1011 0 11 11110 1010 0 11 01111 1001 0 0 110000 0000 0 0 00001 0001 0 0 100010 0010 0 10 00011 0011 0 10 10100 0100 10 0 00101 0101 10 0 10110 0110 10 1 00111 0111 10 1 1

In Table 3, the bit significance representation shown in each column includes 1 or 2 bits. In the case of two bits, the first bit is the first one bit followed by the sign bit.

The order used when the value is a non-negative integer, such as occurs for a pixel density, is a bit plane order (e.g., from the most significant bit plane to the least significant bit plane). In embodiments where a negative integer of two's complement is also allowed, the embedded order of the sign bit is equal to the non-first non-zero bit of the absolute value of the integer. The sign bit is thus not considered until a non-zero bit is encoded. For example, using the sign size representation, a 16-bit number-7

1000000000000111

to be. Based on the bit-plane, the first 12 decision is non-critical or zero. The first 1-bit occurs at the 13th decision. Next, the sign bit (negative) is encoded. After the sign bit is encoded, the tail bit is processed. The 15th and 16th decisions are all 1s.

Since the coefficients are encoded in the most significant bit plane to the least significant bit plane, the number of bit planes in the data must be determined. In the present invention, this is accomplished by calculating the upper bound of the magnitude of the coefficient value that is calculated from the data or derived from the depth of the image and the coefficients of the filter. For example, if the upper boundary is 149, there is an 8-bit significance or 8-bit plane. For the speed of the software, bit plane coding is not used. In another embodiment, the bit planes are encoded only when the coefficients become significant as a binary number.

Counting order

The present invention aligns the coefficients relative to each other before bit-plane coding. This is because the coefficients of the other frequency subbands represent different frequencies similar to FFT or DCT. By sorting the coefficients, the present invention controls quantization. The less heavily quantized coefficients are sorted into earlier bit-planes (e.g., shifted left). Thus, if the stream is truncated, these coefficients have more bits that define them than heavier quantized coefficients.

In one embodiment, the coefficients are aligned for best rate-distortion performance in terms of SNR or MSE. There are many possible alignments, including those that are near optimal in terms of statistical error metrics such as MSE. Instead, the alignment allows for physiscovial quantization of the coefficient data. Alignment has a significant impact on the evolution of image quality (or, in other words, the rate-distortion curve), but negatively impacts the final compression ratio of a lossless system. Other arrangements may correspond to specific coefficient quantization, region of interest fidelity coding, or resolution progression alignment.

Alignment can be signaled at the header of the compressed data or fixed for a particular application (i.e., the system has only one alignment). Alignment of coefficients of different sizes is known to the coder or decoder and does not affect entropy coder efficiency.

The bit depths of various coefficients in two-level TT-transform and TS-transform decomposition of an input image having b bits per pixel are shown in Fig. 12 is an embodiment of a frequency band multiplier used in coefficient alignment in the present invention. To align the coefficients, the 1-DD coefficient magnitude is used as a reference and is shifted over this magnitude. The n shift is to multiply by 2 ⁿ .

In one embodiment, coefficients are shifted for the largest magnitude of coefficients to produce an alignment of all coefficients of the image. The sorted coefficients are processed from the highest significance level to the lowest significance level in the bit-plane called the importance level. The sign is encoded along with the last head bit of each coefficient. The sign bit is at any significance level with the last head bit. It is important to note that alignment only controls the order in which the bits are sent to the entropy coder. The actual padding, shift, store, or coding of the extra zero bits is not performed.

Table 4 illustrates one embodiment of the number of sorts for sorting the coefficients.

Counting order 1-DD criteria 1 left, 1 left, 2 left, 2 left, 3 left, 3 left, 1 left, 1 left, 1 left, 2 left, 4

Alignment of coefficients of different sizes is known to the coder and decoder and does not affect the entropy coder efficiency.

Coding units in the same data set may have different alignment.

Ordering code streams and context models

Figure 10 illustrates the ordering of a code stream and the ordering in a coding unit. Referring to FIG. 10, following the header 1001, the coding unit 1002 comes in order from the top band to the bottom. (The header 1001 is optional in applications coded for a single picture type.) Each coding unit includes a topmost data 1003, an important data 1004, and a least significant data 1005.

The context model determines both the order in which the data is encoded and the conditions used for a particular bit of data. Ordering is considered first. The highest level of data ordering has already been described above. The data is divided into the most important data and the important data. The former is called the most important chunk (MIC) and is encoded without loss in the conversion order. The latter is referred to here as the least important chunk (LIC) and is an embedded and integrated lossless / .

The order in which the coefficients are processed during each bit-plane is from low resolution to high resolution (from low frequency to high frequency). Each in-plane coefficient subband coder is from a high level (low resolution, low frequency) to a low level (high resolution, high frequency). Within each frequency subband, the coding is in the defined order. In one embodiment, the order may be a raster order, a 2 * 2 block order, an S-order, a Peano scan order, or the like.

In the case of 4-level decomposition using the code stream of FIG. 3, the order is as follows.

4-SS, 4-DS, 4-SD, 4-DD, 3 -DS, 3 -SD, 3 -DD, DD

One embodiment of the context model used in the present invention will be described next. This model uses the bits in the coding unit based on the dependence of the spatial spectrum of the coefficients. The available binary values of the neighboring coefficients and the parent coefficients are used to generate the context. However, the context is the cause of the decoding capability and a small number for efficient application.

The present invention provides a context model for modeling a bit stream generated by a coefficient of an embedded bit-importance order of a binary entropy coder.

Figure 37 shows neighboring coefficients of all coefficients of a coding unit. 37, neighboring coefficients are specified by a clear location mark (e.g., N = north, NE = northeast, etc.). Given a coefficient and current bit- Can use any information from any coding unit prior to a given bit-plane. The parent coefficient of the current coefficient is also used in this context model.

The head bit is the most compressible data. Thus, rather than using neighboring or sub-coefficients to determine the context for the current bit of the current coefficient, the information may be used to enhance the compression of the two signals < RTI ID = 0.0 > Bit. This information can be stored in memory or can be calculated from neighboring coefficients or parent coefficients.

Implement embedding to save to disk

One embodiment of the embedded architecture of the present invention is based on the fact that at the start of data coding, all the band buffer memories are filled with data, so that no extra space is available in the band to use as the motion spatial memory. The present invention records some of the less important data into memory for later embeddedness. In the present invention, the data to be embedded is stored in memory and this is less important data. More important data is directly encoded. The least significant data includes the number of least significant bits.

In one embodiment, if a portion of each coefficient is written back into memory for later encoding, the head and tail bits must be known as well as the code bits for proper coding. In one embodiment, two or more signal bits (e.g., 3, 4, 5, etc.) are used to indicate head, tail, and sign bit information.

In one embodiment where 8-bit memory locations are used, the two signal bits represent head, tail, and sign bit information. With the use of two signal bits, the least significant six priority levels can be written back into memory with two signal bits. 1 signal bit indicates whether the most significant bit of the 6 significance level is the head or the tail bit. If the first signal bit indicates that the head bit is a head bit, then the second signal bit is the sign of the coefficient. If, on the other hand, the first signal bit indicates that the most significant bit of data rewritten in memory is a tail bit, the second signal bit is a free signal bit, for example if the most significant tail bit is the first tail bit, Additional tail information, such as < RTI ID = 0.0 > a < / RTI >

13A shows the coefficients divided by the most important data 1301 called the MIC and the less important data 1302 called the LIC. In one embodiment, the MIC contains the six higher order bits of each coefficient, while the LIC contains six lower order bits. The most important data 1301 is sent in the context model and is immediately encoded in the count order. It is not necessary to buffer in this external memory for this data. The less important data 1302 is written to a memory (e.g., RAM) and later encoded and embedded by an order. In addition, two signal bits of data are also recorded in the memory. The signal bit 1303 indicates whether the most significant bit recorded in the memory is a head bit. The signal bit 1304 indicates the sign of the coefficient or indicates whether or not the first tail bit is included in the data. The signal bits may be stored in conjunction with less significant data 1302 or may be stored in memory or other memory locations associated with memory storing less critical data 1302 so that the signal bits associated with each portion of the coefficients are identified .

The example in Table 5 shows the use of two signal bits. The columns of Table 5 line up in the data form of Figure 13A. The sign bit is denoted by S, the tail bit is denoted by T, the unrelated bit is denoted by x, and the tail-on bit value is denoted by h or t. In Table 5, h = 0 and t = 1 for the signal bits. In another embodiment, the rules may be reversed. In one embodiment, the sign bit of 0 in Table 5 represents a positive sign whereas the sign bit of 1 in Table 5 represents a negative sign. The opposite assignment can also be used. Since the sign bit is always kept as the first on bit, it can be encoded at the same time as the embedding.

size Most Significant Less Significant Signal Bits (Lossless) (Bit Plane Built-In) 1xxxx1xxxxx1xxxxxx1xxxxxxx1xxxxxxxx1xxxxxxxxx x 0000000 01TTTT h sx 0000000 1TTTTT h sS 0000001 TTTTTT t 0S 000001T TTTTTT t 1S 00001TT TTTTTT t 1S 0001TTT TTTTTT t 1

In Table 5 above, T represents the corresponding bit of the coefficient and may be 0 or 1.

In one embodiment, during decoding, when the most important data is decoded, it is written to memory and at the same time the appropriate two signal bits are written to the memory to initialize the memory to store the less important data. (Depending on the alignment of the coefficients, some of the most important data may also be stored in the second byte.) With this initialization, decoding less important data in a 1-bit plane requires one byte per coefficient Less) to read and write. When coefficients are read and entered in the inverse transform, they are transformed into a normal number form (eg, a two's complement form).

In addition to having the most important data and less important data, there is also data that is discarded or quantized during encoding. The coefficients are divided by the quantization scale factor 2 ^Q-1 . (The quantization of coefficients is described in the JPEG standard.) In the present invention, the quantization is a power of 2 since division is made by discarding the bit plane. For example, Q = 1 indicates division by 1 and thus the coefficients do not change. On the other hand, Q = 2 represents the division by 2, which means that the 1-bit plane is discarded. This partitioning can be accomplished using shifts. (For example, shifted by one bit position with respect to Q = 2). Figures 13B and 13C illustrate the most important and less important data formats when considering quantization and coefficient alignment of different subbands.

FIG. 13B shows a case of lossless data in which data is not discarded. According to the convention of JPEG, since the actual coefficient is divided by 1 (lossless), this is called quantization Q = 1. The most important data is shown without shading, while the least important data is shaded.

Fig. 13C is like discarding the bit plane by dividing by 2 when the 1-bit plane of data is discarded (i.e., Q = 2). This abandoned bit plane is black.

In addition to those shown in Figures 13B and 13C, the most important data also includes SS coefficients. Although the coefficients are represented by 8-bit data, the use of the reversible color space requires 9-bit data and increases the size of the color coefficient by one bit.

In the present invention, the sign bit context model includes encoding the sign after the last head bit. There are three contexts for the sign, depending on whether the N-factor is positive or negative or where the sign has not yet been encoded. Instead, a context can be used for the code or the code can always be encoded at 50%.

Coding order of wavelet coefficients

One embodiment of the ordering of coding for wavelet coefficients is summarized in the following pseudo-code.

When the most important data is coded, the first bit plane of less important data, which is not all composed of zero head bits, is determined for each coefficient. This allows the encoder and decoder to preview the entire bit plane of less important data. This is particularly useful for coding units of black and white data where all information is in the K coefficient and CMY coefficients are all zero. In particular, if R2 (7) is the longest run length code possible, not coding the bit planes separately will aid the compression ratio. (In U.S. Patent Nos. 5,381,145 and 5,583,500 for a description of the R2 code.) However, if a 4 parallel coding core operates in synchronism with a component, the processing speed is determined by the component having the most bitplanes to be encoded. The core assigned to the other component of the uncoded bit plane is idle.

A flowchart illustrating an embodiment of the operation of the above pseudo code is shown in Fig. Referring to FIG. 14, the context model begins by encoding the most significant chunk (MIC) (processing block 1401). After coding the MIC, the processing logic encodes the position of the first LIC bit plane into data (processing block 1402). This is for the entire coding unit. If the LIC has a 6 bit plane, either the 0,1,2,3,4,5 or 6 bit planes will hold the data. The processing logic then sets the current LIC bitplane variable to the first LIC bit plane with data (processing block 1403).

Next, the test determines whether all LIC bit planes with data have been coded (processing block 1404). If so, processing ends and processing logic encodes the LIC bit plane (processing block 1405) and sets the current LIC bit plane variable to the next LIC bit plane (processing block 1406). The processing loop then returns to processing block 1404 again.

Coding order of the most important data

An embodiment of the coding order of the most important data is as follows.

The most important data is treated as one wavelet tree at a time. To be repeated, it is not embedded. MIC look-ahead determines the bit-plane, which is zero head bits for all non-SS coefficients in the wavelet tree. In one embodiment, a 4-bit number is sufficient to identify the first bit plane for individually encoding. In another embodiment shown in FIG. 15, one bit is used to indicate that all non-SS coefficients 1501 in the second decomposition (hatched region) are 0, and all non-SS coefficients 1503 in the first decomposition are zero, Is used. These two bits are used in addition to the four bits used to specify the first bit plane.

In another embodiment, the tree preview is used where the SS coefficients are encoded and then the first bit plane with non-zero head bits is hatched for all the trees.

If adjustment is used for the SS and first bit plane coding to account for the context re-visit delay, the actual coding / decoding of the bits of the SS coefficients (which is 9 bits if reversible color space is used) have. If the condition is not used, it does not need to happen alternately.

As discussed above, the context model of the present invention uses a preview. One embodiment of the preview is employed in the most important data, the MIC (most important chunk). In one embodiment, 6 bits are used for each tree, as shown in Fig. Four are used for the maximum bit plane, one for level 0, one for all, and one for level 1, all zeros. If the maximum bit plane is zero, then two extra bits are unnecessary, but this is not important. Otherwise, one adaptive coding decision is used to determine (isolated) zero / non-zero. For non-zero coefficients, they are further specified by

One M-ary operation to determine the value and sign of the coefficients (overall: 2 cycles per coefficient)

. One adaptive coding decision is used to determine ± 1 / ratio ± 1. The second cycle is used to obtain a sign with a magnitude of 1 and a sign with a magnitude greater than 1 (all: 3 cycles per coefficient).

. Similarly, for all four cycles per coefficient, it can be ± 1 / ratio ± 1, ± 2,3 / ratio ± 2,3, and so on.

Next Steps

Specifying a bit or bits may be adaptive coding and coding with a 50% probability or simply copying the bits to the encoded data stream.

If all or most of the bit planes are individually coded, some level of translation may have unused bit planes due to alignment. Unused bit planes are not encoded. There are many options for treating bits as the context delay of the head and tail bits. One method is to alternate the three coefficients: DD, SD, and DS. The sign bit of the non-zero coefficient is encoded at the end of the coefficient. Since all of the most important data is always lossless, it is not necessary to follow the first on bit exactly.

One embodiment of a flowchart describing the pseudo code for encoding the MIC is shown in FIG. Referring to FIG. 16, the process begins with processing logic that sets the current tree to the first tree (processing block 1601). The processing logic then encodes the SS coefficients (processing block 1602). After encoding the coefficients, the processing logic either encodes the position of the first bit plane into data in the tree's MIC (processing block 1603) .

The processing logic then tests whether the MIC of the entire tree is zero (processing block 1604). If the MIC of the entire tree is zero, processing continues at processing block 1614; otherwise, processing moves to processing block 1605 where processing logic sets the current coefficient to the first non-SS coefficient of the tree.

After setting the current coefficient to the first non-SS coefficient of the tree, processing logic sets the current bit plane to the first bit plane having data (processing block 1606). Processing logic then encodes the current coefficient bit of the current bit plane (processing block 1607). Thereafter, the processing logic tests whether all bit planes have been encoded (processing block 1608). If not all bit planes have been coded, processing logic sets the current bit plane to the next bit plane (processing block 1609) and moves to processing block 1607. If all bit planes have been encoded, the processing logic tests whether the current coefficient is zero (processing block 1610). If the current coefficient is not zero, the processing logic codes the sign bit (processing block 1611) and the processing moves to processing block 1613. If the current coefficient is zero, the processing logic moves to processing block 1613.

At processing block 1613, the processing logic tests whether all coefficients of the tree have been encoded. If all the coefficients of the tree have not been coded, then processing logic sets the current coefficient to the next coefficient in the tree (processing block 1612) and processing moves to processing block 1606. If all the coefficients of the tree have been coded, the processing logic tests whether all of the trees have been coded (processing block 1614). If all the trees have been coded, the processing ends; otherwise, processing moves to processing block 1615 where processing logic sets the current tree to the next tree and processing moves to processing block 1602.

Figure 17 is a block diagram of one embodiment of a formatting unit and context model used during the coding pass of the most important data. According to FIG. 1, the barrel shifter 1701 is connected to receive the quantization level used to prevent the size of the coefficient and the most important data during encoding from exceeding the maximum disk bandwidth, to ensure lossless reconstruction. Thus, the quantization level controls the barrel shifter 1701. In one embodiment, the barrel shifter 1701 shifts the magnitude bits by 0, 1, 2, or 3 to support 1, 2, 4, or 8 quantization. In another embodiment, a lower or higher number of quantisations such as only two quantisations are supported.

The output of the barrel shift 1701 includes the less significant 6-bit plane of order and the remainder of the higher order bits, which is the most important data. In another embodiment, a simple separation mechanism is used to generate these two outputs.

The two outputs of the balrel shifter 1701 are input to a first bit plane unit 1702 to determine which bit plane has data. The first bit plane unit 1702 is used to find the bit plane with the first on-bit to the entire coding unit (FIG. 10) for use in processing less critical data. The other bit plane unit 1706 is also connected to receive the most significant data output from the barrel shifter 1701. The first bit plane unit 1706 is used for each tree when processing more important data. One embodiment of the first bit plane is described below with reference to FIG.

The barrel shifter 1701 is also coupled to comparison units 1703 and 1704 to perform two comparison functions for the most important data in order to generate 2-bit signal information for less important data. The comparison unit 1703 determines whether the most significant data is equal to zero, thereby indicating whether the tail bit has already been generated (i.e., whether it is still coded in the tail). The output of comparison unit 1703 is a tail-on bit. The comparison unit 1704 determines whether the most important data is equal to one. If the most important data is equal to 1, the output from Table 5 above is zero. The output of the comparison unit 1704 is connected to one input of the multiplexer 1705. The other input of the multiplexer 1705 is coupled to receive the sign bit. The selection input of the multiplexer 1705 is controlled by the output of the comparison unit 1703 so that if the output of the comparison unit 1703 indicates that the bits are tail bits, the output of the multiplexer 1705 is the first tail bit. However, if the output of the comparison unit 1703 indicates that the bit is a head bit, then the MUX 1705 is controlled to output a sign.

In one embodiment, comparison units 1703 and 1704 may be implemented using a simple bit comparator.

The memory 1707 is coupled to receive the sign bit, the most significant data output of the barrel shifter 1701, and the output of the bit plane unit 1706. Memory 1707 may be used to delay the coefficients to obtain the parent and neighbor information for the condition. The organization of memory 1707 is discussed below.

Context model (CM) 1710-1712 provides code, head, tail and other bit conditions. Each of these context models is described below.

Figure 18 illustrates one embodiment of the first bit plane. According to FIG. 18, a first bit plane unit 1800 includes an OR gate coupled to receive a coefficient and a feedback of the output of the register 1802. The output of the OR gate 1801 is connected to the input of the register 1802. The register 1802 is controlled by the start indication of the tree / coding unit. The output of the register 1802 is connected to a priority encoder 1803. The output of the priority encoder 1803 is the output of the first bit plane unit 1800.

At the start, the register 1802 is cleared. Each bit of the register 1802 is ORed with each bit of the coefficient using the gate 1801. For each bit of the coefficient of zero, the value of the register 1802 holds its current value and outputs it to the priority encoder. The output from the gate 1801 to the register 1802 is 1, and it is output to the priority encoder 1803. The priority encoder 1803 positions the first one and it is the first bit plane of the coefficient with one.

Processing order of less important data

Each bit plane for LID (least important data) is processed as follows.

***** P74 *****

One embodiment for coding the LIC bit planes is shown in the flowchart of Fig. Coding of the LIC bit planes begins with the processing logic that sets the current tree to the first tree (processing block 1901). The processing logic then sets the current coefficient to the first non-SS coefficient of the tree (processing block 1902). After setting the current coefficient to the first non-SS coefficient in the tree, the processing logic tests whether the coding is in the start of the preview section (processing block 1903). If the coding process is at the start of the preview section, the processing logic performs a preview (processing block 1904) and continues at processing block 1905. If the coding process is not at the start of the preview section, the processing logic immediately goes to processing block 1905 and determines whether the preview is active.

If the preview is active, processing continues at processing block 1909 where processing logic determines whether all coefficients of the tree have been coded. If all the coefficients of the tree have been coded, processing continues at processing block 1913; otherwise, processing logic sets the current coefficient to the next coefficient in the tree after the preview section (processing block 1910) and moves to processing block 1903.

If the preview is not active, the processing logic encodes the head or tail bit (processing block 1906) and then tests whether the first non-zero bit has been received (processing block 1907). If the first non-zero bit has not been received, processing continues at processing block 1911. If the first non-zero bit has been received, processing continues at processing block 1908 where the processing logic codes the sign bit and then proceeds to processing block 1911.

At processing block 1911, the processing logic determines whether all coefficients of the tree have been coded. If all the coefficients of the tree have not been coded, processing logic sets the current coefficient to the next coefficient in the tree (processing block 1912) and moves to processing block 1903. If all the coefficients of the tree have been coded, go to processing block 1913 where the processing logic tests whether all of the trees have been coded. If all the trees have not been coded, processing logic sets the current tree to the next tree (processing block 1914) and continues at processing block 1902. If all the trees are coded, the process ends.

Treating a wavelet tree at a time may not be important, but it is convenient because it allows data to be read and written with such orders. Once the data is processed by the wavelet tree, the bits up to the context delay can be accommodated by alternating between DD, SD, and DS coefficients (alternating between subtrees). Otherwise, one subband can be coded at a time. Regardless of the order selected, unused head / tail bits due to alignment of other subbands are not encoded and do not require an idle cycle.

Figure 20 is a block diagram of one embodiment of a context model of preview and less important data. In one embodiment, the most important data and less important data use the same context model (CM), which provides modulation of the sign, head, and tail bits.

Referring to FIG. 20, the context model 2001-1003 is connected to input data. The sign context model 2001 is coupled to receive a tail-on bit, a sign / first tail bit signal, and data. Head bit context model 2002 is coupled to receive tail-on bit data. The tail bit context model 2003 is coupled to receive a tail-on bit, a sign / first tail bit signal, and data. In response to their input, each context model 2001-2003 generates a context.

Context generated by context model 2001-2003 is connected to input of mux 2004. Mux 2004 is controlled by the previous bits and the bit importance representation itself. The head context model 2002 is used until one bit is seen in the data input. The sign context model 2001 is used until the last bit is the first 1 bit of the head. Then, the tail context model 2003 is used.

Mux 2004 output = head? Unit 2005 and a first-in / first-out (FIFO) buffer 2006. = Head? Unit 2005 tests whether the current context is a head bit context having 0 head bits for the neighbor and the parent. If all the contexts are in the head, = head? The signal of unit 2005 deletes the FIFO 2006.

Context and results are buffered in FIFO 2006 or other memory in the preview section. At the end of the interval, a preview decision and / or an individual decision are encoded if necessary. If the coefficients are processed as one wavelet tree at a time, the FIFO of the preview can be a single FIFO used for all subbands, or multiple FIFOs used for each subband can be used.

If it is convenient to reduce multiplexing, the most important data can also be previewed. However, using both the preview and the first bit plane in each tree may be somewhat unnecessary.

When a core assigned to one component codes a sign bit, the core allocated to another component that does not code the sign bit in the same bit plane is idle. Thus, up to four clock cycles can be used for the sign bit if each core encodes the sign bit of the other bit plane. In one embodiment, there are up to six heads or tail bits per coefficient.

One possible timing problem is that the disk is idle while the MIC is sufficiently compressed to decode that data portion. If the bandwidth buffer has enough memory bandwidth, the preview can be used to process the most important data faster. Less critical data can then have a head start. It is also acceptable if the disk has a burst transfer rate higher than the maximum sustained rate. Hard disks usually have critical buffers and pre-reading them into this buffer removes idle time.

Partial adjustment of the context model

The adjustments used in the context model depend on the hardware cost versus the trade-off of compression. Thus, in the next section, a number of options are provided for the designer to consider.

Context model of SS factor

In one embodiment of the context model, the SS coefficients are not encoded. Since they only constitute 1/256 of the original data, there is little gain to code them. If they need to be coded, they can be handled by Gray coding, by adjusting for the previous bit of the same coefficient, and / or the corresponding bit of the previous coefficient.

The context model of the first bit plane information

The 4 bits of the first bit plane information for the most important data of each wavelet tree can be handled similarly in the SS coefficients. This increases the original data size by only 1/512. In one embodiment, due to their small size compared to the original data, they may not be encoded or may perform gray coding and adjustment.

Similarly, if six bits are used according to FIG. 15, they can be handled like SS coefficients.

Head bit's context model

Figure 21 is a block diagram of one embodiment of a context model that provides adjustment for head bits. According to Fig. 21, the context model 2100 includes a shift register such as that in the bit plane context model. The important difference is that instead of using the previous coefficients from the current bit plane, it is adjusted based on tail-on information using previously encoded information in all previous bit planes and the current bit plane. Also, some bits identify the bit plane coding rate or bit plane group coding rate or the coding rate of the subband or subband group generated by the importance level and subband bucketing.

21, the context model includes two inputs: a current importance level 2110 and a coefficient 2111 from memory. The current importance level 2110 is coupled to the tail-on information / bit generator block 2101 and the input of the importance level and subband bucketing block. The coefficients from memory are also coupled to block 2101 and registers 2103-2106.

Block 2101 takes a coefficient and determines whether there is one bit. In one embodiment, 2101 also determines where one bit is present. The output of block 2101 is one or two bits based on the tail-on information. In one embodiment, the tail-information relates to whether a bit of the first non-zero size is observed (e.g., whether the first on-bit is observed) and if so, how many bit- do. Table 6 describes the tail-information bits.

Definition of tail information Tail Justice 0123 On-bit is not observed First on-bit is in last bit plane First on-bit is before 2 or 3 bit planes First on-bit is before 3 or more bit planes

From the 2-bit tail information, the 1-bit tail-on value is synthesized to indicate whether the tail information is zero. In one embodiment, the tail-information and tail-on bits are updated immediately after the coefficients are encoded. In another embodiment, updating may occur later to enable parallel context generation.

Also, two bits can be used to indicate the level of importance being encoded. The first 2-bit plane uses the value 0, the second 2-bit plane uses the value 1, the third 2-bit plane uses the value 2, and the remaining bit planes use 3. There is also run-length encoding of bits, which are all zero head bits.

The context 10 bits of the head bit include two bits of information from the parent and the west coefficients, respectively, one bit information from the north, east, south west, and south coefficients, and two bits of importance level information.

In one embodiment, tail information is not used for any or all frequency bands. This allows the frequency band to be decoded without decoding its parent in advance.

In another embodiment, one alignment is used to assign the bit planes of each frequency band to the importance level. It uses a second alignment to determine the parent's tail-on information, which uses fewer parent bits than is actually encoded. This allows certain bit planes of the frequency band to be decoded without decoding the corresponding bit planes of the same significance level (Fig. 38). For example, an image can be encoded in a pyramid alignment. But is encoded into parent tail-on information based on MSE alignment (Figure 39). This allows the decoder to decode with pyramid alignment, simulate MSE alignment, or simulate any alignment between the pyramid and the MSE.

According to Fig. 21, the output of block 2101 is connected to the inputs of registers 2103-2106. Registers 2103-2106 accumulate neighboring data. For example, the Up / Left shift register maintains a bit during the line, which is the current coefficient above. The current shift register contains the bits of the current line of the coefficient, while the lower / right shift register 2105 contains the line from the line immediately below the shift register. Finally, the parent register 2106 holds the parent data. The output of the shift register constitutes a context.

The importance level and the output of bucketting block 2102 may also be used for context. When subbands and other levels are encoded in the same context, they become part of the context. In such a case, the output of block 2102 combines with the output of registers 2103-2106 to form a context. Otherwise, the context only includes the output of registers 2103-2106.

The output of the context model 2100 is also a bit.

Coding can be done by alternating between the DD, SD, and DS coefficients and allows bits up to the context delay (alternating between subtrees) to use the data in the current bit plane.

Memory is needed to store the coefficients needed for adjustment (Figure 17). The use of memory for one embodiment of the context model with adjustments to all neighbors and parents is shown in FIG. Assume a short shorthand order. (You can use external memory to support long shorthand orders, which requires additional memory storage and bandwidth).

Adjustment to higher-level parents is particularly costly. The level 4 DD coefficients of a given tree are not calculated up to 16 trees after most level 1 DD coefficients of the tree. Also, storing the total coefficients that are later encoded (unhatched portions in FIG. 22) is more expensive than simply storing the tail-on information (netted portion in FIG. 22) for later use in adjustment. Adjusting for the west information in the same tree and the parent without data from the western tree reduces the amount of memory required. If you can not get parent or west information, it is useful to copy north or east information.

The context model of the sign bit

The context model that provides control over the sign bits is simple. Knowing the sign of the above pixel can be used for adjustment. (R2 (0) is used.) Alternatively, no coding (R2 (0) can be used for all sign bits) is not performed if the sign of the above pixel is not known

23 is a block diagram illustrating an embodiment of a context model for sign bits. 23, the MUX 2301 receives the northern sign bit 2303 and the 0 bit 2304 (wired) and is controlled by the north tail on bit 2302 to output the north sign bit 2303 if the north tail on bit 2302 is 1, Output. Thus, the north pixel supplies the north tail-on bit 2302 and the north sign bit 2303 and provides the context for the south pixel of the north pixel.

Tailbit's Context Model

No adjustments are used for tail bits. In one embodiment, a fixed probability state is used, and a probability update is not used. Table 7 shows three options of code used for tail bits. The second option using R2 (1) and R2 (0) is a good choice.

Probability state (code) used for tail bits Bit of tail 1 2 3 4, ... Option 1 Option 2 Option 3 R2 (0) R2 (0) R2 (0) R2 (0) R2 (0) R2 (0)

In one embodiment, a good golden ratio code for a probability of M = 60% L = 40% is:

Input codeword

MMM 00

MML 110

ML 01

LM 10

SS 111

Context bean summary

The minimum number of context beans that can be used in the system is: SS, the first bit plane of each tree, and the sign and tail bits are not encoded (code R2 (0) is used). There must be logic to select the R2 (0) code even though the PEM state or most probable symbol (MPS) bits do not need to be stored. Thus, depending on how this is counted, the hardware cost is zero or one context bin. Adaptive coding should be used for head bits. For less important data, the adjustment to the bit plane is not important since one bit plane is encoded at a time. For the most important data, the first bit plane of each wavelet tree is sufficiently shortened by the number of bit planes so adjustment to the bit planes is not important. It is less clear what the usefulness of the control on subbands is, but this will also be ignored in the minimal context example here. The tail-on bits of 3 neighbors and one parent may be used for the entire 4 bits (16 context beans). One additional context bean can be used for previewing. (It may be more convenient to create a margin for the preview by mapping the two head context beans together. Memory size is still a power of 2.)

With four cores (requiring four contexts to be replicated), two context memory banks per core, the minimum number of context beans to use is 128, depending on how the uncoded context is counted and whether the two head contexts are mapped together. Lt; / RTI >

A system with an abundant amount of control is as follows.

. For the SS (9-bit) and the first bit plane (4 bits), use a total of 52 context beans with 4 context beans per bit (they can be divided into banks and they do not need to be replicated)

. The tail bits are not encoded, but both R2 (0) and R2 (1) are used. Depending on how this is counted, this is a 0, 1, 2 context bean.

. Two adaptation contexts and one no code context are used for sign bits.

The head bit can use 8 bits from neighbor / parent and 2 bits for subband / bit plane information (1024 context beans).

. 1 Context is used for preview.

Another embodiment of the context model is disclosed in US patent application Ser. No. 09 / 954,856, filed June 30, 1995, which is incorporated by reference herein in its entirety, including embodiments of code / size units for transforming input coefficients into sign / U.S. Patent Application Serial No. 08 / 498,695 entitled Codestream and U.S. Patent Application Serial No. 08 / 498,036 entitled Reversible Wavelet Transform and Embedded Codestream Manipulation filed on June 30, 1995, and Compression and No. 08 / 642,518, titled Decompression with Wavelet Style and Binary Style, Including Quantization by Device-Dependent Parsar, and U.S. Patent Application No. 08 / 642,518, entitled Compression / Decompression Using Reversible Embedded Wavelets, filed May 3, 643,268.

The context model provides context for entropy coding of data. In one embodiment, all entropy coding performed by the present invention is performed by a binary entropy coder. A single coder can be used to generate a single output code stream. Alternatively, multiple (physical or virtual) coder may be employed to generate multiple (physical or virtual) data streams.

M-ary coding of LIC

Figure 24 illustrates the use of M-ary coding for LIC. M-ary for reduced coding acts as a preview. First, examine the state of the next eight coefficients. If there is something in the head, entropy coding is performed on the head bit and all head bits of the entropy are encoded, one per cycle, until all the bits in 8 are encoded. Referring to FIG. 24, a head bit of 1 is encoded in the first and third cycles, while a head bit of 0 is encoded in the second and fourth cycles. Once all of the head bits are entropy encoded, the sign and tail bits are encoded in the same cycle. For example, in FIG. 24, a code followed by a head bit and a tail bit are encoded in the fifth cycle. In this way, the number of total cycles is reduced.

[Application example of printing system of the present invention]

25 is a block diagram of one embodiment of the printer front end. Referring to FIG. 25, a renderer 2501 receives data in the form of a page rendering language or a display list. The renderer 2501 may include raster image processing. For each position (e.g., dots), the renderer 2501 determines its color (e.g., black / white, 8-bit-RBG values, 8-bit CMYK values in accordance with the application). The output of the renderer 2501 is a set of pixels that are formatted into bands and stored in a band buffer (memory) 2503.

In another embodiment, a page presentation language (PDL), such as Adobe Postscript or Microsoft Window GDI, is presented in the display list. The display list is used to generate a band of pixels. In this embodiment, the pixel represents a continuous-tone value and the halftoning and dithering required by the print engine are performed after reconstruction.

In the present invention, the memory used in the band buffer 2503 is also used as a working space for compression (without increasing the required memory). Both of these uses will be described in more detail below.

A compressor 2504 compresses each band of pixels. If the input of the compressor 2504 is a halftone or trembling pixel, then the compressor 2504 will continue to operate, but the compression made will not be satisfactory for wavelet processing. A binary context model can be used for halftone or trembling images. The compressor 2504 records the compressed data on the disk 2505. The disk 2505 may be a hard disk. In another embodiment, the disc may be a random access memory (RAM), a flash memory, an optical disc, a tape, any form of storage, any type of communication channel.

26 is a block diagram of an embodiment of the printer rear end. 26, the rear end of the printer 2500 includes a restorer 2602 connected to the disk 2505, a band buffer (memory) 2603, and a print engine 2604. The restoring unit 2602 reads and restores the compressed data from the hard disk 2505. The restored data is stored in the band buffer (memory) 2603 in the form of pixels. The band buffer 2603 is the same memory as the band buffer 2503 which operates as the operating space of the compressor 2504. The restorer 2602 sufficiently fills the band buffer 2603 so that the pixel can be transmitted to the print engine 2604 in real time.

Figure 27 is another embodiment that includes options. 27, the pixel from the reconstructor 2602 goes to the band buffer 2603 via the enhancement block 2705, while the other information, which is not the pixel (partial coefficient), is directly sent to the band buffer 2603. [ The enhancement block 2705 performs functions such as interpolation, smoothness, error distribution, halftoning, and dithering.

The necessary bandwidth between the reconstructor 2602 and the band buffer 2603 allows the reconstructor 2602 to write the transform coefficients to the band buffer 2603 and to access the band buffer 2603 to obtain a certain coefficient, And then write them back to the band buffer 2603. As the operation space memory, the band buffer 2603 is small. For example, if the full page image is 64 megabytes and the bandwidth buffer 2603 is 16 megabytes, it can be regarded as a small working space memory.

In one embodiment, an A4 image at 400 dpi with 32 bits / pixel (four 8-bit components, CMYK) requires a data rate of approximately 8 Mbytes / s from the band buffer 2603 to the print engine 2604 do. The transfer speed of the exemplary hard disk is about 2 Mbytes per second (for example, 1.7 to 3.5 Mbytes / s). Thus, a typical compression ratio of about 4: 1 is required to match the bandwidth of the disk 2601 to the bandwidth of the printer. In one embodiment, compressor 2504 in Fig. 25 and reconstructor 2602 in Fig. 26 or 27 are included in a single integrated circuit chip.

28 is a block diagram of one embodiment of an integrated circuit (IC) chip including printer compression / decompression. According to Fig. 28, the pixel data interface 2801 generates an address for reading pixel data from the band buffer and writing it to the band buffer. An optional reversible color space 2802 can be included to perform the reversible color space conversion. The coefficient data interface 2804 generates an address for reading and writing coefficients and combines the 2-byte coefficients as appropriate. The coefficient data interface 2804 along with the pixel data interface 2801 handles any line buffering or coefficient buffering in external memory. The use of the coefficient data interface 2804 and the reversible color space will be described in more detail below.

A double arrow indicates that the data can flow in either direction. For example, when compressing data, data flows through the other components of the IC chip from left to right. On the other hand, when restoring data, the data generally flows from right to left.

When coding the data, the pixel data from the pixel data interface 2801 or reversible color space 2802 (if included) is received by the wavelet transform block 2803 which performs wavelet transform on the pixel data. In one embodiment, the transform performed by wavelet transform block 2803 is a nested wavelet transform. It provides energy condensation for lossless and lossy image compression. For lossy compression, block boundary artifacts that annoy JPEG were avoided. When properly aligned, the filter coefficients are normalized and scale quantization provides good lossy compression results. In one embodiment, the wavelet transform block 2803 performs a 2,6 transform. In another embodiment, the wavelet transform block 2803 performs a 2,10 transform. The wavelet transform block 2803 performs other well known transforms. Various implementations of the wavelet transform block 2803 are discussed in more detail below.

The coefficient output of the wavelet transform block 2803 is written back to the memory (e.g., the band buffer) via the coefficient data interface 2804 for later coding. In one embodiment, the data written back into the memory is less important and is described in detail below. Such data is later re-read and encoded in the IC chip.

The coefficient output received from the wavelet transform block 2803 or via the coefficient data interface is provided to the context model 2805. The context model 2805 provides a context for encoding (decoding) data using an encoder / decoder 2806. In one embodiment, the context model 2805 supports sending data directly to the coding. In this way, the context model 2805 operates as the most important context model. The architecture for implementing various context models has been described above.

In one embodiment, the encoder / decoder 2806 includes a high-speed parallel coder. A fast parallel coder handles multiple bits in parallel. In one embodiment, a fast parallel coder is implemented in a VLSI hardware or a multi-processor computer without sacrificing compression performance. One embodiment of a high-speed parallel coder used in the present invention is described in U.S. Patent No. 5,381,145 entitled Method and Apparatus for Parallel Decoding and Encoding of Data, filed on January 10, 1995.

In another embodiment, the binary entropy coder includes one in a Q-coder, a QM-coder, a finite state machine coder, and so on. Q and QM-coder are well-known and efficient binary entropy coders. A finite state machine (FSM) coder provides a simple conversion from a probability output to a compressed bitstream. In one embodiment, a finite state machine coder is implemented using a table look-up for both the decoder and the encoder. Various probability prediction methods can be used with such finite state machine coder. In one embodiment, the finite state machine coder of the present invention includes a B-coder as defined in U.S. Patent No. 5,272,478, entitled Method and Apparatus for Entropy Coding,

The output of the encoder / decoder 2806 is coupled to an encoded data interface 2807 that provides an interface to a disc or other storage medium or other channel.

The encoded data interface 2807 receives and transmits the encoded data from the disc. In one embodiment, if a SCSI controller is included in the needle, it can be implemented at this point. In another embodiment, the encoded data interface 2807 communicates with an external SCSI controller. Non-SCSI storage or communication is used.

During reconstruction, the encoded data is received by the encoder / decoder 2806 from the disk (or other memory storage or channel) via the encoded data interface 2807 and reconstructed there by the context of the context model 2805. The coefficients resulting from the reconstruction are inversely transformed by the wavelet transform block 2803. (The wavelet transform block 2803 performs all of the inverse transform in one embodiment, but in another embodiment, the two transforms can be performed by separate blocks.) The output of the transform block 2803 is a transform And a pixel output through the data interface 2801 to the band buffer.

The basic timing of the system during printing is shown in Fig. According to Fig. 29, the coded data of each coding unit is read from the disc. After reading as much data as possible and after a short delay, the coefficients are decoded. After decoding, an inverse wavelet transform is computed. After the conversion, the pixel is transmitted to the print engine. The netted portion of FIG. 29 shows when a different operation occurs for a specific coding unit.

Embedding coefficients for disk storage

Figure 10 shows the organization of the encoded data of the present invention. According to Fig. 10, the most important data 1003 is converted (not embedded) into a coefficient order immediately after being converted. Thus, this data need not be buffered. In one embodiment, the amount of the most important data 1003 is always limited to be readable from the disk.

The amount of less important data that is buffered, embedded, and recorded is determined by the transmission time. That is, the system reads data until the transfer time from the disk expires. The transfer rate of the disk determines how much data it holds. This rate is known and depends on the physical characteristics of the particular transmission.

Since it is difficult to compress the image, some data may be discarded during the encoding time. Data is represented as least significant data 1005. If there is no chance of reading the least important data even if the best disk transfer rate is given, there is no reason to store the data on disk. Data is not discarded for many pictures and perhaps most pictures.

The ordering of the encoded data and how it accomplishes is explained in more detail above.

In the following, we discuss bandwidth buffer management during compression and restoration, and then describe the embedded structure of the encoded data. The hardware implementation of the transformation, the context model, and the parallelization of the encoder / decoder is also described.

[Pixel and counter interface]

30 is an embodiment showing how pixel data is organized. According to Fig. 30, the page (image) 3000 is divided into bands 3001-3004. In one embodiment, page 3000 may include a page description language or a display list description of a page used to generate pixels of each band. In one embodiment, bands 3001-3004 are rasterized using a display list technique, respectively. Each band 3001-3004 is also divided into coding units (e.g., 3001A-D).

The advantage of using multiple coding units per band is that a portion of the band buffer (similar to ping-pong buffering) can be used for rotation as a workspace at restoration. In other words, one area of the pixel can be restored and stored in the band buffer and then sent to the printer, while the second area of the band buffer is used as the operating space to store the coefficients upon decoding and the third area is used as the coefficient Can be used to store pixels.

31 shows the band buffer 3101 of the page 3100. Fig. The band buffer 3101 is composed of a coding unit 3101A-D. The coding units 3101A and 3101B operate as the operating space of the restorer by storing the coefficients. The coding unit 3101C stores pixels output to the printer (or channel), and the coding unit 3101D functions as an operation space for the reconstructor by storing the next pixel.

A portion of the band buffer 3101 is used for rotation as the entire page 3100 is printed. For example, in the case of the next coding unit, the pixel of the coding unit 3101D is a pixel output to the printer. When such a phenomenon occurs, the coding units 3101B and 3101C are used as an operation space for a reconstructor for storing coefficients. At this time, the coding unit 3101A can also be used as a restoration operation space for storing the next pixel outputted to the printer.

In the present invention, the coefficient is larger than the pixel. Thus, twice as much memory is allocated to the motion space memory. In another embodiment, the band may be divided more or less than the coding unit. In one embodiment, for example, the bands are each divided into 8 coding units.

[Memory bandwidth]

The pixel data interface and the coefficient data interface effectively manage the band buffer memory. If high-speed page mode DRAM, Extended Data Out (EDO) DRAM, or other memory that facilitates continuous access is used, these interfaces transfer data from successive accesses to bursts of sufficient length to effectively use the potential bandwidth of memory Let's do it. Some small buffers may be used to support burst access to consecutive addresses.

32 shows a timing diagram of the encoding indicating the requirements of concurrent memory access. Referring to FIG. 32, the bandwidth required for decoding is as follows. In the previously mentioned embodiment, a pixel clock of 2 MHz, a component-clock of 8 MHz and a decoding clock of 32 MHz are used and the print engine requires 1 byte / component clock, Read 2 bytes per count and write 1 byte per fraction. If the conversion is performed at half the coding unit time, it requires 6 bytes / component clock. The speed of the conversion is limited by the bandwidth of the memory, not the computation time. If a bandwidth of 24 bytes / component clock is used, the conversion will be calculated in 1/8 coding unit time. The conversion requires additional bandwidth if the external memory is used as seams. In one embodiment, decoding of the coefficients requires writing of two bytes per component clock to the most significant part of the coded data. Decoding requires one byte of read and write per component clock for each bit plane of the less significant portion of the coded data. This may be less in other embodiments. If the two operations take place during half of the coding unit time, a bandwidth of 4 bytes and a bandwidth of 24 bytes are required per component clock, respectively. If external memory is used for context seam information, it will require significant bandwidth.

In one embodiment, the maximum burst mode transmission ratio is four memory accesses per component clock (one access per code clock). Therefore, for a 32-bit data bus, the maximum transmission ratio is slightly less than 16 bytes / component clock. For a 64-bit data bus, the maximum transmission rate is slightly less than 32 bytes / component clock.

Reduced LIC memory bandwidth requirements

Each bit of each coefficient in the LIC requires reading and writing of the external memory during decoding (the encoding is read only). These memory accesses describe the majority of the required memory bandwidth. In one embodiment, the invention stores coefficients using less than 8 bits when it is possible to reduce the bandwidth requirement instead of storing the LIC coefficients in 8 bits.

Table 8 shows the bits required to store the LIC coefficients during decoding, and indicates how much memory is required to store the LIC coefficients for decoding each bit plane. According to Table 8, when the MIC is executed, 1 bit of tail-on bit per coefficient is recorded. Which is written in the bit plane 5 is again read out in the bit plane 4. That is, 2-3 bits including a tail on bit, a value of bit 5, and a sign bit when bit 5 is 1 are written and read. The ratio is for each bit plane that contains the ratio of the coefficients. This is further clarified by Fig. 13B. According to FIG. 13B, since all coefficients from DD1 to DS4 and the SD4 subband have data in bit plane 5 (indicated by shading), bit plane 5 holds coefficients from all included subbands. Bit plane zero only holds coefficients from the subband of DD1. As shown in Table 8, bit planes 4 and 5 hold coefficients from all subbands, with a percentage of 100%, while bit plane 0 only retains 25% of the coefficients (DD1 subband). As the decoding proceeds further, some bit planes end before reaching bit plane zero.

The bits needed to store the LIC coefficients during decoding Percentage of bit plane coefficients in MSE alignment Record Read Bits / Count Context (Write / Read) - * 5 1 Tail On - / 100% 5 4 2-3 Tail On, Bit 5, 100% / 100% 4 3 3-4 tail on, bit 4 ... 5, sign? 100% / 99% 3 2 4-5 tail on, bit 3 ... 5, sign? 99% / 96% 2 1 5-6 Tail On, Bit 2 ... 5, sign? 96% / 82% 1 0 6-7 Tail on, bit 1 ... 5, sign? 82% / 25% 0 - + 7-8 tail on, bit 0 ... 5, sign? 25% / -

Here, * indicates recording during MIC (Most Important Chunck) processing and † indicates reading during inverse conversion.

In Table 8, decoding of the bit planes does not occur at the beginning of decoding. Therefore, only one bit (bit / count) per coefficient is read out to determine whether it is head or tail. As the decoding continues, the number of bits per coefficient increases.

FIG. 33 shows how circular addressing treats recorded data that is larger than the read data. This occurs because the result of the processing produces more bits than are generally read for writing. According to Fig. 33, the process starts by writing 1 bit per coefficient, which is 1/8 of the memory space. Then, one bit per coefficient is read and 2-3 bits per coefficient are written, then 2-3 bits per coefficient are read and 3-4 bits per coefficient are written. This process continues until all the data has been processed.

There are several choices for simplifying hardware devices. Instead of always using the least bit, a bit of about 1, 2, 4, 6 or 8 can be used which causes a bit to be consumed because of a certain size. Even if the sign bit is not coded or poorly known in the LIC, the space for the sign bit can always be used.

The choice to further reduce the memory bandwidth is to not store tail-on bits if they are not needed. For example, when writing bit plane 0, there are six bits that are head or tail bits. If there is a non-zero bit among these bits, the tail-on becomes true so that it is not necessary to store the tail-on value, and the sign bit is stored as the seventh bit.

The memory bandwidth of the MIC can also be reduced by a variable length storage method. Using the minimum value of the bits instead of always using 8 bits per coefficient causes savings. Storing the 6 bit preview value (shown in FIG. 15) instead of the zero coefficient bit enables the use of more efficient memory.

[Reversible color space]

The present invention is completely reversible at the time of integer operation by selectively performing the switching of the reversible color space enabling the switching between the two color spaces. That is, the color space data to be converted is reversed to obtain all existing data even though rounding or truncation occurs during the forward conversion processing. The reversible color space is disclosed in U.S. Patent Application Serial No. 08 / 436,662, entitled Method and Apparatus for Reversible Color Conversion filed on May 8, 1995, assigned to the assignee of the present invention.

Color space conversion provides the advantage of conflicting color space without loss of ability to provide lossless results. In the case of lossless, conflicting color spaces provide free inertia to improve compression. For a lossy code, contradictory color spaces provide luminance information that is quantized less than color information, enabling high quality. When a reversible color space is used in the transform of the present invention, the luminance and chrominance numbers are superior to subsampling for lossy compression, allowing lossless compression to continue.

When the reversible color space is used, the most significant bits of the 8-bit luminance component and the 9-bit color component have the same alignment by arranging the coefficients. In oil-loss compression, such an alignment causes color data to be quantized twice as large as luminance data, and enables lossless compression on luminance and lossy (high quality) compression on color. These results improve the characteristics of the Human Visual System.

[Other pixel operation]

Printers sometimes contain discontinuous documents, most or all of them. For example, a text image with black and white (with values of only 0 and 255) is common.

In one embodiment, a bar graph of the bandwidth is completed. For example, 0,255 black / white image (K component) is mapped to 0,1 image. Similar shortening can be made for a spot color image. If shortening is used, compression must be lossless compression. However, the implemented lossless compression is substantially improved when the shortening is performed.

Also, instead of using the superimposed wavelet transform represented here, the binary and spot color images are bit-plane based and lossless and can be adjusted by a context model such as JBIG.

In another embodiment, the system may be designed to include a binary model. Figure 35 illustrates one embodiment of a binary context model similar to the JBIG expression context template. 35, shift registers 3501-3503 provide a plurality of bits per JBIG standard. Shift registers 3501 and 3502 receive the second and first upper lines from line buffer 3500. The upper line provides bits corresponding to the North West (NW), North (N), and NE (NE) pixels of the template as shown in Fig. The outputs of shift registers 3501 and 3502 are provided directly to the context model. The output of shift register 3503 provides an optional mux 3504 that can execute the appropriate template of the JBIG standard. The context model 3505 is coupled to a Probability Estimation Machine (PEM) 3506 and eventually to a bit generator (BG) 3507. Context models 3505, PEM 3506, and BG 3507 operate in a well known manner.

The output of the MUX 3504 combined with the outputs of the shift registers 3501 and 3502 and the feedback from the BG form a context bin address that is used to address the context memory. In one embodiment, the context memory 3505 includes 1024 contexts with 6 bits to represent each probability state. This requires 1024 x 6 bits of context memory.

Since BG provides the decode bits from the current line as part of the context address, there is a bit to context delay to the large context including the access time to the context memory.

Figure 36 shows another embodiment of accessing the PEM combined with the same address block 3601 receiving the outputs of the shift registers 3501 and 3502 and the output of the multiplexer 3504 using the decoded bits of the current line. PEM 3506 receives the previous bit and uses it to select the appropriate context from the used pair of contexts. The selected context is updated and the two contexts are written back to memory. The same address block 3601 detects the address already read so that the data is located in the PEM. In addition, the same address block 3801 transmits a signal using data already present in the PEM (updated data) instead of the memory stale information.

In one embodiment, the decoder includes 1024 context beans with 6 bits to represent each probability state. This requires 512 x 12 bits of context memory. The outputs of shift registers 3501 and 3502 together with the output of multiplexer 3504 provide a partial context bean in which the previous bits have not been used. This causes the context memory 3505 to select one of the pair of context beans. More than one bit of the context bean may be excluded from the partial context. Each memory location contains a probability state of 2 &^lt; n ^> (n is the number of bits excluded).

The bit delay to the context decreases. The context memory access occurs before the previous bit is decoded. The processing of the PEM state for a pair of two states begins to run in parallel before the previous bit is decoded and high speed operation is achieved.

[Controlling the encoding ratio]

In addition to the ability to quantize data, a performing rate control in the encoder to determine the quantization requires a measure of the ratio. If the ratio indicates poor compression (ie not the desired level), the quantization increases, and if the ratio indicates too much compression, the quantization decreases. The rate control decision must proceed equally in the encoder and decoder.

One way to ensure that the encoder and decoder make the same decision is to use signaling. The encoder measures the ratio at a set interval and stores the quantization (Q) in memory for use in the next interval. The decoder easily reproduces the quantization from memory for each interval. This will require another memory. For example, an SRAM chip with 256 locations in 2 bits (to represent a change in Q by +2, +1, 0, -1, or to store Q by 1, 2, 3, 4) The quantization (Q) is changed sufficiently for every 16 lines of the image.

There are many options for measuring the ratio. Figure 34 shows a pair of encoder and decoder. As shown in FIG. 34, the pair of encoders / decoders may include a context model (CM), a Probability Estimation Models / Machines (PEM), a BG, a run count reorder unit, A reorder unit and a shifter. This is well known and is disclosed in U.S. Patent Nos. 5,381,145 and 5,583,500, assigned to the assignee of the present invention.

The ratio measurement must be made clear when the decoder is not measuring at the same position. For example, the ratio measurement is supplied to the decoder as part of the compressed code stream.

Another option for ratio management, shown as a small circle (position 2 in FIG. 34), counts the beginning of interleaved words in the encoder. In yet another embodiment, this is performed after the bit generation step (position 4 in Figure 34). Because the encoder and decoder start codewords at the same time, obvious signaling of the ratio is used. The counting is performed by a counting hardware consisting of an adder that determines the average codeword length by summing register and codeword lengths. The hardware to perform the counting and determination of the average number of bits is already well known and is shown in FIG. 34 as block 3401. This block is useful for performing similar measurements at different locations in the system (i. E., Positions 1, 2, 3, 4 in the encoder and decoder).

Another option is to count the size of the codeword ended after BG before the interleaved word reorder unit (position 3 in FIG. 34) or to determine the amount of data actually recorded in the disc (position 1 in FIG. 34).

The ratio measurement can be made clear. The encoder and decoder perform the same ratio determination calculation. For example, the encoder and decoder can accumulate the average size of the codeword each time a new codeword is started. This is indicated by position 4 in Figure 34. (The actual size can not be used because the encoder can not know the size until the end of the codeword.) If the size of the R-code used in the code is R2 (0) When changing through R2 (7), the average codeword size changes from 1 to 4.5 bits. If the probability test is done well, the use of the average becomes very accurate. In other cases, the difference between the minimum and maximum codeword lengths versus the average is not so large, making the test very useful. The average size of Rz (k) is k / 2 + 1 bit.

In most cases, the most important data is well compressed so that quantization (Q = 1) is not necessary. Only pathological images will require quantization (Q> 1). However, the inclusion of quantization characteristics has the advantage that the system is not destroyed by pathological images.

Another advantage of encoder rate control is that encoding of less important data can be stopped when the maximum bandwidth is exceeded. This increases the speed of encoding and reduces the total time to output the data (i. E., The total time taken to print).

It is very important to maintain a track of the quantization effect. For example, the limitation of the largest coefficient in a coefficient group must always be consistent when the quantization changes. In addition, reconstruction of the quantized coefficients (when the bit planes are discarded) needs to take into account the number of discarded bit planes for best results.

[High-speed Parallel Encoding and Context Model]

The entropy coding portion of the present invention consists of two parts. First, a high-speed coding core running in parallel provides probability tests and bit generation. Second, the context model provides the context used for coding.

The number of cores required to achieve the desired speed depends on the application.

Another part of the entropy coding system is the contextual context model of the present invention. There are a myriad of possible exchanges in the execution of the context model. In one embodiment, the present invention provides a context model that has low-cost hardware and provides parallelism to support the use of the high-speed parallel coder of the present invention. An embodiment of the contextual model has been described above.

Although only the context model for the wavelet coefficients is described above, the present invention is not limited to the context model for providing the wavelet coefficients. For example, if the bitplane coding mode is useful for binary or spot pictures, see U.S. Patent Application Serial No. 08/1994, entitled Compression and Decompression with Wavelet Style and Binary Style Including Quantization by Device Dependent Parser, filed May 3, Additional context models such as those disclosed in U.S. Patent Application Serial No. 08 / 643,268, entitled Compression / Decompression Using Reversible Embedded Wavelets, filed May 3, 1996, may be used.

Parallelism

In one embodiment, four fast coding cores are used to encode / decode 8 bits per coefficient, where the range of coefficients is 8-12 bits (13 bits if reversible color space is used). In one embodiment, the core is assigned to each of the four components to facilitate parallelism and data flow. Each coefficient can be used up to 16 cycles for encoding / decoding bits (including preview etc.).

The present invention keeps the core synchronized for each component, even if the core is lost by a successful preview or another core handles the sign bit after the first on-bit. The total time that the context model runs depends on the first on bit of data, especially the effect of the preview and the narrower range.

In the present invention, in performing compression and / or restoration by a system having a buffer, a wavelet transform unit, and a coder, the wavelet transform unit performs wavelet transform on the pixels stored in the buffer, and the coder encodes the transformed pixels, There is an effect that lossless compression can be provided.

The present invention can provide an economical system by implementing a system that can use cheap hard disk technology instead of expensive RAM.

The present invention also has the effect of matching the ratio to the hard disk and matching the hard disk to the bandwidth of the other part implementing the system such as the print engine.

The present invention also has the effect of performing rate matching on RAM using RAM so that compression and restoration time are not much later than RAM speed.

Claims (78)

buffer; A wavelet transform unit having an input connected to a buffer and performing wavelet transform on pixels stored in a buffer and generating a coefficient on an output; a wavelet transform unit connected to the wavelet transform unit and receiving a bit plane of the wavelet transformed pixel of the wavelet transform unit, And a coder for coding the stored bit planes of the wavelet transformed pixels. 2. The apparatus of claim 1, wherein the buffer comprises a band buffer for storing at least one pixel band. The method of claim 1, wherein the coder comprises a context model, a parallel entropy coder encoder, wherein the most important data is not embedded, encoded in counting order without buffering, and the portion of less important data is buffered and embedded Wherein the data is recorded in the memory in an order of importance. 2. The apparatus of claim 1, wherein the encoder comprises a high speed parallel coder. 2. The apparatus of claim 1, wherein the encoder comprises a QM-coder. 2. The apparatus of claim 1, wherein the encoder comprises a finite state machine coder. The apparatus of claim 1, further comprising an encoded data interface. A method of compressing information comprising the steps of: wavelet transforming pixel information received from a buffer, wherein at least one coefficient bit plane represents a reversible wavelet transform pixel; replacing pixels of the buffer with an encoded bit plane; And encoding the bit planes. A restoration apparatus comprising: a band buffer; a plurality of coding units for performing inverse transform operation of coefficients; at least one coding unit for storing pixels output to the output apparatus; And a reconstructor connected to the buffer, wherein the reconstructor restores the compressed data to the transformed coefficients, writes the transformed coefficients to the band buffer, and outputs the transformed coefficients again from the band buffer And performs inverse transformation on the transformed coefficient read back from the band buffer to generate the pixel value, and writes the pixel value to the band buffer. 10. The apparatus of claim 9, wherein the reconstructor reads the compressed data from the storage area. 11. An apparatus according to claim 10, wherein the storage area comprises a hard disk. 10. The apparatus of claim 9, further comprising a print engine coupled to the band buffer. Dividing the coefficients into the most important data and less important data, sending the most important data to the context model and coding them into immediate count orders, storing less important data and a plurality of signal bits in the memory, Coding the most significant data of all coefficients and then coding less important data and embedding by order based in part on a number of signal bits. 14. The method of claim 13, wherein the signal bits comprise a first bit and a second bit. 14. The method of claim 13, wherein the first of the signal bits indicates that the first bit of the less significant data of the coefficient is a head bit or a tail bit and the first bit of the signal bit is the head bit of the less significant data of the coefficient And the second of the signal bits represents a sign bit. 14. The method of claim 13, wherein the signal bits are stored adjacent to less significant data. And a first level conversion unit coupled to receive the even and odd samples to generate a coefficient, the input buffer having an input connected to receive input data, a first and a second output for transmitting even and odd samples, The horizontal low pass coefficient and the vertical high pass coefficient are the outputs of the positive conversion; a first input coupled to receive the ss coefficients generated by the first level conversion unit and a second input receiving the ss coefficients from the high level translation filtering; An order unit having a first input connected to the memory and ordering an ss coefficient for high level filtering, a first filter unit connected to the order unit for applying a plurality of conversion levels, and a filter unit for receiving from the order unit Level conversion of the ss coefficient, and the filter unit performs a high-level translation of the ss coefficients twice It generates an input and two ss coefficient value is applied again to the second input unit of the order-device characterized in that comprising: a. 18. The apparatus of claim 17, wherein the first level translation operates on 2 * 2 blocks of input data. 18. The apparatus of claim 17, wherein the first level translation comprises a second filter unit performing a first level horizontal conversion, the second filter unit having a first output and a second output, A first multiplexer coupled to receive outputs of a first single delay, a second single delay coupled to a second output of the second filter, a double delay coupled to a second output of the second filter, and outputs of a first single delay and a double delay, (MUX), a second MUX coupled to receive the output of the first filter unit and an output of a second single delay, a third filter coupled to receive outputs of the first and second MUX, ≪ / RTI > CLAIMS What is claimed is: 1. An apparatus for compressing an image, the apparatus comprising: a compressor; a motion memory coupled to the compressor; wherein the motion memory is the same size as the image and the compressor uses spatial memory to encode the image using a coefficient greater than a pixel of the image. . ≪ / RTI > CLAIMS What is claimed is: 1. A method of coding information comprising the most important data and less important data, comprising the steps of: coding the most important data; coding the position of the first bit plane of less important data for each coefficient not all configured with zero head bits And coding each bit plane of less significant data that is not all comprised of zero head bits. 22. The method of claim 21, wherein the information comprises wavelet coefficients. 22. The method of claim 21, wherein coding the location of the first less significant bit plane comprises performing a preview of the entire bit plane of less significant data. 22. The method of claim 21, wherein coding the most important data comprises: coding an ss coefficient for each tree; performing a preview on the most important data; for each non-SS coefficient, Coding the head bit or tail bit of the plane, and coding the sign bit if the coefficient is not zero. 25. The method of claim 24, wherein the preview comprises a tree preview, the step of performing a preview comprises coding an ss-coefficient and coding a first zero bit plane with non-zero head bits for the entire tree ≪ / RTI > 25. The method of claim 24, wherein the most important data is processed into one wavelet tree at a time. 22. The method of claim 21, wherein the preview determines a bit plane that includes all zero head bits for all non -ss coefficients of the wavelet tree. 28. The method of claim 27, further comprising identifying a first bit plane to be individually encoded. The method of claim 28, wherein identifying the first bitplane to be individually encoded comprises: using the first bit to indicate that all non-sss coefficients of the second decomposition are zero; ≪ / RTI > wherein all non-sss coefficients are zero. 22. The method of claim 21, wherein coding the most important data comprises: for each tree, coding a ss coefficient; determining a bit plane that is a zero head bit for all non-ss coefficients of each tree; Determining whether the most important data of the entire tree is zero or not; if the most important data of the entire tree is not zero, for all coefficients of the tree, Wherein the current coefficient is the first non-sss coefficient of the tree and begins with a first bit plane holding data, and if the current coefficient is not zero, coding the sign bit. 22. The method of claim 21, wherein coding less important data comprises: for each tree, performing a preview if it is at the start of the preview section, for each coefficient; if the preview is not active, And coding the sign bit if the first on-bit occurs and the preview is not active. CLAIMS What is claimed is: 1. An apparatus for coding information comprising most important data and less important data, comprising: means for coding the most important data; means for coding the position of the first bit plane in less significant data for each coefficient not all configured with zero head bits; Means for coding each bit plane of less significant data not all comprised of zero head bits. 33. The apparatus of claim 32, wherein the information comprises wavelet coefficients. 33. The apparatus of claim 32, wherein the means for coding the position of the first less significant bit plane comprises means for performing a preview of the entire bit plane of less significant data. 32. The apparatus of claim 32, wherein the means for coding the most important data comprises means for coding an ss coefficient for each tree, means for previewing the most important data for each tree, Means for coding a head bit or tail bit for each bit plane having data, means for coding a sign bit if the coefficient is not zero for each non-zero coefficient in each tree. 36. The apparatus of claim 35, wherein the preview comprises a tree preview, the means for performing the preview comprises means for coding the SS-coefficients, and means for coding the first zero bit plane having non-zero head bits for the entire tree And means for determining whether the device is in use. 36. The apparatus of claim 35, wherein the most important data is processed into one wavelet tree at a time. 33. The apparatus of claim 32, wherein the means for performing a preview determines a bit plane comprising all zero head bits for all non-ss coefficients in a wavelet tree. 39. The apparatus of claim 38, further comprising means for identifying a first bit plane to be individually encoded. 40. The apparatus of claim 39, wherein the means for identifying the first bitplane to be individually encoded comprises means for indicating that all non -ss coefficients of the second decomposition are zero using the first bit, And means for indicating that all the non-sss coefficients of the non-sss coefficients are zero. 32. The apparatus of claim 32, wherein the means for coding the most important data comprises means for coding an ss coefficient for each tree, a preview for determining bit planes that are all zero head bits for all non-SS coefficients in each tree Means for determining whether the most important data of the entire tree is zero for each tree, means for determining whether the most significant data of the entire tree is zero or not, Means that the current coefficient is the first non -ss coefficient in the tree and starts with the first bit plane holding the data; if the most significant data of the entire tree is not zero, then if the current coefficient is not zero for all coefficients of the tree, And means for coding the bits. 32. The apparatus of claim 32, wherein the means for coding less important data comprises means for previewing each coefficient of each tree if it is at a start of a preview section, Means for coding a bit or tail bit, means for coding the sign bit of each coefficient for each tree if a first on bit occurs and a preview is not active. A method of m-ary coding information, comprising the steps of: examining a predetermined number of coefficients; entropy coding all head bits, one for each cycle, until all head bits are encoded in a predetermined number of coefficients; ≪ / RTI > coding the sign bit and the tail bit of the coefficients of the first and second coefficients. A pixel data interface for transferring pixel data between the IC chip and the memory, a reversible wavelet transform connected to the pixel data interface for transferring information to and from the memory via the pixel data interface, A context model that provides a context for coding data; and an encoder that encodes coefficients generated by the reversible wavelet transform based on the context provided by the context model. 45. The integrated circuit (IC) of claim 44, further comprising a coefficient data interface coupled to transfer coefficients from the conversion to the memory without coding. 45. The integrated circuit (IC) of claim 44, wherein the coefficient data interface transfers coefficients from the memory to the context model for encoding. The integrated circuit (IC) according to claim 44, further comprising an encoded data interface for providing entropy encoded data to a memory. The integrated circuit (IC) according to claim 47, further comprising a decoder for decoding the encoded data. 47. The integrated circuit (IC) of claim 46, further comprising an encoded data interface that provides entropy encoded data for decoding to a decoder. 45. The integrated circuit (IC) of claim 44, further comprising a reversible color space converter coupled between the pixel data interface and the reversible wavelet transform to perform reversible color space conversion. A decoder for decoding encoded data, the decoder comprising: at least one bit generator coupled to receive encoded data and decoding encoded data based on a probability prediction, the at least one bit generator generating a decoded bit from a current line Coupled to the at least one bit generator and coupled to a probability prediction machine probability prediction machine that provides probability prediction based on the decoded bits from the current line to generate a plurality of contexts based on the partial context addresses, Wherein the context model-probability prediction machine is configured to select among a plurality of contexts based on decoded bits. 52. The apparatus of claim 51, further comprising: an identical address indicator coupled to the probability prediction machine for detecting an already-read address indicating that data is already available in the probability prediction machine; And generating an indication in the probability prediction machine indicating that it is in a probability prediction machine. 52. The decoder of claim 51, further comprising a plurality of shift registers coupled to the context model to provide partial context addresses. 52. The decoder of claim 51, further comprising a line buffer coupled to provide a plurality of said lines. The first bit plane unit, which is connected to receive the less important data and the most important data, determines which bit plane has the data. The first bit plane unit is the first bit plane unit used by the entire coding unit A bit plane representation of the first bit plane having a comparison mechanism, a sign bit, a most significant data, data, connected to receive the less important data and the most important data to generate signal information of less important data A first contextual model coupled to the memory for providing a context of a sign bit, a memory coupled to the most significant data to provide a context of the head bit, Second context model, memory and most important Is connected to the data model context, it characterized in that the configuration including the third context models providing a context for the tail bits. 56. The context model of claim 55, further comprising a separation mechanism for separating input data into more important data and less important data. The context model according to claim 56, wherein the separation mechanism comprises a barrel shifter. The context model according to claim 57, wherein the barrel shifter shifts data based on a quantization level. 55. The method of claim 55, wherein the comparison mechanism determines whether the most significant data is equal to zero, the first comparison unit indicating that tail bits have already been generated, the output of the first comparison unit being a tail on bit, 1, if the most significant data is equal to 1, then the output of the second comparison unit is zero, connected to receive the output and sign bit of the second comparison unit, and the selection input is connected to the first state And outputting a sign if the selected input is in a second state, and a multiplexer for outputting a sign if the selected input is in a second state. 59. The context model of claim 58 wherein the selection input comprises tail-on output of the first comparison unit. The context model of claim 58, wherein at least one of the first and second comparison units comprises a bit comparator. 56. The apparatus of claim 55, wherein the first bitplane unit comprises: an OR gate coupled to receive coefficients and feedback; a register coupled to receive an output of the gate; a coefficient coupled to receive an output of the register; And a priority encoder for recording the first bit plane of the context model. 63. The context model of claim 62, wherein the register comprises a reset input that resets the contents of the register at the start of the coding unit. 62. The context model of claim 62, wherein the reset input also resets the contents of the register at the beginning of each tree. CLAIMS What is claimed is: 1. A method of performing compression comprising: determining an average length of a codeword to identify an encoding rate; and adjusting a compression rate based on a desired amount of compression. 66. The method of claim 65, further comprising the step of increasing the amount of quantization level if the encoding rate indicates that compression is below a first desired level, and decreasing the amount of quantization level if the encoding rate indicates compression is above a second desired level ≪ / RTI > 67. The method of claim 66, wherein the first desired level and the second desired level are not the same. 65. The method of claim 65, wherein determining the average length of the codeword is performed after bit generation. 66. The method of claim 65, further comprising: applying a signal of a new compression rate to the decoder; ≪ / RTI > 70. The method of claim 69, wherein applying the signal is explicit. 70. The method of claim 69, wherein applying the signal is implicit. A context model, a probability prediction machine connected to the context model, a bit generator connected to the probability prediction machine, and an encoder ratio control for controlling the encoding rate by determining an average code word length connected to the output of the bit generator . 72. The apparatus of claim 72, wherein the encoder rate control adjusts the quantization. 73. The apparatus of claim 72, further comprising: a signal block for applying a signal to the decoder for a new quantization level; ≪ / RTI > 73. The apparatus of claim 72, further comprising: a signal block for generating header data for a compressed data stream output of an encoder coupled to the compressed bitstream and for indicating a new quantization level to the decoder; ≪ / RTI > 73. The apparatus of claim 72, wherein the encoder rate control stores an indication of the quantization level required for continued use by the decoder. A method of processing a least significant portion of a data bitplane for a transformed set of coefficients, the method comprising: reading a first portion of data from a memory; And writing to the memory a second amount of data greater than a first amount while reading the first amount of data to compensate for the second amount of data. 79. The method of claim 77, wherein the bits needed to store the least significant chunk coefficient increase as the number of bitplanes decreases.