KR19980082679A - Data verification method of flash memory device - Google Patents

Abstract

The present invention provides a flash memory device including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells in order to provide a data verification method of a flash memory device for reliably verifying data of a flash memory device. Enabling bit lines connected to a plurality of memory cells to be verified among the plurality of memory cells; Enabling a plurality of word lines for controlling the plurality of memory cells to be verified; And comparing the magnitude of the current flowing through the enabled bit line with the magnitude of the reference current.

Description

Data verification method of flash memory device

The present invention relates to a flash memory device, and more particularly, to a verification method for reliably verifying the programmed data after programming each memory cell of the flash memory device.

Conventional flash memory devices typically store data in individual memory cells under program mode and verify data to verify that the stored data has been stored correctly under verify mode. However, in such a scheme, as the memory capacity of the memory device increases, a huge amount of time is required, and parallel programs and parallel verification schemes for simultaneously programming and verifying a plurality of bits have been used.

The conventional parallel program and parallel verify scheme as described above is the first of the plurality of bits, instead of simultaneously verifying the plurality of bits programmed by the program start signal, in order to efficiently perform the program and verify functions. It is characterized by verifying only bits and skipping verification of the remaining bits.

However, as described above, the data verification method of the conventional flash memory device does not verify the data of all the memory cells, so there is a problem that reliable verification cannot be performed.

Accordingly, an object of the present invention is to provide a data verification method of a flash memory device for reliably verifying data of a flash memory device.

1 is a circuit diagram of a portion of a flash memory device that may implement the method of the present invention.

* Explanation of the symbols of the main parts of the drawings

10, 10 'and 10' '. Word lines 12, 12 'and 12' '. Bitline

14, 14 'and 14' '. Memory cells 16. Reference voltage generator

18. Current source 20. Comparator

In order to achieve the above object, the present invention provides a flash memory device including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, wherein the plurality of memory cells are connected to a plurality of memory cells to be verified. Enabling the bitline; Enabling a plurality of word lines for controlling the plurality of memory cells to be verified; And comparing the magnitude of the current flowing through the enabled bit line with the magnitude of the reference current.

Hereinafter, an embodiment of the present invention will be described with reference to FIG. 1.

1 is a circuit diagram of a portion of a flash memory device that may implement the method of the present invention. As shown in FIG. 1, the flash memory device includes a plurality of word lines 10, 10 ′ and 10 ″, a plurality of bit lines 12, 12 ′ and 12 ″, and a plurality of memory cells ( 14, 14 'and 14' '), and reference potential generator 16 and comparator 20.

The specific bit line 12 is enabled in order to verify in parallel the plurality of memory cells 14, 14 'and 14 " in which data is stored by the program operation as described above. Here, in order to verify all the memory cells connected to the enabled bit line 12, each memory cell 14, 14 ′ and 14 ″ connected to the enabled bit line 12 is controlled. A plurality of word lines 10, 10 'and 10 " are each enabled.

As the bit line 12 and word lines 10, 10 ′ and 10 ″ are enabled, currents i ₁ , i ₂ and i _{N in} each of the memory cells 14, 14 ′ and 14 ″ are enabled. Is the sum of the currents, I is the current flowing through the bit line 12, and I is given by the following equation. In other words,

I = i ₁ + i ₂ +... + i _N (N is a natural number)

Comparing the sum (I) of the currents with the magnitude of the predetermined reference current (I _ref ), it is possible to verify whether the data of each of the memory cells 14, 14 'and 14''are correct data.

FIG. 1 illustrates a circuit for converting the sum I of the current into a potential and comparing the reference voltage V _ref by the reference voltage generator 16 with the comparator 20 to verify it.

In addition, if the next bit line 12 'is enabled and the same process is repeated, data of all memory cells can be verified.

According to the present invention, not only the verification operation of the highly integrated flash memory device can be efficiently performed but also the verification operation with high reliability can be performed.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (4)

A flash memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, Enabling bit lines connected to a plurality of memory cells to be verified among the plurality of memory cells; Enabling a plurality of word lines for controlling the plurality of memory cells to be verified; And And comparing a magnitude of a current flowing through the enabled bit line with a magnitude of a reference current. According to claim 1, And converting a current flowing in the enabled bit line into a potential and comparing the current to a reference voltage. A flash memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, Enabling bit lines connected to a plurality of memory cells to be verified among the plurality of memory cells; Enabling a plurality of word lines for controlling the plurality of memory cells to be verified; And And comparing the sum of the magnitudes of the currents flowing in the plurality of memory cells to be verified with the magnitudes of the reference currents. According to claim 3, And converting the sum of the magnitudes of the currents flowing through the plurality of memory cells into a potential and comparing the sum with a reference voltage.