KR19980081671A - Electronic control resistance generation circuit - Google Patents

Abstract

In a circuit that generates an electrical resistance electronically controlled by at least one MOS transistor whose source-drain junction is used to generate an electrical resistance between the first and second terminals, to optimize the linearity of the electrical resistance. Generating a signal for driving the bulk electrode of the associated MOS transistor from a voltage on the terminal of the circuit connected to the source electrode of the associated MOS transistor, the signal depending on the voltage on the terminal and the doping type of the MOS transistor. Bulk signal generating means is provided for generating from an additional superimposed direct current voltage having a polarity to prevent the generation of a diode between the source and the bulk region.

Description

Electronic control resistance generation circuit

The present invention relates to a circuit for producing an electrical resistance electronically controlled by at least one MOS transistor whose source-drain junction is used to produce an electrical resistance generated between the first and second terminals.

In manufacturing a signal processing circuit inside a BICMOS or CMOS IC, problems associated with the manufacture of resistors with sufficient precision arise. Moreover, in such an IC, it is impossible to realize a resistor having a high resistance value at low cost. Conventional circuits for generating resistance by electronic means are known. For this purpose, for example, the source-drain path of the MOS transistor is used. This path is generated electronically between the two terminals of the circuit and forms an electronically controllable resistor. The known circuit has the problem that the resistance produced by the MOS transistor has nonlinearity, that is, the resistance value depends on the voltage applied to the terminals. This is due to the nonlinear drain-source nature of the MOS transistors. Moreover, the above circuit has a problem that, depending on the driving of the source terminal of the MOS transistor, its potential can reach the magnitude of the bulk voltage of the MOS transistor. In this case, a diode is created between the bulk region of the transistor and the source terminal or the drain terminal, which produces a limiting effect, causing distortion of the signal passing through the transistor. Before these effects are activated, the bulk-source / bulk-drain diodes produce nonlinearities that increase with the voltage across the controlled resistor. This effect is known as the backgate effect.

After all, it is an object of the present invention to provide a circuit of the type defined at the outset, which operates at the highest possible linearity and prevents the production of diodes which operate capacitively in the bulk region.

1 is a circuit diagram of a first embodiment according to the present invention using a bipolar PNP transistor to generate a bulk voltage and a PMOS transistor to form an electronically generated resistor;

2 is a circuit diagram of a second embodiment in which a resistor is disposed in series with a source-drain junction of a PMOS transistor;

3 is a circuit diagram of a third embodiment using only MOS transistors.

Explanation of symbols on the main parts of the drawings

1: first PMOS transistor 2: second PMOS transistor

5: first input 6: second input

9 second bulk signal generating means 10 first bulk signal generating means

13,14 current source 21 first NMOS transistor

22: second NMOS transistor 24, 26: resistance

25: third PNP transistor 27: fourth PNP transistor

According to the invention, a signal for driving the bulk electrode of the associated MOS transistor is generated from a voltage on a terminal of a circuit connected to a source electrode of the associated MOS transistor, the signal being dependent on the voltage on the terminal and the doping type of the MOS transistor. The above object is achieved by providing bulk signal generating means for generating from an additional superimposed DC voltage having a polarity so as to prevent the generation of a diode between the source and the bulk region of this MOS transistor.

The MOS transistor used to generate the electronically controlled resistor in the present invention has a source and drain electrode of the first doping type. A gate electrode that makes the transistor controllable extends between the source and drain electrodes. The transistor is formed inside a so-called bulk region having a second doping type as a whole. In operation, this type of transistor has the problem that the source potential must always be less than the potential in the bulk region. However, if both regions have similar potentials, a diode is formed between the source electrode and the bulk region, which imparts capacitive and dc loads to the signal applied to the gate electrode of the transistor, resulting in a signal Distorted or change

In order to eliminate this undesirable effect and to ensure that the transistor always operates in the region with the most linearity of its drain-source characteristic, according to the invention, the transistor does not produce such a conductive diode while Means are provided to generate the bulk signal so that it operates in the region as linear as possible. This is achieved by causing the bulk signal generating means to generate this signal in such a way that the bulk signal includes an overlap of an additional direct current voltage with the voltage on the terminal of the circuit connected to the source electrode of the MOS transistor. Thus, in addition, the direct current voltage is superimposed on the external signal voltage applied to the source electrode of the transistor. The superimposed signals are applied to the bulk electrodes of the MOS transistors as bulk signals. Accordingly, the potential of the bulk electrode, and consequently the potential of the bulk region of the transistor, is always higher than the potential of the source region of the transistor. This also eliminates the influence of the capacitor layer of the diode on the bulk.

As a result, the circuit forms an electronically generated resistor whose resistance value is adjustable by selection of the gate voltage of the transistor and whose resistance value is large linearity and does not exhibit undesirable capacitive effects.

According to the embodiment of the present invention as set forth in claim 2, even in the case of asymmetrical driving to two terminals, the circuit has the above advantages without any limitation.

According to claim 3, Preferably, the means for generating the bulk signal or bulk signals comprises a transistor suitable for superimposing a direct current voltage on the bulk signal of a MOS transistor, whereby the direct current voltage is compared with the source signal when compared with the source signal. Can be produced relatively simply by means of a diode junction.

For example, in the embodiment described in claim 4, the base-emitter potential difference of the bipolar PNP transistor is d.c. Used to further overlap the potential, the potential for generating the bulk signal is connected to the source region of the MOS transistor.

In the embodiment described in claim 5, the above configuration is achieved in a similar manner for a bipolar NPN transistor.

Embodiments as claimed in claims 6 and 7 use PMOS and NMOS transistors as means for generating bulk signals. In these transistors, gate-source junction is used to generate the potential difference. The requirement for using such a MOS transistor is that the bulk electrode must be available externally.

The embodiment described in claim 8 has the advantage that the linearity can be further improved. The resistor provided therein has a relatively small resistance value. However, they cause the resistance value generated by the transistor to be larger. These resistors with relatively small resistance values can be integrated in a relatively simple manner inside the integrated circuit.

Hereinafter, three embodiments according to the present invention will be described in detail with reference to the drawings.

The circuit constituting the first embodiment shown in FIG. 1 uses the first PMOS transistor 1 and the second PMOS transistor 2 to generate a resistance. The source-drain junctions of these two PMOS transistors 1 and 2 are arranged in parallel.

The first PMOS transistor 1 has a source electrode 4 connected to the second terminal 6 of the circuit. This first PMOS transistor also has a drain electrode 3 connected to the first terminal 5 of the circuit.

The second PMOS transistor 2 also includes a source electrode 8 connected to the first input 5 of the circuit and a drain electrode 7 connected to the second terminal 6.

The circuit shown in FIG. 1 further comprises means 10 for generating a bulk signal for the first PMOS transistor 1 and second means 2 for generating a bulk signal for the second PMOS transistor 2. Equipped. In the present embodiment, the means 9 and 10 comprise bipolar PNP transistors.

In the first means 10 for generating a bulk signal for the first PMOS transistor 1, the collector is connected to a reference potential and the base electrode is the second terminal 6 of the circuit and the source electrode 4 of the first PMOS transistor. A PNP transistor connected to is provided. In the means 10, the emitter of the PNP transistor is connected to the bulk electrode 11 of the first PMOS transistor. Moreover, it is connected to the power source potential Vd via the current source 13.

The second means 9 for generating a bulk signal for the second PMOS transistor 2 is likewise referred to the reference potential, the first input 5, the bulk electrode 12 of the second PMOS transistor 2 and the current source ( A PNP transistor connected to a power supply potential via 14).

In the means 9 and 10, the PNP transistor is such that the bulk voltage applied to the bulk electrodes 11 and 12 of the transistors 1 and 2 is equal to the potential difference higher than the voltage applied to its source electrode, respectively. The voltage across the base-emitter junction is used. The voltage on the second terminal of the circuit is applied, for example, to the source electrode 4 of the first PMOS transistor 1. Moreover, this voltage, increased by the potential difference across the base-emitter junction of the PNP transistor provided inside the second means, is applied to the bulk electrode 11 of the same PMOS transistor 1. Accordingly, the bulk electrode 11 of the first transistor 1 is identical to its source electrode but is adapted to receive a signal increased by the potential difference across the base-emitter diode junction of the PNP transistor inside the means 10. This potential difference is approximately 0.7V. Thus, if any signal change occurs at terminal 6, such a potential difference is obtained between the source and bulk terminal of transistor 1, and a capacitance diode is formed between the source electrode and the bulk region.

This fact applies likewise to the bulk signal generated by the second PMOS transistor 2 and the second means 9.

In addition, the circuit shown in FIG. 1 includes two NMOS transistors 21 and 22 having a source electrode connected to a reference potential and a gate electrode connected to a control potential Vcontrol. The first transistor 21 has its drain electrode connected to the gate electrode 23 of the first PMOS transistor 1, and is connected to the emitter of the third PNP transistor 25 via a resistor 24. The third PNP transistor 25 has its base electrode connected to the first input 5 of the circuit and its collector connected to the power supply potential Vd. Similarly, a fourth drain electrode of the second NMOS transistor 22 is connected to the gate electrode of the second PMOS transistor 2 and disposed similarly to the third bipolar PNP transistor 25 via a resistor 26. It is connected to a bipolar transistor 27, which is connected to the source electrode 4 of the first PMOS transistor 1. That is, the drain electrode of the second NMOS transistor 22 is connected to the gate electrode 28 of the second PMOS transistor 2.

Since the control potential Vcontrol can be used to control the potentials on the gate electrodes 23 and 28 of the PMOS transistors 1 and 2, the resistances of the source-drain junctions of the two transistors 1 and 2 can be controlled. . In this way it is possible to adjust the electronically controllable resistance of the circuit between the terminals 5, 6 of this circuit.

Alternatively, an NMOS transistor may be used instead of the PMOS transistors 1 and 2 described above. Similarly, NPN transistors may be used in the means 9 and 10 instead of the PNP transistors.

2 shows a second embodiment of the present invention. In the circuit shown in FIG. 2, a resistor 31 is disposed between the source electrode 4 of the first transistor 1 and the second terminal 6 of the circuit, and the source electrode of the second PMOS transistor 2 ( Same as that shown in FIG. 1 except that a second resistor 32 is disposed between 8) and the first terminal 5 of the circuit.

In this embodiment, resistors 31 or 32 are arranged in series with the source-drain junctions of the two PMOS transistors 1 and 2, respectively.

The resistance value of the resistors 31 and 32 is selected smaller than the resistance obtained between the terminals 5 and 6. Thus, on the one hand, the resistors 31 and 32 can be integrated relatively easily on the substrate of the integrated circuit. On the other hand, the resistance value generated by the source-drain junction of the two PMOS transistors 1 and 2 should be small. In this way, the linearity of the circuit can be further improved.

The third embodiment according to the present invention shown in FIG. 3 comprises first and second means 42 for generating bulk signals using PMOS transistors instead of the bipolar PNP transistors of the embodiments shown in FIGS. 1 and 2. Means 41 are provided. Furthermore, the third and fourth bipolar PNP transistors 25 and 27 in the two embodiments shown in FIGS. 1 and 2 have been replaced with NMOS transistors 43 and 44. Accordingly, the circuit shown in FIG. 3 can be manufactured only by the MOS process, but it is required that the bulk electrodes of the transistors 41 to 44 be externally accessible.

In the PMOS transistor of the first means 42, its drain electrode is connected to the reference potential and the gate electrode is connected to the second input 6 of the circuit and the source electrode 4 of the first PMOS transistor. The source and drain electrodes of the PMOS transistor in the first means 42 are both connected to the bulk electrode of the first PMOS transistor 1, and are connected to the power source potential Vd via the current source 13. Thus, the bulk signal is always equal to the potential difference across the gate-source junction of the PMOS transistor that is higher than the input signal applied to the second input 6 of the circuit. In this way, the same advantages as in the circuit in FIG. 1 are obtained.

Similarly, the PMOS transistor of the second means 41 has a reference potential, the first terminal 5 of the circuit, the source electrode 8 of the second PMOS transistor 2 and the second bulk of the second PMOS transistor 2. Not only the electrode 12 but also a power supply potential is connected.

In order to operate without the bipolar transistor in the circuit shown in Fig. 3, transistors 25 and 27 in the circuit shown in Figs. 1 and 2 were replaced with MOS transistors, that is, MOS transistors 43 and 44.

The bulk and source electrodes of the NMOS transistors 43 and 44 are connected to the drain electrodes of the transistors 21 and 22, respectively, and the drain electrodes of the transistors 43 and 44 are connected to a reference potential. The gate electrode of the transistor 43 is connected to the first input 5 of the circuit and the gate electrode of the transistor 44 is connected to the second input 6 of the circuit. In this embodiment, transistors 43 and 44, together with transistors 21 and 22, serve to set the gate potential of PMOS transistors 1 and 2, as a result of which the circuits between the terminals 5 and 6 of this circuit are located. It serves to set the electrical resistance.

As described in detail above, according to the present invention, by controlling the potential on the gate electrode of the PMOS transistor using a control potential, while maintaining high linearity and preventing generation of a diode that operates capacitively in the bulk region, An electronically controllable electrical resistance generating circuit capable of controlling the resistance of the source-drain junction of the two transistors can be provided.

Claims (8)

A circuit for generating an electrical resistance electronically controlled by at least one MOS transistor whose source-drain junction is used to generate an electrical resistance generated between the first and second terminals, wherein: A signal for driving the bulk electrode of the associated MOS transistor is generated from a voltage on a terminal of a circuit connected to a source electrode of the associated MOS transistor, the signal being dependent on the voltage on the terminal and the doping type of the MOS transistor. And a bulk signal generating means is provided for generating from an additional superimposed direct current voltage having a polarity to prevent generation of a diode between the source and the bulk region. The method of claim 1, First means for generating a bulk signal from a voltage on a first terminal having the controlled resistance for a MOS transistor connected to the first means, the source-drain junction of which is arranged in parallel produces an electrically controllable resistance, The MOS transistor connected to the second means is provided with a bulk signal generating means consisting of second means for generating a bulk signal from a voltage on a second terminal having the controlled resistance, and two MOS transistors respectively connected to each other. Resistance generation circuit. The method of claim 1, And the means for generating the bulk signal or the plurality of bulk signals comprises a plurality of transistors. The method of claim 1, The bulk signal generating means has a source-connected source for generating a current source and a resistor connected at its base to one of the terminals of the circuit, at its collector at a reference potential, and connected at a positive power supply potential. And a bipolar PNP transistor whose emitter is connected to a bulk electrode of a PMOS transistor in which a drain junction is used. The method of claim 1, The bulk signal generating means has a source-connected source for generating a current source and a resistor connected at its base to one of the terminals of the circuit, at its collector at a positive power supply potential, and at a reference potential. And a bipolar NPN transistor whose emitter is connected to a bulk electrode of a PMOS transistor in which a drain junction is used. The method of claim 1, The bulk signal generating means has a current source connected to one of the terminals of the circuit, a gate electrode thereof connected to a reference potential thereof, a drain electrode thereof connected thereto, and a resistor to generate a current source and a resistance connected to a positive power source potential. And a PMOS transistor having a source electrode and a bulk electrode connected to a bulk electrode of a PMOS transistor in which a source-drain junction is used. The method of claim 1, The bulk signal generating means is configured to generate a current source and a resistor connected at one of the terminals of the circuit, its gate electrode is connected, its drain electrode is connected at a positive power supply potential, and is connected at a reference potential. A resistance generating circuit comprising: an NMOS transistor connected to a bulk electrode thereof and a bulk electrode thereof in a bulk electrode of an NMOS transistor in which a source-drain junction is used. The method of claim 1, And a resistor is arranged in series in each of a plurality of MOS transistors whose source-drain junction is used to create a resistor.