KR19980079130A - Pad Control Circuit and Method - Google Patents

Abstract

A semiconductor device including a plurality of circuits requiring a test, comprising: a common pad, a plurality of switching means, and a pad control circuit, the pad capable of testing a plurality of circuits with a common pad A control circuit is disclosed. Each of the plurality of switching means is connected between a corresponding one of the plurality of circuits and one common pad, and is enabled by a corresponding control signal among the plurality of control circuits output from the pad control circuit, thereby Select the circuit and connect it to one common pad. The pad control circuit is enabled by an enable signal according to a user's request to generate control signals corresponding to the plurality of switching means, respectively, and maintains the state of the generated control signals until it is enabled again. According to the present invention, by controlling the electrical connection of a plurality of circuits to one common pad, the operation of a plurality of circuits inside the chip using one common pad even if the area of the pad decreases as the chip density increases. Has the effect of testing.

Description

Pad control circuit and method

The present invention relates to a pad control circuit and method, and more particularly to a pad control circuit and method that can test a plurality of circuits in need of testing using one common pad.

As semiconductor process technology develops and chip density increases, efforts are being made to reduce the chip size and reduce costs by producing as many chips as possible on one wafer.

However, the development of a package is not being made at the pace of development of process technology and chip density. Therefore, when assembling a package from a wafer, a pad size connecting the wafer and the lead frame by a wire bonder is used as it is.

In semiconductor memory devices, in particular DRAM or synchronous DRAM, there are direct current voltage generators generated within the chip. DC voltage generators include internal voltage converters, reference voltage generators, memory array reference voltage generators, boosted power generators (VPP generators), and pre-charge voltage generators (VBL generators). , A cell charge compensation voltage generator (VP generator), and a back bias voltage generator (Back Bias Voltage Generator). As the DC voltage generators process, the levels of the DC voltages generated in the DC voltage generators are changed by changing the threshold voltage, the saturation drain current, and the like of the devices. These changes in the levels of DC voltages change the margins of the circuits operating inside the chip and, in the case of fatal, cause no operation of the circuits at all. In order to prevent this phenomenon, in a DRAM or a synchronous DRAM, a pad is provided for each DC voltage generator, and each pad is probed at the wafer level test. Therefore, the process is performed while detecting the levels of the DC voltages generated from the DC voltage generators, checking the changed levels, and correcting them through an appropriate method.

Figure 1 shows the conventional pad control circuit mentioned above.

Referring to FIG. 1, a conventional pad control circuit includes DC voltage generators 102 to 110 and pads 112 to 120.

The DC voltage generators 102 to 110 are connected to corresponding pads among the pads 112 to 120, respectively. Therefore, the tests on the DC voltage generators 102 to 110 are performed through corresponding pads, respectively.

However, as mentioned above, in the current situation of trying to reduce the chip size and reduce the cost by producing as many chips as possible on one wafer, the area of pads for monitoring the DC voltage generators is no longer provided. This led to a situation in which no more space was available for the pads. Therefore, it is not possible to monitor the change of DC voltage level according to the process change, fail analysis of the chip internal circuits, and fail to respond quickly to the process change, which is disadvantageous in terms of mass production.

Accordingly, an object of the present invention is to test a plurality of circuits using one common pad in order to meet the current situation in which the space for the pads to enter as the chip density increases with the development of process technology. The present invention provides a pad control circuit.

Another object of the present invention is to be able to test a plurality of circuits using one common pad, in order to meet the current situation in which the space for the pad is reduced as the chip density increases with the development of process technology. It is to provide a pad control method.

1 is a block diagram of a conventional pad control circuit.

2 is a block diagram of a pad control circuit according to the first embodiment of the present invention.

3 is a block diagram of a circuit according to an exemplary embodiment of the pad control signal generator of FIG. 2.

FIG. 4 is a circuit diagram of a circuit according to a specific embodiment of the test mode control signal generator in FIG. 3.

FIG. 5 is a circuit diagram of a circuit according to a specific embodiment of the register circuit in FIG. 3.

FIG. 6 is a circuit diagram of a circuit according to a specific embodiment of the control signal generator in FIG. 3.

7 is a block diagram of a pad control circuit according to a second embodiment of the present invention.

FIG. 8 is a block diagram of an embodiment of a mode register setting circuit in FIG. 7.

9 is a circuit diagram of a circuit according to an embodiment of a mode register in FIG. 8.

FIG. 10 is a circuit diagram of a circuit according to an embodiment of a burst length mode signal generator in FIG. 8.

11 is a flowchart illustrating a pad control method according to a third embodiment of the present invention.

12 is a flowchart illustrating a pad control method according to a fourth embodiment of the present invention.

* Detailed description of the main symbols in the drawing

CL1, CL2, CL3: CAS latency mode signals, PVCCH: power voltage clock signal,

RAi: low address, MDSTi: mode register data signal,

PWCBR: Mode register enable signal, CT: CAS type mode signal,

BL1, BL2, BL4, BL8, BLFULL: Burst length mode signals.

In order to achieve the above object, the pad control circuit according to the present invention is a semiconductor device having a plurality of circuits requiring a test, the pad control circuit comprising one common pad, a plurality of switching means, and a pad control circuit. It is done.

Each of the plurality of switching means is connected between a corresponding one of the plurality of circuits and one common pad and is enabled by a corresponding control signal, thereby connecting the corresponding circuit to one common pad.

The pad control circuit is enabled in the test mode to generate control signals respectively corresponding to the plurality of switching means.

The pad control circuit is enabled in the test mode and has a register circuit for storing data input from the plurality of pins and a control signal generator for generating control signals for controlling the plurality of switching means in accordance with the data stored in the register. do.

The pad control method according to the present invention for achieving the above another object is characterized in that it comprises a test mode setting step, a control signal generation step, a circuit selection step to test, an electrical connection step, a test step, and other test whether to determine whether or not do.

The test mode setting step sets a test mode for circuits requiring a test.

The control signal generation step generates control signals for controlling the connection state between the circuits requiring the test and the common pad after the test mode setting step.

The circuit selection step to test selects one of the circuits to be tested according to the control signals generated from the control signal generation step.

The electrical connection step electrically connects between the circuit selected in the circuit selection step to be tested and the common pad.

The test step tests the operation of the selected circuit through a common pad.

The other test determining step determines whether to continue the test for the other circuits requiring the test after the test step, and in the case of the continuous test, to perform the above series of steps from the control signal generation step.

Next, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a pad control circuit according to the first embodiment of the present invention.

Referring to FIG. 2, the pad control circuit according to the first embodiment of the present invention includes a plurality of circuits 202, 204, 210, a plurality of switching means 212, 214, 220, a pad control circuit 230, and one requiring a test. The common pad 240 is provided.

The plurality of circuits 202, 204, and 210 are circuits that need to be tested and include DC voltage generator circuits existing inside the chip.

The pad control circuit 230 generates control signals for controlling the plurality of switching means 212, 214, and 220. The control signals generated here enable the plurality of switching means 212, 214, 220 only one at a time.

The plurality of switching means 212, 214, 220 are respectively connected between a corresponding circuit among the plurality of circuits 202, 204, 210 and one common pad, and a corresponding control signal among control signals generated from the pad control circuit 230. Controlled by the control circuitry to select a corresponding circuit from among the plurality of circuits 202, 204, and 210 to form an electrical connection between the corresponding circuit and one common pad.

One common pad 240 is for probing signals for testing a circuit that is electrically connected among the plurality of circuits 202, 204, and 210 through the plurality of switching means 212, 214, and 220.

3 is a block diagram of a circuit according to a specific embodiment of the pad control circuit 230 in FIG. 2.

Referring to FIG. 3, a circuit according to a specific embodiment of the pad control circuit 230 includes a test mode control signal generator 248, a register circuit 250, and a control signal generator 260.

The test mode control signal generator 248 generates an enable signal PA that controls the register circuit 250.

The register circuit 250 is enabled by the enable signal PA, inputs and stores a raw address RA, and outputs it as output data MRA.

The control signal generator 260 inputs and decodes the data MRAi output from the register circuit 250 and outputs the decoded data as control signals PTSi. Here, the control signal generator 260 inputs and decodes the data MRAi (i = 0-2) output from the register circuit 250 and outputs the decoded data as the control signals PTSi (i = 0-7).

In FIG. 3, in particular, the operation of the chip circuit is determined by the low address strobe signal RASB, the column address strobe signal CASB, the write enable signal WEB, and the chip select signal CEB. In a semiconductor memory device to be fabricated, it is a circuit diagram of a circuit according to a specific embodiment of the test mode control signal generator 248.

A circuit according to a specific embodiment of the test mode control signal generator 248 is comprised of NAND gates 244, 242, 246 and inverters 241, 243, 245.

The NAND gate 244 has a low address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, and a chip select signal CEB all at low level ('L'). Outputs a signal that is high ('H').

The inverter 241 inputs a raw address RA7 and inverts it and outputs it.

The NAND gate 242 is at a high ('H') level only when the levels of the low address (RA7) and low address (RA8) are high ('H') and low ('L'), respectively, among the low addresses Rai. Outputs a signal.

The inverter 245 and the inverter 243 input the outputs of the NAND gate 244 and the NAND gate 242, respectively, and invert them and output them.

The NAND gate 246 outputs a signal that becomes a high ('H') level as an enable signal PA only when the signals output from the inverter 245 and the inverter 243 are both low ('L') levels. do.

The test mode control signal generator 248 has a low address strobe signal (RASB), a column address strobe signal (CASB), a write enable signal (WEB), and a chip select signal (CEB) all low ('L'). Level and the enable signal PA which becomes a high ('H') level only when the levels of the low address (RA7) and low address (RA8) are high ('H') and low ('L'), respectively. Output

In addition, various specific embodiments of the test mode control signal generator 248 may be possible within a range that does not interfere with normal chip circuit operation.

FIG. 5 illustrates a circuit diagram of a circuit in accordance with a specific embodiment of the register circuit 250 in FIG. 3.

Referring to FIG. 5, a circuit according to a specific embodiment of the register circuit 250 may include an inverter 262, a transfer gate 264, a latch unit 266, a precharge unit 268, and a driver 270. Equipped.

The inverter 262 inputs and outputs the raw address RAi output from the raw address buffer circuit (not shown).

The transmission gate 264 receives and transmits a signal output from the inverter 262 under the control of the enable signal PA. That is, when the enable signal PA is high (H), the transmission gate 264 inputs and transmits a signal output from the inverter 262.

The precharge unit 268 precharges the signal input to the latch unit 266 by the input signal PVCCH to a low level 'L'. Here, the input signal PVCCH is a signal that is switched from the low ('L') level to the high ('H') level when the register circuit 250 is enabled by the enable signal PA.

The latch unit 266 latches and stores a signal transmitted from the transmission gate 264.

The driver 270 drives a signal latched and stored in the latch unit 266 and outputs the output data MRAi of the register circuit 250.

6 is a circuit diagram of a circuit according to a specific embodiment of the control signal generator 260 in FIG. 3.

Referring to FIG. 6, a circuit according to a specific embodiment of the control signal generator 260 includes inverters 271 to 281, and NAND gates 282 to 289.

The inverter 271 inputs the output data MRA2 and inverts it and outputs it.

The inverter 272 inputs the output data MRA1 and inverts it and outputs it.

The inverter 273 inputs the output data MRA0 and inverts the output data MRA0 to output the same.

The NAND gate 282 outputs a signal that becomes a high ('H') level only when the output data MRA2, MRA1, and MRA0 are all low ('L') levels.

The NAND gate 283 outputs a signal that becomes a high ('H') level only when the output data MRA2 and MRA1 and the signal output from the inverter 271 are both low ('L') levels.

The NAND gate 284 outputs a signal that becomes a high ('H') level only when the output data MRA2 and MRA0 and the signal output from the inverter 272 are both low ('L') levels.

The NAND gate 285 outputs a signal that becomes a high ('H') level only when the output data MRA2 and the signals output from the inverters 271 and 272 are both low ('L') levels.

The NAND gate 286 outputs a signal that becomes a high ('H') level only when the output data MRA1 and MRA0 and the signal output from the inverter 273 are both low ('L') levels.

The NAND gate 287 outputs a signal that becomes a high ('H') level only when the output data MRA1 and the signals output from the inverters 271 and 273 are both low ('L') levels.

The NAND gate 288 outputs a signal that becomes a high ('H') level only when the output data MRA0 and the signals output from the inverters 272 and 273 are both low ('L') levels.

The NAND gate 289 outputs a signal that becomes a high ('H') level only when the signals output from the inverters 271, 272, and 273 are all low ('L') levels.

The inverter 274 inputs a signal output from the NAND gate 282, inverts it, and outputs the signal as the control signal PTS0.

The inverter 275 receives a signal output from the NAND gate 283, inverts it, and outputs the signal as the control signal PTS1.

The inverter 276 inputs a signal output from the NAND gate 284, inverts it, and outputs the signal as the control signal PTS2.

The inverter 277 receives a signal output from the NAND gate 285, inverts it, and outputs the signal as the control signal PTS3.

The inverter 278 receives a signal output from the NAND gate 286, inverts it, and outputs the signal as the control signal PTS4.

The inverter 279 receives a signal output from the NAND gate 287, inverts it, and outputs the signal as the control signal PTS5.

The inverter 280 receives a signal output from the NAND gate 288, inverts the signal, and outputs the signal as the control signal PTS6.

The inverter 281 receives a signal output from the NAND gate 289, inverts it, and outputs the signal as the control signal PTS7.

The following table is a truth table for burst length mode signals output according to a combination of data MRA0, MRA1, and MRA2 input in the circuit of FIG.

TABLE 1

MRA2 MRA1 MRA0 PTS0 PTS1 PTS2 PTS3 PTS4 PTS5 PTS6 PTS7 0 0 0 1 0 0 0 0 0 0 0 0 0 One 0 1 0 0 0 0 0 0 0 One 0 0 0 1 0 0 0 0 0 0 One One 0 0 0 1 0 0 0 0 One 0 0 0 0 0 0 1 0 0 0 One 0 One 0 0 0 0 0 1 0 0 One One 0 0 0 0 0 0 0 1 0 One One One 0 0 0 0 0 0 0 1

In this way, the pad control circuit 230 is provided, and the plurality of switching means 212, 214, 220 are generated by the plurality of control signals PTSi by generating the plurality of control signals PTSi from the pad control circuit 230. ) Can be selectively enabled one by one to control the electrical connection of one common pad 240 and a plurality of circuits 202, 204, and 210 that require testing, thereby providing a plurality of circuits with one common pad 240. Tests on (202, 204, 210) are possible. Accordingly, the problem of reducing the area where the pad may exist as the chip density increases may be solved. In addition, the control signals PTSi generated from the pad control circuit 230 may maintain their states until the pad control circuit 230 is enabled again by the enable signal PA. Therefore, when testing circuits that require testing, in particular DC voltage generator circuits, the DC voltage levels of the DC voltage generator circuits as well as the operation of the circuit itself are forced through the common pads and thus within the chip circuit. The effects on the circuits can be tested simultaneously.

7 is a block diagram of a pad control circuit according to a second embodiment of the present invention.

Referring to FIG. 7, the pad control circuit according to the second embodiment of the present invention includes DC voltage generator circuits 302, 304, 306, 308, 310, switching means 312, 314, 316, 318, 320, a mode register set circuit 330, and one. The common pad 340 is provided.

The DC voltage generator circuit 302 is an internal voltage converter that converts a voltage from an external power source to suit the internal voltages of internal circuit elements.

The DC voltage generator circuit 304 is a reference voltage generator for generating the reference voltage necessary to control the input level.

The DC voltage generator circuit 306 is a bit line precharge voltage generator (VBL Generator) that generates the bit line precharge voltage required to precharge the bit line during the precharge period.

The DC voltage generator 308 is a cell potential control voltage generator (VP generator) for generating a voltage for compensating the potential of the memory cell in order to define the memory cell charge amount.

The DC voltage generator circuit 310 is a memory cell array control voltage generator (Array Reference Voltage Generator) for generating a memory cell array control voltage required to control the level of the breakdown voltage of the elements constituting the memory cell array.

The switching means 312 is connected between the DC voltage generating circuit 302 and one common pad 340, and is controlled by the control signal BL1 generated from the mode register setting circuit 330, so that the control signal ( Only when BL1 is at a high ('H') level, the DC voltage generator circuit 302 and one common pad 340 are electrically connected.

The switching means 314 is connected between the DC voltage generator circuit 304 and one common pad 340, and is controlled by the control signal BL2 generated from the mode register setting circuit 330, so that the control signal ( Only when BL2 is at the high ('H') level, the DC voltage generator circuit 304 and one common pad 340 are electrically connected.

The switching means 316 is connected between the DC voltage generating circuit 306 and one common pad 340, and is controlled by the control signal BL4 generated from the mode register setting circuit 330, so that the control signal ( Only when BL4 is at the high ('H') level, the DC voltage generator circuit 306 and one common pad 340 are electrically connected.

The switching means 318 is connected between the DC voltage generating circuit 308 and one common pad 340, and is controlled by the control signal BL8 generated from the mode register setting circuit 330, so that the control signal ( Only when BL8 is at the high ('H') level, the DC voltage generator circuit 308 and one common pad 340 are electrically connected.

The switching means 320 is connected between the DC voltage generating circuit 310 and one common pad 340, and is controlled by the control signal BLFULL generated from the mode register setting circuit 330, thereby controlling the control signal ( Only when BLFULL) is at a high ('H') level, the DC voltage generator circuit 310 and one common pad 340 are electrically connected.

In the synchronous semiconductor memory device, the mode register setting circuit 330 is configured by a low address strobe signal RASB, a column address strobe signal CASB, a chip select signal CSB, and a write enable signal WEB. It is a circuit for controlling the CAS latency, burst type, burst length, and the like. The mode register setting circuit 330 is enabled by the low address strobe signal RASB, the column address strobe signal CASB, the chip select signal CSB, and the write enable signal WEB, and is input to the address. Determine the CAS latency, burst type, burst length, and the like according to the combination of C, and accordingly the CAS latency mode signals CL1 CL2, CL3, burst type mode signals (not shown), and burst length mode signals. (BL1, BL2, BL34, BL8, BLFULL) is generated. Here, the states of the CAS latency mode signals CL1 CL2 and CL3, the burst type mode signals (not shown), and the burst length mode signals BL1, BL2, BL34, BL8, and BLFULL may be set in the mode register setting circuit ( 330 is multiple enabled and does not change until the mode is set. That is, when the mode register setting circuit 330 is enabled, the CAS latency and burst length are determined according to the combination of the input addresses, and accordingly, one of the CAS latency mode signals CL1 CL2 and CL3 is enabled and bursted. One of the length mode signals BL1, BL2, BL34, BL8, BLFULL is enabled, and their state does not change until the mode register setting circuit 330 is enabled again to set the mode. Therefore, using the burst length mode signals BL1, BL2, BL34, BL8, BLFULL as control signals for controlling the switching means 312, 314, 316, 318, and 320, the DC voltage is generated through the operation of enabling the mode register setting circuit 330. The circuits 302, 304, 306, 308, 310 may individually make electrical connections with one common pad 340. Therefore, a test of a plurality of circuits is possible using one common pad.

FIG. 8 is a detailed block diagram of an embodiment of the mode register setting circuit 330 in FIG. 7.

Referring to FIG. 8, one embodiment of the mode register setting circuit 330 includes a mode register 410, a burst length mode signal generator 420, and a CAS latency mode signal generator 430.

The mode register 410 is enabled by the control of the control signal PWCBR, and inputs and stores the raw address RAi output from the raw address buffer circuit (not shown), and stores it in the mode register 410. The data are output as the data MDSTi (i = 0 to 6). The control signal PWCBR is the low address strobe signal RASB, the column address strobe signal CASB, the chip select signal CSB, and the write enable signal WEB all low ('L'). Only active signal.

The burst length mode signal generator 420 inputs the data MDST0, MDST1, and MDST2 output from the mode register 410, and sets the mode for the burst length according to the combination, so that only the corresponding burst length mode signal is generated. It outputs the activated burst length mode signals BLi, i = 1, 2, 4, 8, FULL.

The CAS latency mode signal generator 430 inputs the data MDST3 output from the mode register 410, sets a mode for the CAS type according to the combination, and generates a corresponding CAS type mode signal CT. Output

The CAS latency mode signal generator 440 inputs the data MDST4, MDST5, and MDST6 output from the mode register 410, and sets the mode for CAS latency according to the combination, so that only the corresponding CAS latency mode signal is generated. It outputs the activated burst length mode signals CLi, i = 1, 2, 3.

FIG. 9 is a circuit diagram of a circuit according to an embodiment of the mode register 410 in FIG. 8.

9, a circuit according to an embodiment of the mode register 410 includes an inverter 502, a transfer gate 504, a latch unit 506, a precharge unit 508, and a driver 510. do.

The inverter 502 inputs and outputs the raw address RAi output from the raw address buffer circuit (not shown).

The transmission gate 504 inputs and transmits a signal output from the inverter 502 under the control of the control signal PWMBR. That is, when the control signal PWCBR is high (H), the transmission gate 504 inputs and transmits a signal output from the inverter 502. The control signal PWCBR is the low address strobe signal RASB, the column address strobe signal CASB, the chip select signal CSB, and the write enable signal WEB all low ('L'). It is a signal that is only active high ('H').

The precharge unit 508 precharges a signal input to the latch unit 506 by the input signal PVCCH to a low ('L') level in advance. Here, the input signal PVCCH is a signal that is switched from the low ('L') level to the high ('H') level when the mode register 410 is enabled by the control signal PWMBR.

The latch unit 506 latches and stores a signal transmitted from the transmission gate 504.

The driver 510 drives a signal latched and stored in the latch unit 506 and outputs the output data MDSTi of the mode register 410.

FIG. 10 is a circuit diagram of a circuit according to an embodiment of the burst length mode signal generator 420 in FIG. 8.

Referring to FIG. 10, a circuit in accordance with one embodiment of a burst length mode signal generator 420 includes inverters 602 through 616 and NAND gates 622 through 630.

The inverter 602 inputs and outputs the output data MDST2.

The inverter 604 inputs and outputs the output data MDST1.

The inverter 606 inputs the output data MDST0 and inverts it to output the output data MDST0.

The NAND gate 622 outputs a signal that becomes a high ('H') level only when the output data MDST2, MDST1, and MDST0 are all low ('L') levels.

The NAND gate 624 outputs a signal that becomes a high ('H') level only when the output data MDST1 and MDST0 and the signal output from the inverter 602 are both low ('L') levels.

The NAND gate 626 outputs a signal that becomes a high ('H') level only when the output data MDST0 and the signals output from the inverters 602 and 604 are both low ('L') levels.

The NAND gate 628 outputs a signal that becomes a high ('H') level only when the signals output from the inverters 602, 604, and 606 are all low ('L') levels.

The inverter 608 inputs a signal output from the NAND gate 622, inverts it, and outputs it as a burst length mode signal BLFULL.

The inverter 610 inputs a signal output from the NAND gate 624, inverts it, and outputs it as a burst length mode signal BL8.

The NAND gate 630 outputs a signal that becomes a high ('H') level only when the signals output from the NAND gates 622, 624, 626, and 628 are all low ('L') levels.

The inverter 612 inputs a signal output from the NAND gate 630, inverts it, and outputs it as a burst length mode signal BL1.

The inverter 614 inputs a signal output from the NAND gate 626, inverts it, and outputs it as a burst length mode signal BL2.

The inverter 616 inputs a signal output from the NAND gate 628, inverts it, and outputs it as a burst length mode signal BL4.

The following table is a truth table of the burst length mode signals BL1, BL2, BL4, BL8, and BLFULL which are output according to the combination of the data MDST0, MDST1, and MDST2 input in the circuit of FIG.

TABLE 2

MDST2 MDST1 MDST0 BL1 BL2 BL4 BL8 BLFULL 0 0 0 1 0 0 0 0 0 0 One 0 1 0 0 0 0 One 0 0 0 1 0 0 0 One One 0 0 0 1 0 One 0 0 1 0 0 0 0 One 0 One 1 0 0 0 0 One One 0 1 0 0 0 0 One One One 0 0 0 0 1

As described above, in the synchronous semiconductor memory device, one common pad 340 and a test are required by using the burst length mode signals BL1, BL2, BL4, BL8, and BLFULL output from the mode register setting circuit 330. By controlling the switching means 312 to 320 for electrically connecting the DC voltage generator circuits 302 to 310, the DC voltage generator circuits 302 to 310 are tested with one common pad 340. You can do it. In addition, the burst length mode signals BL1, BL2, BL4, BL8, and BLFULL generated from the mode register setting circuit 330 may include a low address strobe signal RASB, a column address strobe signal CASB, and a chip select signal. The states may be maintained until the mode register setting circuit 330 is enabled again by the (CSB) and the write enable signal WEB. Therefore, when testing the DC voltage generating circuits 302 to 310, the DC voltage level of the DC voltage generating circuits 302 to 310 as well as the operation of the circuit itself is polled through the common pad and thus the chip. You can test the effects on the circuits inside the circuit at the same time.

11 is a flowchart illustrating a pad control method according to a third embodiment of the present invention.

Referring to FIG. 11, the pad control method according to the third exemplary embodiment of the present invention includes a test mode setting step 702, a control signal generation step 704, a circuit selection step 706 to be tested, and an electrical connection step 708. , A test step 710, and another test decision step 720.

The test mode setting step 702 is a step for setting a test mode for circuits requiring a test.

The control signal generation step 704 generates control signals for controlling the connection state between the circuits requiring the test and the common pad after the test mode setting step 702.

The circuit selection step 706 to be tested selects one of the circuits to be tested according to the control signals generated from the control signal generation step 704.

The electrical connection step 708 electrically connects the common pad and the circuit selected in the circuit selection step 706 to be tested.

The test step 710 tests the operation of the selected circuit through a common pad.

The other test decision step 720 determines whether to continue the test for the other circuits requiring the test after the test step 710, and if it continues, starting from the control signal generation step 704 To perform a series of the above steps.

As such, by selecting the circuit to be tested by the control signals generated from the control signal generation step 704 and forming an electrical connection between the one common pad and the selected circuit, a plurality of common pads are used. You can test the circuits. Therefore, even if the pad area decreases as the chip density increases, various circuits requiring a test can be tested. In addition, the control signals generated from the control signal generation step 704 may maintain their states until control signals are generated by the control signal generation step 704 again. Thus, when testing a plurality of circuits, in particular DC voltage generator circuits, the DC voltage levels of the DC voltage generator circuits as well as the operation of the circuit itself are forced through a common pad and thus applied to the circuits inside the chip circuit. The effects can be tested simultaneously.

12 is a flowchart illustrating a pad control method according to a fourth embodiment of the present invention. 12 shows a method of controlling a pad using a mode register setting circuit in a synchronous semiconductor memory device.

12, the pad control method according to the fourth embodiment of the present invention, the mode register setting circuit enable step 802, the address input step 804, the circuit selection step 806 to be tested, the electrical connection step ( 808, a test step 810, and another test decision step 820.

The mode register setting circuit enabling step 802 is to enable the mode register setting circuit.

The mode register setting circuit is controlled by a low address strobe signal (RASB), a column address strobe signal (CASB), a chip select signal (CSB), and a write enable signal (WEB) in a synchronous semiconductor memory device. A circuit for setting a CAS latency, burst type, burst length, and the like. That is, the mode register setting circuit is enabled by the low address strobe signal RASB, the column address strobe signal CASB, the chip select signal CSB, and the write enable signal WEB, and is a combination of input addresses. Determine the CAS latency, burst type, burst length, etc., accordingly to generate CAS latency mode signals, burst type mode signals (not shown), and burst length mode signals. The states of the CAS latency mode signals, burst type mode signals (not shown), and burst length mode signals do not change until the mode register setting circuit is enabled again to set the mode. That is, when the mode register setting circuit is enabled, the CAS latency and burst length are determined according to the combination of the input addresses, thereby enabling one of the CAS latency mode signals and enabling one of the burst length mode signals. Their state does not change until the mode register setting circuit is enabled again to set the mode.

The address input step 804 is a control signal for controlling a connection state between a circuit requiring test and one common pad when the mode register setting circuit is enabled in the mode register setting circuit enabling step 802. Enter the corresponding raw address to generate burst length mode signals.

Circuit selection step 806 selects one of the circuits to be tested according to the burst length mode signals generated according to the raw address combination input in the address input step 804.

The electrical connection step 808 electrically connects the common pad and the circuit selected in the circuit selection step 806 to be tested.

The test step 810 tests the operation of the selected circuit through a common pad.

The other test decision step 820 determines whether to continue the test for the other circuits that need to be tested after the test step 810, and if so, starting from the address input step 804 A series of above steps is performed.

As such, by selecting the circuit to be tested by the control signals generated from the control signal generation step 804 and forming an electrical connection between the one common pad and the selected circuit, a plurality of common pads are used using one common pad. You can test the circuits. Therefore, even if the pad area decreases as the chip density increases, various circuits requiring a test can be tested. In addition, burst length mode signals generated from the mode register setting circuit may be generated by a low address strobe signal (RASB), a column address strobe signal (CASB), a chip select signal (CSB), and a write enable signal (WEB). The states can remain intact until the mode register setting circuit is enabled again. Therefore, when testing DC voltage generator circuits, the operation of the circuit itself, as well as the DC voltage level of the DC voltage generator circuits, is forced through the common pad, thereby simultaneously testing the effects on the circuits inside the chip circuit. Can be.

The present invention has the effect of testing a plurality of circuits using one common pad, in particular in the test of the DC voltage generator circuits present inside the chip, as well as the operation of the DC voltage generator circuit itself, as well as the DC voltage generator circuit The effect of these voltage levels on the internal circuits of the chip has the effect of simultaneously testing. Therefore, it is possible to meet the reality that the pad area is decreasing as the chip density increases.

Claims (18)

A semiconductor device comprising a plurality of circuits requiring a test, One common pad; A test mode control signal generator for generating a test mode control signal activated by the user in a test mode; A register circuit that is enabled in a test mode by a test mode control signal and inputs and stores data from a plurality of pins; A control signal generator for inputting data stored in the register circuit to generate a plurality of control signals according to the data; Each of the plurality of circuits is connected between a corresponding circuit and the common pad, and the corresponding circuit is electrically connected to the pad according to a corresponding control signal among a plurality of control signals generated from the control signal generator. It has a plurality of switching means for connecting to, And the control signal generator activates only one of the plurality of control signals according to a user's request. The pad control circuit of claim 1, wherein the plurality of circuits include DC voltage generator circuits. The apparatus of claim 1, wherein the plurality of switching means are respectively controlled by the corresponding control signal, and transmit a signal from the corresponding circuit among the plurality of circuits to the pad or transmit a signal from the pad. Pad control circuit comprising a switching element for transmitting to a corresponding circuit among the circuits of the. 4. The pad control circuit according to claim 3, wherein said switching element is a transfer gate. The pad control circuit of claim 1, wherein the test mode control signal generator generates a test mode control signal that is activated only when all control signals required for normal operation of the chip circuit are not active. The test mode control signal generator of claim 5, wherein the test mode control signal generator is activated only when the low address strobe signal, the column address strobe signal, the write enable signal, and the chip select signal are not all active in the semiconductor memory device. And a mode control signal. The method of claim 5, wherein the test mode control signal generator A first NAND gate for outputting a high level signal only when all control signals required for normal operation of the chip circuit are not active; A first inverter inputting an output of the first NAND gate and inverting the output of the first NAND gate; A second NAND gate inputting data from a plurality of pins and outputting a signal having a high level only when the combination of the data corresponds to a predetermined combination; A second inverter inputting an output of the second NAND gate and inverting the output of the second NAND gate; And And a third NAND gate for outputting a high level signal as the test mode control signal only when the outputs of the first inverter and the second inverter are both at a low level. The method of claim 1, wherein the register circuit, A first inverter that inputs an address and inverts and outputs the address; A transmission gate controlled by the enable signal to transmit an output from the first inverter; A latch unit configured to input and latch a signal transmitted from the transmission gate; Precharge means for precharging the input of the latch portion to a low level before the register circuit is enabled by the enable signal; And And a driving unit for driving a signal latched in the latching unit. The method of claim 1, wherein the control signal generator, And decode the data stored in the register circuit and output the decoded data as the control signals. A synchronous semiconductor device comprising a plurality of circuits and a mode register setting circuit requiring a test, One common pad; A test mode control signal generator for generating a test mode control signal activated by the user in a test mode; Enabled in the test mode by the test mode control signal, the mode register setting for inputting and storing raw address data from the raw address buffer circuit and generating burst length mode signals and CAS latency mode signals according to the raw address data. Circuit; Each of the plurality of circuits is connected between a corresponding circuit and the common pad, and according to the corresponding burst length mode signal generated from the mode register setting circuit, according to the corresponding burst length mode signal. And a plurality of switching means for electrically connecting a circuit to the pad. 12. The test mode control signal generator of claim 10, wherein the test mode control signal generator generates a test mode control signal that is active only when the low address strobe signal, the column address strobe signal, the write enable signal, and the chip select signal are not all active. And a pad control circuit. 12. The apparatus of claim 11, wherein the test mode control signal generator A first NAND gate for outputting a high level signal only when the low address strobe signal, the column address strobe signal, the write enable signal, and the chip select signal are not all active; A first inverter inputting an output of the first NAND gate and inverting the output of the first NAND gate; A second NAND gate inputting data from a plurality of pins and outputting a signal having a high level only when the combination of the data corresponds to a predetermined combination; A second inverter inputting an output of the second NAND gate and inverting the output of the second NAND gate; And And a third NAND gate for outputting a high level signal as the test mode control signal only when the outputs of the first inverter and the second inverter are both at a low level. The pad control circuit as claimed in claim 10, wherein the plurality of circuits are DC voltage generator circuits. The pad control circuit of claim 13, wherein the one common pad is not included as a chip circuit in a process of packaging a corresponding chip. 11. The apparatus of claim 10, wherein the plurality of switching means are each controlled by the corresponding burst length mode signal, and transmit a signal from the corresponding circuit among the plurality of circuits to the pad or receive a signal from the pad. And a switching element for transmitting to a corresponding circuit among the plurality of circuits. 16. The pad control circuit of claim 15, wherein the switching element is a transfer gate. In a semiconductor device, Setting a test mode; A control signal generation step of generating control signals for controlling a connection state between circuits requiring a test and a common pad after the test mode setting step; A circuit selecting step to test selecting one of the circuits according to the control signals generated from the control signal generating step; An electrical connection step of electrically connecting between the circuit selected in the circuit selection step to be tested and the common pad; Testing the operation of the selected circuit through the common pad; And Determining whether to continue the test for the other circuits after the test step, and in case of continuing the test step, another test determining step for performing the series of steps from the control signal generation step, The control signal generating step may activate only one of the control signals to test a plurality of circuits using one of the common pads. A synchronous semiconductor device having a plurality of circuits and a mode register setting circuit requiring a test, Enabling a mode register setting circuit to enable the mode register setting circuit to test the plurality of circuits; An address input for inputting a raw address corresponding to the mode register circuit to use burst length mode signals as control signals for controlling a connection state between the plurality of circuits and the common pad after the mode register setting circuit enabling step step; A circuit selecting step to test selecting one of the plurality of circuits according to the burst length mode signals generated from the address input step; An electrical connection step of electrically connecting between the circuit selected in the circuit selection step to be tested and the common pad; Testing the operation of the selected circuit through the common pad; And After the test step, it is determined whether to continue the test for the other circuits, and if it is carried out continuously, another test whether to determine whether to perform a series of steps from the control signal generation step, And a plurality of circuits can be tested using a common pad.