KR19980077380A - 9 * 9 Matrix Time Switching Device of Electronic Switching System - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Electronic exchanger

2. The technical problem to be solved by the invention

The purpose of this paper is to solve the complexity of processor control, a large number of circuit packs, and the difficulty of maintaining a time switch when a conventional 5 * 5 matrix time switching device is implemented in a large-capacity electronic switch.

3. Summary of Solution to Invention

A 9 * 9 matrix call memory unit 100 for inputting channel data and switching and outputting the channel data under the control of the 1 * 9 matrix address control memory unit 200; A 1 * 9 matrix address control memory unit 200 for controlling type switching of a signal input to the 9 * 9 matrix call memory unit 100; A processor (300) for controlling the 1 * 9 matrix address control memory (100) to list an output address for performing time switching to a corresponding 1 * 9 matrix address control memory (200); The 1 * 9 matrix address control memory unit 200 is characterized by consisting of a sequential address generator 400 for generating a sequential address so as to sequentially read the value written by the processor 300.

4. Intended Use

This is applied to time switching of electronic exchange.

Description

9 * 9 Matrix Time Switching Device of Electronic Switching System

In general, an electronic switch is a device that replaces most of the electromechanical devices constituting the exchanger with electronic parts, and performs an exchange connection function, a charge and maintenance operation function between the sender and the receiver.

In the related art, a 2 * 5 * 5 matrix input / output device having a capacity of 2k was used for a time switch of an electronic exchanger.

As shown in FIG. 1, a conventional all-electronic switch time switch having such a function receives channel data as input and switches the channel data under the control of the 1 * 5 matrix address control memory 70. A 5 * 5 matrix call memory section 60 for outputting; A 1 * 5 matrix address control memory unit 70 for time-switching the signal input to the 5 * 5 matrix call memory unit 60 under the control of a processor 80; A processor (80) for controlling the 1 * 5 matrix address control memory (70) to write an output address for performing time switching to a corresponding 1 * 5 matrix address control memory (70); The 1 * 5 matrix address control memory unit 70 includes a sequential address generator 90 that generates a sequential address so that the value written by the processor 80 can be sequentially read. It became.

Referring to the operation of the conventional electronic switch 5 * 5 matrix time switching device configured as described above are as follows.

First, when channel data each having a capacity of 2k is input to the call memory unit 60 having a 5 * 5 matrix structure, the processor 80 controls the 1 * 5 matrix address control memory unit 70, and thus 1 * 5. The matrix address control memory unit 70 performs time switching based on 16.384 MHz of the sequential address generator 90 as a basic clock. As a result, the 5 * 5 matrix call memory unit 60 outputs channel data each having a capacity of 2k. .

Here, 2k channel data used in the 5 * 5 matrix time switch structure consists of 64 subhighways * 32 channels, and one subhighway consists of 32 channels and has a transmission rate of 2.028 Mbps. That is, 32 channels of serial data having a transmission rate of 2.028 Mbps are called one subhighway, and 2k capacities of 64 subhighways * 64 channels having multiplexed 32 subhighways are input to each matrix.

Channel data having a capacity of 2k is input and output to the 5 * 5 matrix time switch. This is an input channel for signal service which provides a signal service for input channel data for first and second subscribers, input channel data for first and second optical links, and channel data for first and second subscribers each having a capacity of 2k. It consists of data. Therefore, in the 5 * 5 matrix time switch device, since 4k is subscriber channel data, 4k is for optical link connection, and 2k is for subscriber channel signal service, the time switch capacity of 5 * 5 matrix structure becomes 4k * 4k. .

The channel data of 2k capacity is sequentially stored in the 5 * 5 matrix call memory unit 60. That is, the first subscriber input channel data is the first time switch memory to the fifth time switch memory 11-15, and the second subscriber input channel data is the sixth time switch memory to the tenth time switch memory 21-25. ), The input channel data for the first optical link is the eleventh time switch memory 31 to 35, and the input channel data for the second optical link is the sixteenth time switch memory to the twentieth time switch memory 41. 45, the input channel data for the signal service is stored in the twenty-first time switch memory to the twenty-fifth time switch memory 51 to 55, respectively.

Then, the processor 80 writes an output address for performing time switching to the corresponding 1 * 5 matrix address control memory 70, wherein the first to fifth addresses of the 1 * 5 matrix address control memory 70 are controlled. The memory devices 71-75 are read by 16.384 MHz generated by the sequential address generator 90. Data read from the first address control memory 71 is addressed to the first, sixth, eleventh, sixteenth, and twenty-first time switch memories 11, 21, 31, 41, and 51. do. The second to fifth address control memory devices 72 to 75 also perform time switching by addressing in the same manner as the first address control memory device 71 described above.

Therefore, input of channel data each having 2k capacities is performed by the time switching device having a 5 * 5 matrix structure, output channel data for first and second subscribers having 2k capacities, output channel data and signal service for first and second optical links, respectively. Is converted into output channel data for output.

However, the conventional 5 * 5 matrix type switching device that is input and output at a 2k capacity as described above has a problem in that the amount of time switches is relatively large when processing more than 4k * 4k capacity, which complicates the processor to be controlled.

Another problem is that the construction of a high-capacity electronic switchboard requires the preparation of a large space for the installation of a large number of processors and circuit packs, and the maintenance of the electronic switchboard switching device due to the complexity of the optical link for space switch connection is quite difficult There was also a loss.

Accordingly, the present invention has been proposed to solve the above problems of the conventional all-electron exchanger time switching device, and an object of the present invention is to provide a 4k-capacity 9 * 9 matrix structure for a processor and To provide a 9 * 9 matrix time switching device that reduces the number of circuit packs, simplifies the optical link, and facilitates maintenance of the time switching device.

Technical means for achieving this object of the present invention;

A 9 * 9 matrix call memory unit for inputting channel data and switching and outputting the channel data under the control of the 1 * 9 matrix address control memory unit; A 1 * 9 matrix address control memory for controlling the time switching of the signal input to the 9 * 9 matrix call memory; A processor configured to control the 1 * 9 matrix address control memory to write an output address for performing time switching to a corresponding 1 * 9 matrix address control memory; The 1 * 9 matrix address control memory unit includes a sequential address generator for generating sequential addresses so as to sequentially read the values written by the processor.

Hereinafter, the configuration and operation of the present invention in detail as follows.

1 is a block diagram of a 5 * 5 matrix time switching device of a conventional total exchanger

2 is a block diagram of a 9 * 9 matrix time switching device of an all-electron exchanger according to the present invention.

* Description of the symbols for the main parts of the drawings *

100: call memory unit 200: address control memory unit

300: processor 400: sequential address generator

2 is a block diagram of an all-electronic exchange 9 * 9 matrix time switch according to the present invention.

As shown, a 9 * matrix call memory unit 100 for inputting channel data and under control of a 1 * 9 matrix address control memory unit 200 to switch and output the channel data; A 1 * 9 matrix address control memory unit 200 for controlling the time switching of a signal input to the 9 * 9 matrix call memory unit 100; A processor (300) for controlling the 1 * 9 matrix address control memory (100) to write an output address for performing time switching to a corresponding 1 * 9 matrix address control memory (200); The 1 * 9 matrix address control memory unit 200 includes a sequential address generator 400 for generating a sequential address so as to sequentially read the values written by the processor 300.

Referring to the accompanying drawings, the operation of the all-electron exchanger 9 * 9 matrix time switching device according to the present invention configured as described above is as follows.

When the 4k channel data is input to the call memory unit 100 having a 9 * 9 matrix structure, the processor 300 controls the 1 * 9 matrix address control memory unit 200 and accordingly 1 * 9. The matrix address control memory unit 200 controls an address to time-switch the 32.768 MHz generated by the sequential address generator 400 as a basic clock, so that the 9 * 9 matrix call memory unit 100 can respectively store 4k channel data. Output by time switching.

The 4k channel data used in the 9 * 9 matrix time switch structure consists of 64 subhighways * 64 channels, and one subhighway consists of 64 channels and has a transmission speed of 4.096 Mbps. That is, 64 channels of serial data having a transmission rate of 4.096 Mbps are called one subhighway, and 4k capacities of 64 subhighways * 64 channels obtained by multiplexing 64 subhighways are input to each matrix.

In the 9 * 9 matrix type switch, channel data having a capacity of 4k is input. The input data may include first to fourth subscriber channel data for a 4k subscriber signal, first to fourth optical link channel data for connection to a spatial switch, and first to fourth subscriber channel, respectively. It consists of channel data for signaling services that provide signaling services to data. Therefore, in the 9 * 9 matrix time switch, 16k is subscriber channel data, 16k is for optical link connection, and 4k is for subscriber channel signal service, so the time switch capacity of the 9 * 9 matrix structure is 16k * 16k.

Input channel data having a capacity of 4k is sequentially stored in the 9 * 9 matrix call memory unit 100. That is, the first subscriber input channel data is stored in the first time switch memory to the ninth time switch memory 11-19, and in the same manner, the second to fourth subscriber input channel data are also 9 * 9 matrix calls. It is stored in the time switch memories 21-49 in the memory section 100. Input channel data for the first optical link is stored in the 37th to 45th time switch memories 51 to 59, and in the same manner, the input channel data for the second to fourth optical links is 9 * 9 matrix. It is stored in the time switch memories 61-89 in the call memory section 100. Similarly, input channel data for signal service is stored in the 73rd time switch memory to the 81st time switch memory 91 to 99.

Meanwhile, the processor 300 writes an output address for performing time switching to the corresponding 1 * 9 matrix address control memory 200, where the first to ninth addresses of the 1 * 9 matrix address control memory 200 are performed. The control memory devices 201-209 are read by the 32.768 MHz clock of the sequential address generator 400. The data read from the first address control memory 201 is first, tenth, nineteenth, twenty-eighth, thirty-seventh, sixty-fourth, fifty-five, sixty-fourth, and seventy-seventh time switch memories 11 (21). (31) (41) (51) (61) (71) (81) and (91). The second to ninth address control memory devices 202-209 are also addressed in the same manner as the first address control memory device 201 so that time switching is performed.

In other words, when the 9 * 9 matrix currency memory unit 100 is called matrix SMxy, x is an input for performing time switching, and y is an output for performing time switching; When the 1 * 9 matrix address control memory unit 200 is referred to as matrix CMz, z designates y to be output to the x input of the matrix SMxy of the matrix currency memory unit 100. That is, z is a factor controlling the direction to be output with respect to the input x, and when x is to be output as y, z = y is outputted so that the call memory SMxy having y = x is output for the input x.

Therefore, the input of channel data each having 4k capacities is performed by the time switching device having a 9 * 9 matrix structure, and output channel data for the first to fourth subscribers, output channel data for the first to fourth optical links, and signal services, respectively, having 4k capacities. Is converted to output channel data.

Thus, the 16k capacity of the first to fourth subscriber channel data for the subscriber signal and the 16k capacity of the first to fourth optical link channel data for the spatial switch are combined through a 9 * 9 matrix structure and thus 16k. Implemented as a time-switching device for an all-electronic exchanger of 16k capacity.

As described in detail above, the present invention has a 16k * 16k capacity by using a 9 * 9 matrix in an all-electron exchanger time switching device. The subscriber channel is up to four times larger than the in-time switching device, resulting in up to four times less processor circuit packs and simplified processor control to control the time switches.

In addition, since the optical link for connection with the space switch is composed of 4 * 4k, the maintenance of the time switch is easy due to the simplification of the optical link.

The present invention relates to a time switching device of an all-electronics exchanger, which implements a time switching device having a time switch capacity of 16k * 16k using a 9 * 9 matrix structure to simplify processor control and maintain time switches. .

Claims (4)

In the electronic switch time switching device, A 9 * 9 matrix call memory unit 100 for inputting channel data and switching and outputting the channel data under the control of the 1 * 9 matrix address control memory unit 200; A 1 * 9 matrix address control memory unit 200 for controlling the time switching of a signal input to the 9 * 9 matrix call memory unit 100; A processor for controlling the 1 * 9 matrix address control memory unit 100 to write an output address for performing time switching to a corresponding 1 * 9 matrix address control memory unit 200; The 1 * 9 matrix address control memory unit 200 comprises an sequential address generator 400 for generating sequential addresses so as to sequentially read the values written by the processor 300. 9 * 9 Matrix Time Switching Device. The method according to claim 1, wherein the 9 * 9 matrix currency memory unit 100, A 9 * 9 matrix time switching device of an all-electronic exchange, characterized in that the input / output channel data of each matrix has a capacity of 4k. The method of claim 2, wherein the 4k channel data, 64 subhighway * 64 channels, each subhighway has a transmission rate of 4.906 Mbps 9 * 9 matrix time switching device of the electronic switchboard. The method according to claim 1, wherein the sequential address generator 400, 9 * 9 matrix time switching device of an all-electronic exchange, characterized in that it generates a basic clock of 32.768MHz.