KR19980074301A - Fuse layout method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse layout method for a semiconductor device, wherein the fuse is configured to have at least two fuses in parallel therebetween for selecting a path between the wirings in the chip, thereby reducing the delay time caused by the fuse. Can be reduced.

Description

Fuse layout method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method of constructing a fuse used to select a path.

1 is a detailed circuit diagram of a row redundant block generally used in a semiconductor memory device.

In FIG. 1, the input of the circuit is the outputs of the address buffer ( ) To (A ₀ · A ₁ ) are applied and the signal ( ) Is the output of the address buffer for selecting a block. Transistors M1, M4, and MR are small transistors needed to prevent the input of the NAND gate from floating when the fuses F0, F4, FR, etc. are blown. . The signal REN is a signal that becomes high and activates the redundant word line SWLR when there is a problem in the cell associated with one of the word lines SWL0 to SWL4.

A brief description of the operation of this circuit follows. In the case of a prime working die without defects in them in an array with a plurality of memory cells for storing information, the signal REN is kept at a low level so that the redundant word line SWLR is It is always kept low. If a failure occurs in a memory cell connected to the word line SWL0 and a fail occurs, the fuse F0 is turned off. As a result, the word line SWL0 is output from the address buffer ( The memory cell is selected at low level and the signal REN is at the high level. Instead, the redundant word line SWLR is at the high level, and the memory cell is selected, thereby replacing the memory cell. In other words, it can be seen that the path is selected by the fuse in such a circuit.

In such circuits the material of the fuse is basically a conductor. However, a fuse assumed to be a conductor has its own sheet resistance, depending on the material. In general, polysilicon has a value of 5 to 10 ohms and aluminum has a value of 0.004 to 0.08 ohms. Will become large. The reason is that the main word line (MWL) is usually placed over the memory array, so it is usually about 10000μ length, resulting in a capacitance value of several pF.

2 is a plan view showing a conventional laser fuse configuration. Referring to FIG. 2, a fuse having a predetermined width W as a means for selecting a circuit path for electrically connecting or disconnecting the first and second conductive regions 10 and 20 which are not interconnected. (fuse) is connected.

Fuses are essential in constructing a redundancy circuit in a semiconductor memory device. The 4n synchronous static RAM currently in development uses multi-layer-metal, and only polysilicon is the gate poly 1 layer. Since various metals are formed after polysilicon, an oxide has a thickness of 4 to 5 mu. Thus, it has become difficult to use polysilicon as a fuse.

If you want to change the fuse material to aluminum, the metal will not be cut using current laser fuse cutting equipment. Thus, the fuse material developed as a substitute material is titanium nitride (TiNitride, hereinafter referred to as TiN). Forming a material (TiN) on such a wafer and forming aluminum on top of it and etching only aluminum to have a predetermined width on the paste (TiN) results in a fuse made of only the material (TiN).

However, in the case of a fuse having the above structure, its sheet resistance is about 4 to 5 times higher than that of conventional polysilicon, and as a result, by using a redundancy circuit using a fuse having the above structure provided in a semiconductor memory device. There is a problem that the signal delay time increases.

Accordingly, an object of the present invention is to provide a method of laying out a fuse thereof to improve the operation speed of a semiconductor memory device, which has been proposed to solve the above-mentioned problems.

1 is a circuit diagram showing a schematic circuit of a redundancy decoder of a general semiconductor device;

2 is a plan view showing a fuse layout according to the prior art;

3 is a plan view showing a fuse layout according to an embodiment of the present invention;

4 is a waveform diagram showing delay times according to the prior art and the present invention;

* Description of symbols on the main parts of the drawings *

10: first conductive region 20: second conductive region

According to one aspect of the present invention for achieving the above object, a fuse layout method of a semiconductor device having conductive regions for transmitting predetermined signals, comprising: a first conductive region separated from each other among the conductive regions; At least two path selection means for electrically connecting or disconnecting the second conductive region are connected to them in parallel.

In this embodiment, the path selection means is formed of one of polysilicon, aluminum, and titanium nitride.

By this method, it is possible to reduce the sheet resistance by configuring the fuses so that at least two fuses are selected in parallel therebetween in order to select a path between the wirings in the chip.

Reference will be made in detail below with reference to FIGS. 3 to 4 according to an embodiment of the present invention.

Referring to FIG. 3, in the fuse layout method of the novel semiconductor device of the present invention, when a fuse for selecting a path is configured, at least two or more fuses are laid out in parallel to perform high-speed operation using the fuse. It is possible to prevent the delay time from being increased by circuits in the device.

3 is a plan view illustrating a structure of a fuse of a semiconductor device according to an exemplary embodiment of the present invention. Referring to FIG. 3, fuses having a predetermined width W for electrically connecting / disconnecting the first conductive region 10 and the second conductive region 20 which are not interconnected are arranged in parallel over each one of them. Connected. If the area is allowed, the more two or more, the lower the resistance value of the fuse in parallel. As a result, latency is enjoyed.

And, even if the width (W) of the fuse shown in FIG. However, in this case, when the width is wider, there is a limit in the beam size of the laser fuse cutter which cuts the fuse, which is a method that actually has some difficulties.

Figure 4 is a waveform diagram showing the results of the simulation according to the fuse layout of the prior art and the present invention.

As shown in FIG. 4, in the conventional case under the same voltage, the main word line according to the present invention is better than the delay time generated on the main word line MWL0 and the redundancy word line SWL0 by the fuse. It can be seen that the delay time generated on the MWLO and the redundancy word line SWL0 is reduced by the time t.

As described above, it is possible to reduce the delay time caused by configuring the fuses so that at least two fuses are selected in parallel therebetween in order to select paths between the wirings in the chip.

Claims (2)

A fuse layout method of a semiconductor device having conductive regions for transmitting predetermined signals, the method comprising: At least two path selection means for electrically connecting or disconnecting the first conductive region and the second conductive region separated from each other among the conductive regions are connected to them in parallel. . The method of claim 1, And the path selection means is formed of one of polysilicon (poly Si), aluminum (Al), and titanium nitride (TiN).