KR19980073685A - Manufacturing method of nonvolatile semiconductor memory device with enhanced device isolation characteristics - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a nonvolatile semiconductor memory device, wherein the active region and the field oxide film are formed on a semiconductor substrate, ion implantation for device isolation, and selection transistors and peripheral regions except memory cells for adjusting threshold voltage values of memory cells. An ion implantation for the channel stop layer is performed, and a mask pattern for implanting a first ion for device isolation of memory cells and a second implantation pattern for forming a depletion select transistor are implemented in one pattern. Accordingly, the first and second ion implants may be simultaneously performed to improve device insulation characteristics while reducing the number of masks.

Description

Manufacturing method of nonvolatile semiconductor memory device with enhanced device isolation characteristics

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a method of manufacturing a nonvolatile semiconductor memory device having enhanced device isolation characteristics.

In general, one cell in a nonvolatile memory device has a floating gate, a control gate, and a source and drain diffusion region. An interlayer insulating film is interposed between the floating gate and the control gate, and a tunnel oxide film of about 90 kV is interposed between the floating gate and the substrate. The charge is stored in the floating gate through the tunnel oxide film, and the stored charge (data) has a nonvolatile characteristic that the data is maintained even when the power supply disappears. In particular, a flash memory nonvolatile semiconductor device capable of collective erasing of data has been in the spotlight as a solid state storage device in recent years. In order to be used as such a memory device, high capacity is essential through high integration, and the cell structure which is most advantageous for high integration is 1988 IEDM TECH. DIG. In PP412-415, NEW DEVICE TECHNOLOGIES FOR 5V ONLY EEPROM WITH NAND STRUCTURE CELL. The contents disclosed in the above paper are shown in FIG. 1. As shown in FIG. 1, the higher the density, the weaker the margin of the contact region becomes. This means that the distance a between the active region A and the contact BLC and the insulation distance b between the bit line MBL and the bit line MBL become smaller. In addition, the metal overlap c of the contact BLC becomes smaller and the distance d between the metal and the metal becomes smaller. Therefore, a structure having one contact in one bit line as described above is inevitably limited to high integration. The proposed technique to solve this problem is shown in U.S. Patent 4,962,481, which, as shown in FIG. 2, forms one bit line contact (BLC) on two bit lines (MBL). In this regard, it is possible to secure twice the area margin compared to the prior art. On the other hand, before describing the problem, in operation of the nonvolatile memory cell structure illustrated in FIG. 2, the program voltage is applied to a word line at write time to cells of the nonvolatile memory device and 0V is applied to a channel of the memory cell. By applying a voltage, electrons pass through the tunnel oxide film and are charged in the floating gate. However, in the cell layout of the above structure, since a plurality of memory cells are connected to one word line, the program voltage is simultaneously transmitted. Therefore, in order to program the cell to be programmed and the cell not to be programmed, the voltage transferred from the bit line MBL to the channel is different. That is, the select bit line applies a 0V voltage to increase the voltage between the word line and the channel, thereby increasing the potential difference, and the unselected cell applies a predetermined program suppression voltage to the voltage difference between the word line and the channel. To make the program smaller. However, in the case of independent of one bit line, different voltages may be applied to the selected bit line and the non-selected bit line. However, in the nonvolatile semiconductor memory cell layout shown in FIG. 3, two bit lines are divided into one bit line. Since the line contact BLC and the metal MBL are shared with each other, the same voltage is applied to the two channels. In order not to write or write to the bit line sharing such a contact, the channel is precharged by applying a predetermined voltage to the two select transistors consisting of the depletion type (D) 4 and the increasing type and the bit line. The potential between the channel and the word line is increased and programmed by discharging the channel voltage of the selected bit line by the combination of (D) and the increasing transistor.

However, since the operating voltage is selected or not selected by the time difference, if an error occurs at this time, a malfunction occurs, and the parasitic capacitor or noise is vulnerable. When the precharged voltage is lost due to the leakage current, a malfunction occurs in which the non-selected cell is programmed.

The proposed technique to solve this problem is presented in FIG. That is, after forming the word line, the memory array is formed of polysilicon (hereinafter referred to as plate polysilicon) to increase the capacitive coupling efficiency of the floating gate and the control gate. In addition, the capacitive coupling efficiency of the channel region is increased to increase the voltage caused on the channel of the unselected bit lines. Therefore, the program of the non-selected cell is prevented. However, this presents a vulnerability to operational field isolation. In the plan view of FIG. 3, a vertical structure along cut surfaces of A-A ′, B-B ′, and C-C ′ will be briefly described with reference to FIGS. 4 to 10. Since the program voltage is applied to the word line 24 and the plate line 20 during programming, according to the cutting plane C-C ', 0V is applied to the junction 30a of the selected bit line and the program suppression voltage is applied to the junction 30b of the unselected bit line. A field transistor is formed using the oxide film 10 as a gate. The threshold voltage of this field transistor should be higher than the program voltage. Factors controlling the threshold voltage are the thickness of the field oxide film and the concentration of the channel doping layer (or channel stop layer) 2. Further, according to the cut surface B-B ', parasitic field transistors are formed by the junction 30 of the selected bit line and the junction 30d of the unselected bit line, similarly to the cut surface A-A'. The threshold voltage of the transistor depends on the thickness of the field oxide film and the channel concentration 2. Increasing the thickness of the field oxide layer to increase the threshold voltage of the transistor is not possible for high integration and the concentration of channel doping 2 must be increased. In order to increase the channel concentration of the region, a pattern in which only the region is opened (pattern 14 of FIG. 4 for opening two regions of FIG. 3) by a separate mask is formed, and channel stop ion implantation is performed. However, this is a problem that requires an additional mask step.

An object of the present invention for solving the above problems is to provide a method of manufacturing a nonvolatile semiconductor memory device for improving the insulating properties between devices.

Another object of the present invention is to provide a method of manufacturing a nonvolatile semiconductor memory device having improved device isolation without an additional mask step.

1 to 10 are views illustrating a NAND cell array and a cross-sectional view thereof of a nonvolatile semiconductor device presented for describing the prior art,

11 is a plan view illustrating a NAND cell array of a nonvolatile semiconductor memory device according to an embodiment of the present invention;

12 to 16 are vertical cross-sectional views of FIG. 11 taken along the lines D-D ', E-E', and F-F '.

The technical idea of the present invention for achieving the above objects is a field oxide film and an active region on the main surface of the semiconductor substrate, a plurality of select transistors and memory cells are connected in series to the active region, and one end of the bit line A method of manufacturing a nonvolatile semiconductor memory device in contact, comprising: implanting field ions into the selection transistor region and the peripheral region except for the memory cell region, and channeling only a portion of the lower portion of the field oxide layer corresponding to the memory cell region And simultaneously forming the mask pattern for stopping the first ion implantation and the mask pattern for the second ion implantation for adjusting the threshold voltage of the depletion type select transistor to perform the first and second ion implantation. It features.

Hereinafter, an embodiment of a method of manufacturing a nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to the drawings, and in order to help a thorough understanding of the present invention, various vertical elements of the elements in the nonvolatile semiconductor memory device are shown in the drawings. Cutting planes are provided schematically. In addition, various specific details are shown in the drawings, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific matters to those skilled in the art. It will be self explanatory.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 11 is a plan view illustrating a NAND cell array of a nonvolatile semiconductor memory device according to an embodiment of the present invention, and FIGS. 12 through 16 illustrate D-D ′, E-E ′, and F-F ′ of FIG. 11. These are vertical cross-sectional views cut in the direction.

Referring to FIG. 11, two adjacent memory cells share one bit line (MBL), and the memory cells are formed between a selection transistor configured to be an incremental and depletion type for selecting the bit line and a selection transistor for selecting ground. It is connected in series. Referring to FIG. 12, field oxide films 10 are formed on the main surface of the semiconductor substrate 8 to define active regions. Each active region may be formed with diffusion regions of a selection transistor and diffusion regions of memory cells. A photoresist pattern 14 is formed on all surfaces of the semiconductor substrate 8 to protect respective active regions and have holes open on the field oxide films 10. Pattern 14 also opens the channel portion of the depletion select transistor. Ion implantation is performed based on the open holes to form channel stop layers 2 under the field oxide films 10. Ion implantation is performed at about 2 × 10 ¹³ / cm 3 with boron ions at an energy of about 100 to 170 KeV, wherein the boron ions are ion implanted into the channel region of the depletion select transistor. However, when the ion is implanted with an energy of about 150 KeV as an active region, Rp is formed at a depth of about 0.3 to 0.45 µm on the surface, and thus does not significantly affect the characteristics of the depletion type transistor. This may be a factor that can increase the threshold voltage slightly because the ion implantation dopant is the same conductivity type as the bulk of the depletion select transistor, but other factors are not concerned and the threshold voltage of the depletion select transistor is the depletion type of the depletion transistor. It depends on the amount of ion implantation dose. Therefore, ion implantation is performed in an acenic to control the threshold voltage of the depletion type select transistor, and the ion is implanted at about 6 × 10 ¹² with energy of about 30 KeV to 180 KeV depending on the thickness of the oxide layer on the active region. The threshold voltage value of -2.0V comes out. At this time, since the channel ion implantation region of the field oxide film is also open, dopants are ion implanted in the region, but when the energy proceeds to the energy, Rp is about 0.02 μm to 0.08 μm, and the field oxide film is about 0.3 μm. Masking is not introduced into the silicon, so there is no effect. Thereafter, as shown in FIG. 13, the floating gate 20 is defined by forming a pattern for separation of the floating gate 20. FIG. 14 shows that an interlayer insulating film 22 is formed and polysilicon 24 used as a control gate is deposited. 15 and 16 illustrate a process in which an insulating film is formed after the word line formation is completed and the plate polysilicon is deposited to complete the process.

The invention is not limited to the specific embodiments described herein as the best way contemplated for carrying out the invention, but should be defined by the equivalents of the claims as well as the claims set out below. .

As described above, according to the present invention, it is possible to reduce the mask process of one step by proceeding the channel stop ion implantation for device isolation and the ion implantation for the depletion layer formation of the depletion select transistor in the prior art in the same mask. Accordingly, the process can be simplified, and even though the same mask is used, the ion implanted Rp is different from each other and thus there is no detrimental effect on the characteristics of the device, and thus the device isolation and the depletion select transistor can be simultaneously satisfied.

Claims (4)

A method of manufacturing a nonvolatile semiconductor memory device in which a field oxide film and an active region are connected to a main surface of a semiconductor substrate, a plurality of selection transistors and memory cells are connected in series with one end thereof and in contact with a bit line. Implanting field ions into the selection transistor region and the peripheral region except for the memory cell region; Only a portion of the lower portion of the field oxide layer corresponding to the memory cell region is simultaneously formed by forming a mask pattern for the first ion implantation for channel stop and a mask pattern for the second ion implantation for adjusting the threshold voltage of the depletion select transistor. And performing the first and second ion implantation. The method of claim 1; And the memory cell comprises a floating gate and a control gate interposed therebetween. The method of claim 1, wherein the first ion implantation is performed at about 2 × 10 ¹³ / cm 3 with boron ions at an energy of about 100-170 KeV. 2. The method of claim 1, wherein the second ion implantation is performed using a dose such that the threshold voltage of the depletion type select transistor is about −2.0 V with the energy of about 30 to 180 KeV.