KR19980072455A - Apparatus and method for half-pixel motion estimation for video encoder - Google Patents

Abstract

The present invention relates to a half-pixel motion estimation apparatus and method for a video encoder, and reduces the number of clocks used in the operation to be implemented as a real-time system using 4SS, and adds one step to the half-pixel motion It can be used for estimation and motion compensation, and 4SS is better than TSS and requires fewer clocks than FSS. Therefore, it is suitable for real-time system and image data can be input at 6.5MHz. In this case, we propose a search algorithm that can operate the system at about 27MHz and estimate a larger motion vector so that it is excellent in performance and can be efficiently applied to implement video encoders such as MPEG-1 and MPEG-2 in VLSI. It is.

Description

Apparatus and method for half-pixel motion estimation for video encoder

The present invention relates to a half-pixel motion estimation apparatus and method for a video encoder. In particular, a four-step search algorithm (4SS) reduces the number of clocks required for an operation to be implemented in a real-time system. The present invention relates to an apparatus and method for estimating a half-pixel unit for a video encoder, which adds one step for determining a motion compensation while estimating a motion.

In recent years, video compression technology is expanding its applications such as multimedia communication, video, phone, teleconference HDTV, CD-ROM, etc., and the core of video compression technology is redundancy of temporal and spatial information that can occur in video signals. It is a well known fact that it is in use.

Among various compression techniques for image compression, video motion compensation encoding is widely used.

Motion compensation coding consists of a part that compensates for motion by motion estimation and a part that encodes a prediction error. In motion vector estimation, a block matching algorithm (BMA) is most commonly used in consideration of similarity of motion information. have.

In the block matching algorithm, many algorithms such as Full Search Algorithm (FS), Three Step Search Algorithm (TSS), Hierarchical Search Algorithm (HS), and Four Step Search Algorithm (4SS) are published in the paper, and some algorithms are actually implemented. It is used.

However, in the conventional block matching algorithm as described above, FS has the best performance but requires a large amount of computation, which makes it difficult to implement in real time. HS is the most ideal form of a high-speed algorithm, but also has a large amount of computation and a VLSI structure for implementing the algorithm. It was so complicated that it was hard to be put into practical use.

The TSS shows an inefficient aspect in the real image because it considers the probability of all motion vectors equally without considering the statistical motion vectors.

On the other hand, 4SS is known to have higher efficiency than TSS without requiring as many operations as FS.

In addition, although many algorithms for motion estimation have been proposed, studies on the VLSI structure for implementing the algorithm are still insufficient.

In addition, as the video compression technology requires compression not only for MPEG1 but also for MPEG2 video, the MPEG2 model requires a wider search window for extracting motion vectors. There is a need for a real-time motion vector estimator.

Accordingly, the present invention provides a half-pixel motion estimation apparatus and method for a video encoder having a VLSI structure of a motion vector estimator using a 4SS algorithm for a real-time motion vector estimator and a linear approximation half-pixel estimation method. The purpose.

In addition, by adopting E4SS (Extended 4 Step Search Algorithm) modified and expanded 4SS algorithm to cover the wider search window of the present invention to have a VLSI structure for E4SS algorithm with excellent performance and easy to implement in VLSI The purpose.

In order to achieve the above object, the present invention uses a four step search algorithm (4SS) to reduce the number of clocks required for operation to be implemented as a real-time system, and adds one step to estimate motion and compensate for half-pixel units. It is possible to make a decision and use 4SS which is better than TSS and requires fewer clocks than FSS. Therefore, it is suitable for real-time system and it is about 27MHz when image data is input at 6.5MHz. We propose a search algorithm that can operate the system and estimate a larger motion vector so that it can be effectively applied to implement video encoders such as MPEG-1 and MPEG-2 in VLSI.

1 is a block diagram showing the configuration of a general video compression apparatus;

Figure 2 is a schematic diagram showing the processing of a typical 4SS

Figure 3 is a schematic diagram showing the process of half-pixel motion estimation by the general health law

4 is a schematic diagram showing a general linear approximation scheme

5 is a schematic diagram showing the coordinates of each PE in a typical 4SS

6 is a block diagram showing a configuration of a half-pixel motion estimation unit according to an embodiment of the present invention.

7 is a block diagram showing a configuration of a processor array according to an embodiment of the present invention.

8 is a block diagram showing a configuration of a processor element according to an embodiment of the present invention.

9 is a schematic diagram showing a PE for calculating half-pixel unit motion of the present invention.

10 is a schematic diagram showing determination of motion compensation of the present invention.

11 is a schematic diagram showing a discovery process of an E4SS according to another embodiment of the present invention;

12 is a schematic diagram showing a data input state according to another embodiment of the present invention;

13 is a schematic diagram showing sections of a search area and a motion area according to another embodiment of the present invention;

14 is a block diagram showing a configuration of a half-pixel motion estimation unit according to another embodiment of the present invention.

15 is a block diagram showing a configuration of a processor array according to another embodiment of the present invention.

16 is a block diagram showing a configuration of a processor element according to another embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 shows the overall configuration of an image compression device including a moving picture motion estimation device of the present invention;

An NTSC decoder 1 which outputs a signal corresponding to the combination with respect to the combination of the NTSC video signal input from the outside;

A delay buffer (2) for amplifying while delaying the video signal input from the NTSC decoder (1) for a predetermined time;

A discrete cosine transforming unit (3) for easily calculating a coefficient for transforming a video signal delayed for a predetermined time from the delay buffer (2) into a value of a cosine function and converting the coefficient to a frequency coordinate;

A quantization unit 4 for converting the waveform of a continuous curve into a stepped waveform for the video signal converted into the frequency coordinates transmitted from the discrete cosine transform unit 3 and converting the amplitude into an integer value at an appropriate level as a unit and outputting it; ;

Variable length code part 5 for outputting a compressed video signal while assigning a code having a length proportional to the absolute value of the frequency of appearance with respect to the integer value of the step waveform transmitted from the quantizer 4 to the value Wow;

An inverse quantization unit (6) for reducing and outputting an integer value in units of levels transmitted from the quantization unit (5) to a video signal having frequency coordinates;

An inverse discrete cosine transforming unit (7) for reducing the video signal of the frequency coordinate which is the value of the cosine function delivered from the inverse quantization unit (6) to the original video signal;

A motion estimation and compensator (8) for estimating a motion vector with respect to the video signal input from the NTSC decoder (1) and the video signal transmitted from the inverse discrete cosine transformer (7), and compensating for the motion vector; ;

A subtractor (9) which mixes the video signal delayed for a predetermined time from the delay buffer (2) with the signal from the motion estimation and compensation unit (8) and delivers it to the discrete cosine transformer (3);

The motion estimation and compensator 2 converts the 8-bit input data naturalized from the inverse discrete cosine transform unit 9 into a 16-bit bus structure by the register 11;

The 16-bit data input from the register 11 reads and writes in units of frames to the frame memories 14 and 15, which are two DRAMs, by switching operations of the two three-state buffers 12 and 13. To perform;

The even-numbered 8-bit data and the odd-numbered 8-bit data respectively stored in the two DRAM frame memories 14 and 15 are selected by one switch 16 and 17 to one 16-bit data bus. While dividing into 8 bit units;

Data divided by the switch 16 and stored in the two frame memories 14 and 15 are stored in two search windows 18 and 19 which are SRAMs in 8 bit units;

A pixel motion estimator 20 receiving a search window signal stored in the two frame memories 14 and 16 selected by the switch 17 estimates motion in units of pixels;

Half-Pel Motion Estimator 21, which receives pixel-based motion information output from the motion estimator 20, estimates motion in half-pixel units using the surrounding error values. ;

Half-Pel Motion Compensation 22, which receives half-pixel motion information from the half-pixel motion estimation unit 21, inputs data into the two search windows 18 and 19. To compensate for movement;

The buffer 23, which receives the motion-compensated signal from the motion compensator 22, converts the scanning by 8 * 8 blocks.

The operation state of the half-pixel motion estimation apparatus of the present invention configured as described above is described in detail as follows.

Since almost all images are continuous and moving slowly in a moving picture, grasping the check points uniformly in the search window in the first step by TSS method is inefficient in general image with little movement. .

However, the method of 4SS has relatively little movement because it starts the search at 9 points of -2 and 2 horizontally and vertically from the first center based on the statistical movement of about -2 ~ 2 pixels from the center. Applies relatively well to video.

The processing of 4SS is as shown in Fig. 2;

Initially, a first step of finding a point having a minimum Sum of Absolute Difference (SAD) value for nine searching points in a 5 * 5 window of a search area of 15 * 15 is performed.

A second step is performed to find the point with the minimum SAD value for nine checkpoints in a 5 * 5 window centered on the obtained point.

Next, a third step of repeating the process of finding a point having a minimum SAD value for nine check points in a 5 * 5 window is performed based on the obtained point.

If a fourth step of finding a point having a minimum SAD value for nine check points in a 3 * 3 window is performed based on the obtained point, the found point determines the direction of the motion vector.

In general, we can see that 4SS outperforms TSS and approaches FS.

Meanwhile, the full range search half-pixel motion vector determination method by interpolation method is a method of determining the motion vector by calculating SADs for the half-pixels that are possible as shown in FIG. 3, and the linear approximation method is possible as in the interpolation method. It is a method of approximating as shown in FIG. 3 using the previously calculated pixel unit SAD value without calculating the SAD for the position.

This approximation approach almost approaches the interpolation performance.

That is, E = a │x-b│ + c (a 0, │ b│ 1)

Where a is the slope and b is the minimum.

E (-1) = a (1 + b)

E (0) = a│b│

E (1) = a (1-b)

Assuming that both sides of the error curve are symmetric in the figure of FIG. 4, when the minimum error point is between -0.75 and-2.25

2 {E (-1) -E (0) (E (1) -E (0) ------- (Equation 1)

, If the minimum error point is between 0.75 and 0.25

(E (-1) -E (0) 2 {(E (1) -E (0)) ------- (Equation 2)

to be.

In the case of Equation 1, mv-0.5, and in the case of Equation 2, mv + 0.5 is used to obtain half-pixel motion information.

Therefore, in order to apply the existing 4SS algorithm and add the number of processing steps to estimate the motion of the half pixel unit, the MC and the no MC can be determined while the half pixel unit motion estimation is performed in the fifth step.

In 4SS, a SAD (Sum of Absolute Difference) calculation must be performed on 8 points having displacements of up, down, left, and right sides as reference points and reference points as shown in FIG. 5.

Since the areas to be calculated by each PE overlap most of each other, delaying the reference block, that is, DB data according to processing timing, can reduce the number of clocks required for the calculation.

Table 1 shows the state of W and DB data input to each PE in the first, second and third stages of 4SS, and Table 2 is input to each PE in the fourth and fifth stages. It shows the state of W and DB data.

As shown in Table 1 and Table 2, the DB data inputted to each PE is the first step, the second step, and between PE0, PE1, PE2, between PE3, PE4, PE5, PE6, PE7, PE8, and The third stage is inputted with a delay of two clocks, and the fourth stage and the fifth stage are inputted with a delay of one clock.

In addition, between the PE2 and the PE3 and between the PE5 and the PE6 are delayed by 28 clocks in the first, second and third stages, and delayed by 14 clocks in the fourth and fifth stages.

6 shows an internal configuration of a half-pixel motion estimation unit according to the present invention;

Outputs the address signal ADDR while generating and outputting a control signal SRW DRW for controlling the search window memory 32 to which the current frame is input and the memory 33 of the reference block to which the previous frame is input. An address controller 31;

It is composed of nine processor elements and receives upper and lower data (P, Q) and DB data (DB) from the search window memory 32 and the reference block memory 33 to perform calculation of SAD. A processor array 34;

PMVG (preliminary motion vector) for receiving and comparing SAD values from nine unit processors of the processor array 34 and outputting the portion having the minimum error value as an index for nine points to be processed in the next set. generator 35;

A half-pel motion vector generator (HMVG) that receives a SAD value from the processor array 34, calculates a motion vector, estimates motion in a half-pixel unit, and generates a motion compensation flag. 36;

Step type for determining the operation timing of all blocks, outputting an address control signal to the address controller 31, and determining the processor element enable signal PE-E and the step type to the processor array 34. Outputting a control signal (step type) and outputting the MVG control signal (MVG-Control) to the PMVG (35) while receiving the index (PMVH, PMVV) according to the minimum error value and the motion estimation of the HMVG MCD (36) It is composed of processor controllers (processor controllers 37) for outputting a control signal (HMVG-Control) to control the internal operation.

FIG. 7 illustrates the internal structure of the processor array 34 of the motion estimator. The search window memory 32 is arranged by arranging nine processor elements PE0 to PE8 34a to 34i in parallel to calculate the SAD. 8 bit upper and lower data (P, Q) and 1 bit step type control signal (step type) from the processor controller 37 in parallel, respectively, Inputs the processor element enable signals PE0-E to PE8-E and the processor element memory select signals PE0-MSEL to PE8-MSEL, which are generated and transmitted by the multiplexer select generator 38, respectively. On the other hand, by sequentially receiving delayed DB data (Delayed DB) while passing through the DB data DB and the processor elements (PE0 to PE7) 34a to 34h from the reference block memory 33, To calculate the SAD value To output it.

Therefore, the processor elements PE0 to PE8 34a to 34i arranged in parallel have 8 bits of upper data P and lower data Q input from the search window memory 32. In the state, when the processor element memory selection signals PE0-MSEL to PE8-MSEL generated and transmitted by the multiplexer selection generator 38 are 0, 8-bit upper data P is selected and the element memory selection signal PE0 is selected. If -MSEL) ~ (PE8-MSEL) is 1, the lower data Q is selected.

When the 1-bit step type control signal (step type) is input to 0 from the processor controller 37, the step type control signal (step type) becomes 1 while being delayed by the first step, the second step, and the third step. If it is input as is to be delayed by the fourth and fifth steps.

SAD values are calculated by performing 8-bit upper and lower data P and Q from the search window memory 32 and DB data DB from the reference block memory 33 and outputting a SAD value. .

FIG. 8 shows the configuration of each processor element, wherein the search window memory 32 is provided by the processor element memory selection signals PE0-MSEL to PE8-MSEL generated and transmitted by the multiplexer selection generator 38. A search window multiplexer 38 for selecting the upper data P and the lower data Q inputted from?

The next element array (PE1 to PE8) 34b is delayed by the 1-bit step type control signal from the processor controller 37 while receiving the DB data DB from the reference block memory 33. A delay block 39 for outputting to 34i;

A subtraction block 40 which receives the upper, lower data P, Q and the delayed DB data DB from the search window multiplexer 38 and the delay block 39 and compares each other by subtraction;

The upper, lower data (P), (Q) and the delayed DB data (DB) are inputted from the subtraction block 40 and 16 are calculated through the absolute value calculation and the cumulative calculation of the SAD operation according to the result of mutual comparison by subtraction. It is composed of arithmetic blocks 41 for obtaining and outputting the SAD value of the bit.

The delay block 39 is divided into two types, a-type delay method and b-type delay method, depending on the types of the processor elements PE0 to PE8 34a to 34i. Delay two clocks in the first, second, and third phases, and delay one clock in the fourth and fifth phases.

The b-type delay scheme delays 28 clocks in the first, second and third stages, and delays 14 clocks in the fourth and fifth stages.

The delayed DB data and the search window data output from the search window multiplexer 38 output 16-bit SAD values through subtraction, absolute values, and cumulative operations.

Table 3 and Table 4 show the output timing of the processor element enable signal (PE-E) that is the input of the processor element of the processor array 34, the processor element enable signal (PE-E) for each processor element Is 1, SAD is calculated, and 0 is not SAD.

In steps 1, 2, and 3, a delay is performed by one cycle between the processor elements PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, and PE8, and the processor elements PE2, There is a delay of 14 cycles between PE3) and (PE5, PE6) and the next operation.

Further, in steps 4 and 5, the processor element PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8 are delayed by two cycles, and then the processor elements PE2, PE3 are operated. , Between the (PE5, PE6) is delayed by 28 cycles and then the operation.

Data values input to each processor element (PE) are delayed by 1 cycle, 2 cycles, 14 cycles and 28 cycles in steps 1, 2, and 3 by A-delay and B-delay, respectively. The values will be entered.

Table 5 shows the timing for the SAD output from the processor element (PE) in step 5 for the half-pixel unit motion vector calculator.

In FIG. 9, five SAD values by the processor elements PE1, PE3, PE4, PE5, and PE7 are required to perform half-pixel unit motion estimation.

When the output of each of the processor elements PE1, PE3, PE4, PE5, and PE7 comes out according to the timing as shown in Table 5 above, the data is stored until the output SAD value appears and then the processor element ( When the output of PE1, PE3, PE4, PE5, PE7) comes out, the half-pixel motion vector is calculated by the half-pixel motion calculation equation as in Equation 1 and Equation 2 above.

After the half-pixel unit motion estimation is completed by the above process, the MC determines whether it is MC or no MC using the motion compensation decision curve of FIG. do.

In the 32 × 32 search area in the SIF format applied to MPEG-1, the search area is not very wide, and thus the motion vector can be sufficiently tracked by three or four steps.

However, if the search area reaches 48 × 48 or 64 × 64, many steps are required for the smallest step size to reach the maximum interval of the motion vector. Since it can generate a, it is difficult to select a search algorithm.

In other words, a method that reduces the number of steps and uses more search points in each step has a large amount of calculation.However, reducing the search point for each step and increasing the number of steps instead can reduce the calculation amount, Difficulties in finding a motion vector can follow.

Therefore, in the E4SS algorithm according to another embodiment of the present invention, a case where the 4SS algorithm does not adapt well to a large moving image may occur. As shown in the above, when the block-by-block comparison is performed for 36 points, the range where the motion vector can go in the first step is -4 and -6, so that a good performance can be obtained even for a large motion image.

That is, step 1 performs a MAD operation on points within a range of 2 points to the left, 3 to the right, 2 to the right, and 3 points to the bottom at intervals of 2 pixels based on the origin to obtain the minimum error point. .

In step 2, the search range is changed according to the position of the minimum error point obtained in step 1 above.

Therefore, if it is left from the reference point within the horizontal search range of step 1, the horizontal search range of step 2 finds the minimum error point by MAD operation for the points in the range of 3 to the left and 2 to the right at 2 pixel intervals. , If right, the horizontal search range of step 2 finds the minimum error point by MAD operation for points in the range of 2 to the left and 3 to the right in 2 pixel intervals.

On the other hand, if it is above the reference point within the vertical search range of step 1, the vertical search range of step 2 finds the minimum error point by MAD operation for the points within the range of 3 to the left and 2 to the right at 2 pixel intervals. If downward, the vertical search range of step 2 finds the minimum error point by MAD operation for points in the range of 2 to the left and 3 to the right in 2 pixel intervals.

Step 3 calculates the minimum error point by MAD operation on the points within the range of 2 points to the left, 3 to the right, 2 to the top, and 3 points to the bottom with the minimum error point obtained in step 2 above. Obtain

Step 4 finds the minimum error point by MAD operation for the search section corresponding to one point each of left, right, top, and bottom at intervals of one pixel with respect to the minimum error point obtained in step 3.

The range between the minimum error point found here and the reference point in step 1 becomes a motion vector.

Since the E4SS algorithm is superior to the 4SS algorithm described above, it is suitable for the VLSI structure by expanding and modifying the structure of the aforementioned VSLI.

Since the E422 algorithm performs many operations by increasing the number of search points in each step, data is input and operated by 32 bits.

12 to 16 illustrate a VLSI structure by the E4SS algorithm according to another embodiment of the present invention, and descriptions of the same parts as the VISL structure of the aforementioned 4SS algorithm will be omitted.

12 illustrates an input order of data, in which four pixel values are input at the same time to perform MAD operations corresponding to four pixels.

That is, since all inputs and operations are performed by 32 bits and data input and processing are performed by 32 bits, the number of clocks required for processing is also reduced.

When data input to each processor element PE is input simultaneously in 32 bits of 4 pixels, data SW and DB data DB are received as shown in Tables 6, 7, and 8.

It can be seen that the DB data db1, db2, db3, and db4 input to each processor element PE are delayed by one clock and 14 clocks as in the case of steps 4 and 5 of 4SS.

FIG. 13 illustrates a search window having a size of 48 × 48. Since a motion vector has a range of −16 to 16 and the search window is composed of six macro blocks, the search window has a size of 48 × 48. It divided into middle, lower R, P, and Q.

14 to 16 show the configuration of a half-pixel motion estimator capable of performing 32-bit processing on a 48 × 48 search window. The basic configuration is almost the same as that of the VLSI structure for the 4SS algorithm. The input of DB, which is, P, Q data and DB data is 36 bits.

For 32-bit data, sw1, sw2, sw3, and sw4 data are simultaneously input to search window data, and data of db1, db2, db3, and db4 are simultaneously input to DB data.

The internal structure of the processor array is shown in FIG. 15. The structure of the processor array is also similar to that of 4SS except that two SW data of P and Q are input as 8 bits in 4SS as the input of SW. There are three, P, and Q, and two select inputs to the search window multiplexer (SWMUX) within the processor element.

FIG. 16 shows the configuration of the processor elements constituting the processor array. Since the input and the operation are performed at the same time by 4 pixels, the delay units 42, 43, 44, 45 and the search window multiplexer 46 are accordingly shown. (47) (48) (49) are formed in parallel by 4 and subtraction and absolute value calculation is required for subtraction and absolute value calculation respectively for 4 pixels. ) 53 are formed in parallel and their outputs are in the case of adders 54, 55, 56.

However, since four pixels are always performed in the same block, only one operation block 57 is formed.

According to the motion estimation apparatus and method of the half-pixel unit for the video encoder of the present invention, the number of clocks used for the operation is reduced so that it can be implemented as a real-time system using 4SS. Motion estimation and motion compensation determination can be made, and it is suitable to be applied in real-time system by using 4SS, which has better performance than TSS and requires fewer clocks than FSS, and inputs image data at 6.5MHz. In this case, we can operate the system at about 27MHz and propose a search algorithm that can estimate a larger motion vector, which is excellent in terms of performance and can be efficiently applied to implement video encoders such as MPEG-1 and MPEG-2 in VLSI. It would be.

Claims (7)

An address controller 31 for outputting an address signal while outputting a control signal for controlling the search window memory 32 into which the current frame is input and the reference block memory 33 into which the previous frame is input; A processor array 34 including nine unit processors, which receives upper and lower data P and Q and DB data from the search window memory 32 and the reference block memory 33 and performs calculation of SAD. Wow, PMVG 35 which receives the values of SAD from the processor array 34 and compares them and outputs the portion having the minimum error value as an index to be progressed in the next set; An HMVG MCD 36 which receives the value of SAD from the processor array 34 and calculates a motion vector to generate a motion estimation and compensation flag in units of half pixels; The address controller 31 outputs an address control signal, and the processor array 34 outputs a processor element enable signal and a step time bear signal for determining a step time, and outputs an MVG control signal to the PMVG 35. While receiving an index according to a minimum error value and outputting a control signal for motion estimation to the HMVG MCD 36, the motion estimation apparatus for a half-pixel unit for a video encoder comprising processor controllers 37 for controlling internal operations . 2. The processor array 34 according to claim 1, wherein the processor array 34 arranges nine processor elements (PE0 to PE8) 34a to 34i in parallel to calculate an SAD. 1-bit processor element enable signal PE0 from the processor controller 37 while receiving the 1-bit step type control signal (step type) in parallel from the lower data (P, Q) and the processor controller 37, respectively. -E) to (PE8-E) and the processor element memory selection signals (PE0-MSEL) to (PE8-MSEL), which are generated and transmitted by the multiplexer selection generator 38, are respectively input, while the above reference block memory A video encoder which outputs the SAD value by receiving the delayed DB data sequentially while passing through the DB data DB and the processor elements PE0 to PE7 34a to 34h from (33). Movement of half pixel unit for Im estimation device. 2. The processor element of claim 1, wherein the processor element is input from the search window memory 32 by processor element memory selection signals PE0-MSEL to PE8-MSEL which are made and transmitted by the multiplexer selection generator 38. A search window multiplexer 38 for selecting the upper data P and the lower data Q; Receiving the DB data DB from the reference block memory 33, the processor controller 37 performs a 1-bit step type control signal (step type) and then the following element arrays PE1 to PE8 34b. A delay block 39 to be outputted to ˜34i, A subtraction block 40 which receives upper, lower data P, Q and delayed DB data DB from the search window multiplexer 38 and the delay block 38 and compares each other by subtraction; The upper, lower data (P), (Q) and the delayed DB data (DB) are inputted from the subtraction block 40 and 16 are calculated through the absolute value calculation and the cumulative calculation of the SAD operation according to the result of mutual comparison by subtraction. An apparatus for estimating a half pixel unit for a moving picture encoder comprising arithmetic block 41 for calculating and outputting a bit SAD value. 2. The processor element of claim 1, wherein the processor element comprises delay units 42, 43, 44, 45 and search window multiplexers 46, 47, 48, 49 so that input and operation are performed simultaneously by 4 pixels. Four in parallel, Subtraction and absolute value calculation must be performed separately for 4 pixels, so four subtraction units 50, 51, 52, and 53 are formed in parallel for the subtraction operation and the absolute value operation. (54) (55) (56) A half-pixel motion estimation apparatus for a video encoder which outputs the SAD value via the calculation block (57) in order. Half-pixel motion estimation 2 {E (-1) -E (0) (E (1) -E (0) Of Equation 1, (E (-1) -E (0) 2 {(E (1) -E (0)} A half-pixel motion estimation method for moving picture encoder using linear approximation using Equation 2. The delay block is divided into two types, an a-type delay block and a b-type delay block. The a-type delay block delays two clocks in steps 1, 2, and 3, and 1 in steps 4 and 5. And a b-type delay block delays 28 clocks in steps 1, 2, and 3, and delays 14 clocks in steps 4 and 5, respectively. 7. The method of claim 6, wherein in steps 1 and 2, 36 points are searched instead of 9 points of existing two pixel intervals, in step 3, 9 points of two pixel intervals are searched, and in step 4, 9 points of one pixel intervals are searched. A half-pixel motion estimation method for a video encoder which is searched for.