KR19980068373A - Clock and timing recovery device of digital packet data - Google Patents

Abstract

The present invention relates to a clock and timing recovery apparatus for digital packet data of a remodulator of a headend system. The shift register unit outputs input data of each data having a clock delay, and the shift register unit according to a selection signal. A selector which selects and outputs one of the data output from the PDU, a PLL loop which detects and filters the phase of the data output from the selector, divides and outputs a reference clock according to the data mode, and detects a preamble A shift data selection unit for comparing a reference clock output from the PLL loop with input data and outputting a selection signal for the shift amount of input data to the selection unit, and using the clock output from the PLL loop; It is composed of a timing recovery unit for recovering the timing by delaying the data output from There is an effect that locate the clock information of the data having the jitter received at the meter can send the correct data to the object terminal by clock recovery.

Description

Clock and timing recovery device of digital packet data

TECHNICAL FIELD The present invention relates to a headend of a cable modem system, and more particularly, to clock and timing recovery of digital packet data in a remodulator.

A general retransmission apparatus will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a retransmission apparatus in a headend of a typical cable modem, and includes a first mixer unit for outputting an intermediate frequency IF to an upstream radio frequency input and a local oscillation frequency input. 11), a PSK demodulator 12 for performing phase shift keying (PSK) demodulation on the intermediate frequency output from the first mixer 11, and a clock recovery and data of the data output from the PSK demodulator 12; A clock and timing recovery unit 13 for restoring the timing of the clock, and an Ethernet network 14 for outputting Ethernet data for communicating the data recovered by the clock and timing recovery unit 13 with another network. The PSK modulator 15 outputs an intermediate frequency by PSK modulating the data recovered by the clock and timing recovery unit 13, and the intermediate frequency and the local oscillation frequency output from the PSK modulator 15 are synthesized. Frequency The second consists of a mixing unit 16 for output.

The operation of the general retransmission apparatus configured as described above will usually be described with reference to the accompanying drawings for explaining the format of the general digital packet data in FIG. 2 and the waveform diagram for explaining the timing of the general digital packet data in FIG. Is one of the devices used in the headend of the cable modem system, and the first mixer 11 outputs the upstream radio frequency input and the local oscillation frequency to the PSK demodulator 12 to make the intermediate frequency. .

The PSK demodulator 12 outputs a baseband signal by performing PSK demodulation. At this time, jitter noise due to channel noise is generated in the data.

This noisy data is subjected to clock recovery and data timing recovery in the clock and timing recovery section 13 to reduce jitter noise and reduce transmission errors.

The clock and timing recovery unit 13 PSK modulates the data whose clock and timing have been restored by the PSK modulator 15 again, and outputs a radio frequency of the downstream through the second mixer 16 to output a frequency for another user. Switch to the channel.

In addition, the clock and timing recovery data of the clock and timing recovery unit 13 is for communicating with the Ethernet router and the switch in the Ethernet interface 14 and through this, the external network (T1). , DDS, ATM).

Here, the packet data of the stream demodulated by the PSK demodulator 12 is a preamble of 3 bytes in 500 ms data mode, 15 bytes in 4 MHz data mode, followed by a 1 byte start flag, It consists of a six-byte destination address, a six-byte source address, a two-byte length type, 46 to 1500 bytes of data, a four-byte cyclic redundancy check code (CRC), and a one-byte stop flag.

When there is packet data thus configured in the received radio frequency, an active low lock is detected as shown in FIG. 3 (a), and after a certain period of time after the detection of the lock, the packet data is 500 ms data mode. As shown in FIG. 3, a preamble of 3 bytes is placed in front, and subsequent data is placed in random data in the form of No Return to Zero Invert (NRZI).

In addition, in the case of the 4 MHz data mode, the packet data is located in front of the 15-byte preamble as shown in FIG. 3 (c), and the subsequent data is located in the form of NRZI.

Let's look at the clock and timing recovery apparatus according to the prior art, which is mounted in the general retransmission device configured as described above in more detail.

4 is a block diagram illustrating the clock and timing recovery unit of FIG. 1 according to the related art in detail. FIG. 5 is a waveform diagram illustrating the timing of the phase shifter unit of FIG. 4. The control phase shifter 131, the phase detector 132, the loop filter 133, the voltage controlled crystal oscillator (VCXO) 134, and the data recovery unit 135 are provided.

The phase detector 132 of the clock and timing recovery apparatus according to the related art configured as described above detects the phase of packet data of the stream demodulated by the PSK demodulator 12, and the loop filter 133 according to the detected phase is The DC voltage is output to the VCXO 134 by filtering.

Here, the phase detector 132, the loop filter 133, and the VCXO 134 are phase locked loops (PLLs), and data input to the voltage controlled phase shifter 131 and the VCXO 134 output before the PLL locks. The clock phase relationship is random.

Therefore, the voltage control phase shifter 131 checks the level of the DC voltage at which the packet data of the stream demodulated by the PSK demodulator 12 is output from the loop filter 133, thereby rising the rising edge of the VCXO 134 clock. Shift the phase of the input data to center it.

The data recovery unit 135 outputs the input data shifted by the voltage controlled phase shifter 131 according to the clock recovered by the VCXO 134, thereby removing jitter of the input data.

That is, as shown in FIG. 5, since the rising edge of the VCXO 134 clock is near the edge of the input data at time t1, the data recovery unit 135 outputs an errored data.

The voltage controlled phase shifter unit 131 detects a DC voltage level corresponding to an error output from the loop filter 133 so that the rising edge of the VCXO 134 clock is positioned at the center of the input data at the times t2 and t3. Shift to perform timing recovery.

The clock and timing recovery apparatus of the digital packet data according to the prior art receives a data having a lot of jitter in the repeater during data communication through a cable, and when the data is sent back to the destination terminal, a problem of receiving incorrect information due to jitter occurs. .

Clock recovery is performed to receive the correct information. The voltage control shifter used for clock recovery takes a lot of time since it detects the DC voltage level output from the loop filter and shifts the input data.

Therefore, there is a problem in that an error occurs when outputting dozens of bits of the first part of the packet data, that is, preamble data, during the time until the voltage control shifter unit operates properly.

Disclosure of Invention The present invention has been made to solve the above-mentioned problems of the prior art, and provides a clock and timing recovery apparatus for digital packet data in which an error does not occur in the preamble data of the packet data.

1 is a block diagram illustrating a retransmission apparatus in a headend of a typical cable modem.

2 is a diagram for explaining a format of general digital packet data.

3 is a waveform diagram for explaining the timing of general digital packet data;

4 is a block diagram illustrating in detail the clock and timing recovery unit of FIG. 1 according to the related art.

5 is a waveform diagram illustrating the timing of the phase shifter in FIG. 4.

6 is a block diagram illustrating a configuration of a clock and timing recovery apparatus according to the present invention.

* Description of the symbols for the main parts of the drawings *

61: shifter resist portion 62, 654: selection portion

63, 68: 1/2 bit delay 64, 69: XOR

65: PLL loop 66: PLL clock edge detector

67: preamble detector 70: data edge detector

71: shift amount determination unit 72: coder

73: delay portion 74: latch portion

651: VCXO652, 653, 655: divider

656: phase detection unit 657: loop filter

A characteristic of the clock and timing recovery apparatus for digital packet data according to the present invention is that the shift register unit outputs data having a clock delay according to a reference clock, an edge detected by the PLL clock edge detector, and an edge generated by the data edge detector. And using the edge output from the data edge detector, compare the signal output from the data edge detector with the signal output from the PLL clock edge detector according to the detection of the preamble to determine the amount of shift of the input data as the selection signal of the selector. The output unit selects one of delayed data output from the shift register unit according to the selection signal.

Hereinafter, a clock and timing recovery apparatus for digital packet data according to the present invention will be described with reference to the accompanying drawings.

FIG. 6 is a block diagram illustrating a configuration of a clock and timing recovery apparatus according to the present invention. The shift register unit outputs data having 0 to 15 clock delays according to a reference clock of 64 MHz or 8 MHz. 61, a first selector 62 for selecting and outputting one of the data output from the shift register section 61 in accordance with the input of the selection signal, and a first clock according to a reference clock of 64 MHz or 8 MHz. A first half bit delay unit 63 outputting the data output from the selecting unit 62 after a half bit delay, the data output from the first half bit delay unit 63 and the first data; The first XOR (Exclusive OR) 64 performing the exclusive OR operation on the data output from the selecting unit 62 and the phase output from the first XOR 64 are detected and filtered, and the data of 4 or 0.5 MHz is detected. PLL loops that divide the reference clock to generate signals with -90 ° and 0 ° phases depending on the mode The PLL clock edge detector 66 for generating an edge when the reference clock having a phase of 0 ° output from the PLL loop 65 and the PLL loop 65 is generated, and the input data and the lock detection signal are inputted. A preamble detection unit 67 for detecting the preamble, a second half bit delay unit 68 for delaying and outputting the input data by a half bit according to a 64 MHz or 8 MHz reference clock, and A second XOR (69) for performing an exclusive OR operation on the data output from the 2 1/2 bit delay unit 68 and the input data, and an edge when data output from the second XOR 69 is generated. When the preamble detection signal is input from the data edge detector 70 and the preamble detector 67, the signal output from the data edge detector 70 is compared with the signal output from the PLL clock edge detector 66. In the shift amount determining unit 71 that determines the shift amount of the input data, and the shift amount determining unit 71 The coder 72 outputs a selection signal of the first selector 62 with respect to the shift amount, and input data whose delay is fixed by the predetermined clock selected by the first selector 62 using a reference clock of 64 or 8 MHz. A delay 73 for shifting and adjusting the clock to be in the center of the data, and a latch for outputting a clock having a -90 ° phase output from the PLL loop 65 to the center of data output from the delay 73 It is composed of a portion 74.

Here, the PLL loop 65 may include a voltage controlled crystal oscillator (VCXO) 651 for outputting a clock according to an input, a first divider 652 for dividing a clock output from the VCXO 651, and two outputs thereof. In the 16th divider 653 for dividing the clock output from the VCXO 651 by 16 divisions, and in the first 2nd divider 652 or the 16th divider 653 according to the data mode for 4 MHz or 0.5 MHz, The second selector 654 for selectively outputting the output clock and the clock output from the second selector 654 are divided by two to set the clocks for the data mode of 4 MHz or 0.5 MHz to -90 ° and 0 °. Phase error information is output using a second divider 655 outputting an excitation signal, a clock output from the first XOR 69 and a clock having 0 ° output from the second divider 655. A phase detector 656 for detecting and a loop filter 657 for filtering the signal output from the phase detector 656 and outputting the filtered signal to the VCXO 651.

Let's look at the operation of the clock and timing recovery apparatus according to the present invention configured as described above.

First, the data received from each terminal is input to the shifter register section 61 having a resolution 16 times faster than the data rate, and has data having a delay of 0 to 15 clocks from the first selector 62. Are respectively output, and the first selector 62 selects and outputs one piece of data according to a selection signal for the shift amount output from the coder 72 among the input delay data.

Data output from the first selector 62 is input to the first 1 / 2-bit delay unit 63 to extract a clock frequency, and is output after a 1 / 2-bit delay, and the first XOR 69 is the first. The data output from the 1 / 2-bit delay unit 63 and the original input data output from the first selector 62 are subjected to an exclusive OR and output to the PLL loop 65.

The phase detector 656 of the PLL loop 65 detects phase error information of data output from the first XOR 69 using a clock signal having a 0 ° phase output from the second divider 655. The filter is filtered by the loop filter 657 and input to the VCXO 651.

The VCXO 651 generates a clock according to the voltage output from the loop filter 657 and outputs the clock to the first divider 652 and the 16 divider 653, and receives the received first divider 652. And the 16 divider 653 are divided into 2 and 16 divisions, respectively, and are output to the second selector 654.

The second selector 654 outputs the second divider 655 when the clock output from the second divider 652 or the 16 divider 653 is selected according to the data mode of 4 MHz or 0.5 MHz. do. In addition, the second divider 655 divides the input clock into two again to generate a clock having a phase of −90 ° and 0 °.

The clock with the -90 ° phase is used as the clock for outputting the final data from the latch unit 74, and the clock with the 0 ° phase is fed back and used for the phase detection of the PLL in the PLL clock edge detector 66. .

Here, in order to detect the data edge, the second 1 / 2-bit delay unit 68 outputs the input data after delaying 1/2 bit, and the second XOR 69 outputs the second 1 / 2-bit delay unit 68. Exclusive OR is performed on the data outputted from the data) and the original input data, and is output to the data edge detector 70.

The data edge detector 70 detects a data edge having a 64 MHz clock and outputs it to the shift amount determiner 71. The preamble detector 67 detects the preamble using the lock detection signal.

When the preamble detection signal is inputted to the shift amount determination unit 71, the shift amount determination unit 71 counts the preamble signal detected by the preamble detection unit 67 to find a point where data starts.

In addition, the PLL clock edge detector 66 detects an edge of the PLL clock and outputs it to the shift amount determiner 71 using a signal having a 0 ° phase divided by the second divider 655.

Then, the shift amount determiner 71 calculates the positions of the data edge signal input from the data edge detector 70 and the edge signal of the PLL clock input from the PLL clock edge detector 66 to shift the clock of the currently input data. Determine the amount.

That is, the clock amount determined by the shift amount determining unit 71 is an absolute value indicating how far the clock is from the center of the data.

The coder 72 converts the value determined by the shift determiner 71 into a selection signal for a substantial shift amount in consideration of the amount delayed by the shift resister 61 and outputs the selected signal to the first selector 620.

Therefore, one of the data output from the shift register section 61 is selected and input to the PLL loop 65 by the shift amount applied to the first selector 620, and the PLL loop 65 responds to this phase shifting. This narrows the locking range and significantly reduces the locking time.

That is, the data selected by the first selector 61 by the data edge and the PLL clock edge detection are input to the delay unit 73 for the final fine adjustment so that the clock is positioned at the center of the data.

This adjusted signal uses a clock having a -90 ° phase output from the second divider 655 of the PLL loop 65 at the latch portion 74 to avoid jitter at both edges and to provide the signal near the center of the data. To print.

The clock and timing recovery apparatus for digital packet data according to the present invention has the effect of sending accurate data to a target terminal by reclocking the clock information of the data having jitter received at the repeater.

In addition, the clock and timing recovery apparatus for digital packet data according to the present invention can be applied to any line for data communication, and has a great effect even in an area with poor line environment.

Claims (2)

A shift register section for outputting input data to each data having a clock delay; A selection unit for selecting and outputting one of data output from the shift register unit according to a selection signal; A PLL loop that detects and filters a phase of data output from the selector, divides and outputs a reference clock according to a data mode; A shift data selector for comparing a reference clock output from the PLL loop with input data according to the detection of a preamble and outputting a selection signal for the shift amount of input data to the selector; And a timing recovery unit for recovering timing by delaying the data output from the selection unit by using the clock output from the PLL loop. The method of claim 1, The shift data selector A PLL clock edge detector configured to generate an edge using a reference clock output from the PLL loop, A data edge detector for generating an edge when input data is generated; A preamble detection unit for inputting the input data and the lock detection signal to detect the preamble; And a shift amount determiner for comparing the signal output from the data edge detector and the signal output from the PLL clock edge detector according to the detection of the preamble to determine a shift amount of input data and output the selected shift signal as a selection signal of the selector. A clock and timing recovery apparatus for digital packet data.