KR19980068125A - IC card circuit and its test method - Google Patents

Abstract

The present invention relates to an IC card circuit and a test method thereof for loading a predetermined test program into an internal data memory area to test an IC card when testing an abnormality of a finished product during the production of an IC card. The CPU includes a CPU, a high speed serial input / output unit, a program memory, a data memory, an instruction input unit, and a flag. During the IC card test, the internal data memory is set to a program and a data memory area, and a predetermined test program is loaded into the area from the outside to perform a corresponding test. The instruction output from the data memory is passed to the instruction patch by the instruction input unit and output. When the IC card is normal, the flag is set to the normal mode, and accordingly, when the power is input, a corresponding IC card control program is executed with the data memory as the data area.

Description

IC card circuit and its test method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit card. Specifically, an IC for testing an IC card by loading a predetermined test program into an internal data memory area when testing for an abnormality of a finished product during production of an IC card. It relates to a card circuit and a test method thereof.

An IC card is a thin portable card made of an integrated circuit, and is mainly used for storing information. This is emerging as a new technology according to the trend of miniaturization of computers and miniaturization of recording media. The use of such an IC card can be used as an identification card, for example, to record personal information of a person, which is similar to a conventional magnetic card, but has a much larger data capacity. Therefore, IC cards have been replacing the existing magnetic cards, and the information is easy to store, the storage capacity is high, and the security is excellent, so the application range is wide.

1 is a circuit diagram of a conventional IC card circuit.

As shown in FIG. 1, a conventional IC card circuit is largely composed of a central processing unit (CPU) 100, a serial input output (SIO) 200, and a read only memory (ROM). And a data memory 400 including a program memory 300, a random access memory (RAM) 420, an electrically erasable and programmable ROM (EEPROM) 440, and the like. Typically these circuits are integrated into one chip and provided as a single chip.

The program memory 300 stores a predetermined program for controlling the IC card so that the program is executed by the CPU 100. The data generated by the execution of the program is temporarily stored in the data memory 400, and may store data input through the serial input / output unit 200.

The serial input / output unit 200 converts serial data input through an external pin into parallel data and provides the internal data, and conversely, converts parallel data input through an internal bus into serial data. Output to an external pin.

The external pin is generally composed of 8 pins according to the standard of ISO-7816, which is a standard of ISO (International Standardization Organization). Currently, 5 of these 8 pins are used, which are used as power terminals, data (serial) input terminals, and clock terminals.

On the other hand, the IC card as described above goes through a step of testing for the presence of the product during product production. Once the integrated IC card chip is mounted, data must be input and output and tested using the 5-pin provided to test the finished IC card. This process is very complicated and the test time is very time-consuming. . Therefore, it has a problem of causing negative effects such as an increase in unit price of IC cards by acting as a main cause of the decrease in product production rate.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to provide an IC card circuit and a test method thereof capable of efficiently testing the presence or absence of an IC card in a short time.

1 is a circuit diagram of a conventional IC card circuit,

2 to 7 are views for explaining the IC card circuit and its test method according to a preferred embodiment of the present invention,

2 is a circuit diagram of an IC card circuit,

3 is a detailed circuit diagram of a series input / output unit shown in FIG. 2;

4 is a detailed circuit diagram of an instruction input unit shown in FIG. 2;

5A and 5B are views illustrating a configuration of a memory area according to a normal mode and a test mode;

6 is a view showing a flag for indicating whether or not a test of the IC card;

7 is a flowchart of a test method for an IC card.

* Description of the symbols for the main parts of the drawings *

100: CPU200, 500: serial I / O unit

300: program memory 400: data memory

420: RAM440: EEPROM

520: serial / parallel conversion unit 540: multiplexer

560, 620: Register 580: Data input section

582: buffer 584: logic circuit

600: instruction input unit 640: switching unit

According to one aspect of the present invention for achieving the above object, an IC card circuit includes: an IC card controller for performing overall control of the IC card circuit; A serial I / O unit which performs an interface for data input / output between a predetermined external pin and an inside, and performs an input / output interface faster than a normal mode in which a normal operation is performed in a test mode in which an IC card is tested; A program memory in which a predetermined IC control program is stored; A data memory set in a data memory area in the normal mode to store corresponding data, and set in a program and data area in the test mode to load a predetermined test program from the outside; An instruction input unit configured to receive predetermined control signals in a test mode, and in response thereto, to output data from the data memory into an instruction; And a flag for indicating whether or not the IC card is to be tested.

In this embodiment, the serial input / output unit converts serial data input from the external pin into parallel data in the normal mode and provides the same internally, and converts the parallel data input from the internal data into serial data and outputs the serial data. Wealth; A register which receives serial data from the inside in a test mode and outputs in response to an input of a predetermined output control signal; A multiplexer configured to receive an output of the serial / parallel converter or an output of the register in response to an input of a predetermined selection signal, and output a selected one of the outputs to the external pin; And a data input unit configured to internally provide data input from the external pin in response to input of the selection signal and a predetermined input control signal.

In this embodiment, the register is comprised of D flip-flops.

In this embodiment, the program memory is composed of a nonvolatile memory.

In this embodiment, the data memory consists of a volatile memory and a rewritable nonvolatile memory.

In this embodiment, the data input unit and a buffer for outputting the data input from the external pin therein; And a logic circuit unit configured to receive the selection signal and the input control signal and provide a corresponding signal to the buffer through a predetermined logic operation to enable / disable the buffer.

In this embodiment, the logic circuit portion is composed of an AND gate.

In this embodiment, the instruction input unit comprises: a switching unit configured to patch data output from the data memory into an instruction in a test mode; And a register configured to receive a predetermined switching control signal and output the switching control signal to the switching unit in response to the input of the predetermined control signal.

In this embodiment, the register is comprised of D flip-flops.

In this embodiment, the flag is set in a predetermined area of the rewritable nonvolatile memory provided in the data memory.

According to another aspect of the present invention, a test method of an IC card circuit including an IC card control unit, a serial input / output unit, a program memory, a data memory, an instruction input unit, and a flag for determining whether or not to perform a test is: (a) Judging whether the flag is in a test mode when power is input to the IC card; (b) in the normal mode, executing a predetermined IC card control program using the data memory as a data memory area; (c) in the test mode, setting the data memory as a program and a data memory area to load a predetermined test program from the outside; (d) performing a predetermined IC card test by executing the loaded test program.

In this embodiment, the step (d) includes setting the flag to the normal mode when the test of the IC card is normally completed.

According to the present invention as described above, during the IC card test, the internal data memory is set to a program and a data memory area, and a predetermined test program is loaded into the area from the outside to perform a corresponding test. If the IC card is normal, the corresponding flag is set to the normal mode, and when the power is input thereafter, the corresponding IC card control program is executed with the data memory as the data area.

(Example)

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 to 7 are views for explaining an IC card circuit and a test method thereof according to a preferred embodiment of the present invention. In FIG. 2, components having the same functions as those shown in FIG. 1 denote the same reference numerals, and a description thereof will be omitted.

2 shows a circuit diagram of an IC card circuit according to an embodiment of the present invention. The IC card circuit is largely divided into a CPU 100, a serial input / output unit 500, a program memory 300, and a data memory ( 400 and an instruction input unit 600.

The serial input / output unit 500 implements a high speed serial interface to perform a quick test with five limited external pins after the IC card is completed. A serial I / O unit 500 implementing this is shown in FIG. 3.

3 is a detailed circuit diagram of the serial I / O unit 500 shown in FIG. 2.

As shown in FIG. 3, the serial input / output unit 500 according to an embodiment of the present invention includes a serial-parallel converter 520, a multiplexer 540, a register 560, and a data input unit 580. It is configured to include.

The serial-to-parallel converter 520 receives serial data from an external pin and converts the serial data into parallel data and provides the internal data. When outputting to the external pin, the multiplexer 540 converts parallel data input from the internal data into serial data. Output through This is the data input / output operation through external pins when the IC card is in the normal mode to perform normal operation.

The register 560 may be configured as a D flip-flop as a 1-bit register, and receives serial data from within and responds to input of a predetermined clock signal S1. Is provided to the multiplexer 540 to output serial data. This is a data output operation via external pins in the test mode for testing the IC card.

The multiplexer 540 outputs a corresponding input of the input of the serial-to-parallel converter 520 or the input of the register 560 to the external pin in response to an input of a predetermined selection signal S3.

The data input unit 580 may include a buffer 582 and a logic circuit 584, and the logic circuit 584 may include an AND gate. The buffer 582 provides internally the serial data input from the external pin. The logic circuit 584 receives the selection signal S3 and a predetermined input control signal S2 and provides a corresponding logic operation result to the buffer 582 so that the buffer 582 is enabled or enabled. Make it disable.

In the test mode for testing an IC card, the selection signal S3 is input to the multiplexer 540 and the logic circuit 584 at a high level. Therefore, the multiplexer 540 can output the input of the register 560 to the external pin.

At this time, when the input control signal S2 is input to the logic circuit 584 at a high level, the output of the logic circuit 584 is at a high level, and the buffer 582 is enabled. Therefore, when there is an input of serial data from the external pin, it is provided internally through the buffer 582. Serial data provided internally is converted into parallel data and processed by predetermined software for converting it into parallel data.

Meanwhile, a detailed circuit diagram of the instruction input unit 600 is shown in FIG. 4.

As shown in FIG. 4, the instruction input unit 600 according to the embodiment of the present invention includes a register 620 and a switching unit 640. The register 620 may be configured as a D flip-flop as a 1-bit register.

The register 620 receives a predetermined switching control signal S4 and outputs a signal for controlling the switching unit 640 in response to an input of a predetermined clock signal S5. The switching unit 640 is a path that is fetched to an instruction when an instruction occurs according to an execution of a test program loaded in the data memory 400 in response to the output of the register 620. Connect it.

Specifically, referring to FIG. 5A, the data memory 400 is set and used as a data memory area for storing data in the normal mode. However, with reference to FIG. 5B, in the test mode, since the data memory 400 is set as a program and a data memory area, a predetermined program for a test is loaded into the data memory 400. Therefore, the predetermined test of the IC card is performed in accordance with the execution of the loaded test program.

As shown in FIG. 6, the normal mode and the test mode are set by placing a flag 442 in a predetermined region of the EEPROM 440 included in the data memory 400, and whether or not a test is performed on the flag 442. Is displayed. Therefore, when power is input to the IC card, the flag 442 is determined at the initial stage of operation to operate in the test mode or the normal mode. In addition, since the data memory 400 is always fixed to the data memory area after the test of the IC card is completed, it is possible to prevent the data memory 400 from being switched to the program memory area to intentionally correct the information. Security is improved.

Next, a test method of the IC card will be described in detail with reference to FIG. 7.

7 is a flowchart of a test method for an IC card.

Referring to FIG. 7, when power is input to the IC card in step S100, it is determined whether the test mode is in step S110. That is, as described above, it is determined whether the IC card has performed the test by determining the setting state of the flag 442.

If the test is performed and is in the normal mode, the process proceeds to step S120 to set a data memory area, and the process proceeds to step S130 to execute a user program for a corresponding operation of the IC card. That is, the corresponding user program for performing the unique function of the IC card is performed. This means that the user program stored in the ROM constituting the program memory 300 is executed as described above.

On the other hand, in the test mode, the flow advances to step S140 to set the data memory area to a program and a data memory area. That is, the data memory 400 is set as a program and data memory area. In step S150, a predetermined test program is loaded from the outside. That is, the test program is loaded into the data memory 400.

In operation S160, a predetermined IC card test is performed by executing the loaded test program. When the IC card has been successfully tested, the flag 442 is set to the normal mode, and the process proceeds to step S170, where it ends. That is, when the test of the IC card is normally performed, the flag 442 is set to the normal mode. When power is input to the IC card, the steps S120 and S130 are performed.

As described above, since the predetermined test program for testing the IC card is loaded into the memory of the IC card, and the test is performed by the execution of the loaded test program, the test of the IC card is performed in a shorter time than before.

According to the present invention as described above, it is not necessary to perform a complicated and time-consuming test using a limited external pin as in the prior art, and by performing a test internally by loading a predetermined program for testing in the memory of the IC card. The test is completed in a short time. Therefore, the test module for testing the IC card is not required as in the prior art, and the production rate of the IC card is increased, thereby reducing the cost.

Claims (12)

An IC card controller 100 which performs overall control of the IC card circuit; A serial I / O unit 500 which performs an interface for data input / output between a predetermined external pin and an internal device, and performs an input / output interface faster than a normal mode in which a normal operation is performed in a test mode in which an IC card is tested; A program memory 300 in which a predetermined IC control program is stored; A data memory 400 set as a data memory area in the normal mode to store corresponding data, and set to a program and data area in the test mode to load a predetermined test program from the outside; An instruction input unit (600) for receiving predetermined control signals (S4, S5) in a test mode and causing the data output from the data memory (400) to be patched into an instruction in response thereto; And a flag (422) for indicating whether or not the IC card is to be tested. The method of claim 1, The serial input / output unit 500 converts the serial data input from the external pin into parallel data in the normal mode and provides the same to the internal data, and converts the parallel data input from the internal data into serial data and outputs the serial data. 520; A register 560 which receives serial data from the inside in the test mode and outputs in response to an input of a predetermined output control signal S1; A multiplexer 540 that receives an output of the serial / parallel conversion unit 520 or an output of the register 560 in response to an input of a predetermined selection signal S3 and outputs the selected input to the external pin; ; And a data input unit (580) for internally providing data input from the external pin in response to input of the selection signal (S3) and a predetermined input control signal (S2). The method of claim 2, And the register (560) is configured as a D flip-flop. The method of claim 1, The program memory 300 comprises a nonvolatile memory (ROM). The method of claim 1, The data memory (400) comprises an volatile memory (RAM) and a rewritable nonvolatile memory (EEPROM, 440). The method of claim 2, The data input unit 580 includes a buffer 582 which outputs data input from the external pins therein; A logic circuit unit configured to receive the selection signal S3 and the input control signal S2 and provide a corresponding signal to the buffer 582 through a predetermined logical operation to enable / disable the buffer 582. IC card circuit including 584. The method of claim 6, And the logic circuit section (584) is composed of an AND gate. The method of claim 1, The instruction input unit 600 includes a switching unit 640 for patching data output from the data memory 400 into an instruction in a test mode; An IC card including a register 620 for receiving a predetermined switching control signal S4 and outputting the switching control signal S4 to the switching unit 640 in response to the input of the predetermined control signal S5. Circuit. The method of claim 8, And the register (620) is configured as a D flip-flop. The method of claim 1, The flag (422) is set in a predetermined region of the rewritable nonvolatile memory (EEPROM, 440) provided in the data memory (400). An IC card controller 100, a serial I / O unit 500, a program memory 300, a data memory 400, an instruction input unit 600, and a flag 442 for determining whether or not to perform a test. In the test method of the IC card circuit: (a) determining whether the test mode is determined by determining the flag 442 when power is input to the IC card (S110); (b) in the normal mode, executing a predetermined IC card control program using the data memory 400 as a data memory area (S120, S130); (c) in the test mode, setting the data memory 400 as a program and a data memory area to load a predetermined test program from the outside (S140 and S150); (d) performing a predetermined IC card test by executing the loaded test program (S160). The method of claim 1, Step (d) is And when the test of the IC card is completed normally, setting the flag (442) to the normal mode.