KR19980060579A - Semiconductor memory device with extended memory function - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an extended memory function which significantly reduces the number of memory cells required for information storage by converting data associating data into use weight codes, thereby storing and reading information. A block, a data input buffer for buffering input data to be stored in the memory cell, a data output buffer for buffering data output from the memory cell, and input data output from the data input buffer as weighting codes. Data encoding means for encoding and transmitting data to the memory cell array block after data compression, and data decoding means for decoding the data output from the memory cell array block, restoring the data to its original state, and then transmitting the data to the data output buffer.

Description

Semiconductor memory device with extended memory function

The present invention corresponds to a binary code by writing a charge to a cell, whereas a conventional memory device writes a weight code to data of a cell. It is applicable to all memory devices (DRAM, SDRAM, SRAM, ROM, Flash Memory, etc.) as a method of storing the subject data.

1 is a block diagram of a 256M DRAM (DRAM) showing a process of reading / writing data to a conventional memory device.

In general, an operation of reading / writing data stored in a cell of a DRAM device will be described below.

First, the Ras (/ RAS) signal, which is the main signal for operating the DRAM element, changes to an active state, receives an address signal input to the row address buffer 19, decodes the received address signals, and decodes the cell array block 10_0. A row decoding operation is performed to select one of the word lines. At this time, when data of cells connected to the selected word line is loaded to the bit line BL / BL, the bit line sense amplifier is driven to supply the data of the minute signal loaded on the bit line to the power supply voltage Vcc and the ground voltage Vss. Will be amplified. Then, when the column address signal is input, the data of the amplified bit line includes only one bit line data selected by the column decoder output signal on the data bus line (IO / IO), and the data bus line sense amplifiers. Is sensed and amplified by the controller and then output to the outside of the device through the data output buffer 15_0.

As described above, the conventional memory device determines the data '1' and '0' by the presence or absence of the charge stored in the cell. As described above, when one data is stored in one cell, one giga bit SDRAM requires one gigabit, that is, 1,073,741,824 cells. The address of the memory device is also given as a binary number ('1' and '0') so that the density of the device is increased by an N power (integer) of two. For this reason, the density of most chips is increased by two powers of two, usually four times, and the density of cells is also increased by 2 ⁿ times, usually four times the density. This increases the density of the chip by increasing the number of cells by about 4 times by 2 ⁿ times, thereby increasing the power consumption.

Accordingly, an object of the present invention is to provide a semiconductor memory device having an extended memory function which significantly reduces the number of memory cells required for information storage by converting data associations into use weight codes and storing and reading information.

In order to achieve the above object, a semiconductor memory device having an extended memory function according to the present invention includes a plurality of memory cell array blocks, a data input buffer for buffering input data to be stored in the memory cell, and outputted from the memory cell. A data output buffer for buffering data, data encoding means for encoding input data output from the data input buffer into a weighted value code, and transmitting the data to the memory cell array block after data compression; and decoding output from the memory cell array block. Data decoding means for restoring the original state to the data output buffer.

1 is a block diagram showing a process of reading / writing data in a conventional memory device.

2 is a block diagram of a DRAM in accordance with an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10_0, 10_7: 32-bit cell array block

11_0, 11_7: Roo decoder

12_0, 12_7: column decoder

13_0, 13_7: Data bus sense amplifier

14_0, 14_7: Sense Amplifiers and Input / Output Gates

15_0, 15_7: Data output buffer 16_0, 16_7: Data output pin

18: data input buffer 19: row address buffer and latch circuit

20: column address buffer and latch circuit 21: control signal generating circuit

22: data output buffer control circuit

The above objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates a block diagram of a 256M DRAM according to an embodiment of the present invention, a memory cell array block 10_0, a data input buffer 18 for buffering input data to be stored in the memory cell, and the memory. Data output buffer 15_0 for buffering the data output from the cell, and input data output from the data input buffer 15_0 is encoded with a weighted code to compress the data and then transmit the data to the memory cell array block 10_0. A code encoder circuit 30 and a compressed code decoder circuit 40 for decoding the data output from the memory cell array block 10_0, restoring the original state, and transmitting the data to the data output buffer 15_0.

Referring to the operation by the above configuration, the binary data inputted to the data input buffer 18 is converted into an octal or hexadecimal value by the compression code encoder circuit 30 to be compressed. ) To save the data. For example, a device operating in units of bytes has eight data input buffers, D0 to D7, so that binary data is written to the chip. Here, if the 8-bit data is '00000001', it is '001' when expressed in binary code. The binary data '00000001' input to the data input buffer 18 is encoded by the compression code in the compression code encoder circuit 30 and then written to the cell, where the encoded data is (001) _c 3 bits. Since it is binary data, only three cells can write 8-bit '00000001' binary data.

When reading the data stored in the cell, the binary binary data 001 is read and then converted back to the original 8-bit binary data ('00000001') by the compression code decoder circuit 40 before the data output buffer 15_0. When the data is decoded and output, the binary data '00000001' is output at the DQ0 to 7 pins of the data output buffer.

As described above, the semiconductor memory device having an extended memory function according to the present invention can significantly reduce the number of memory cells required for data storage by converting the data association into a code among the available values and storing and reading them in the cell. In addition, the memory capacity can be increased according to the compression code, and data can be compressed to reduce power consumption. In addition, the data stored in the memory varies depending on the compression code and the length of the data, but the capacity of the conventional memory cells is increased. In the case where the memory capacity is fixed like the conventional SDRAM, the ECC code is Can be added without increase.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having an extended memory function that significantly reduces the number of memory cells required for information storage by converting data into a weight-weight code and storing and reading information. .

Claims (3)

In a semiconductor memory device, A plurality of memory cell array blocks, A data input buffer for buffering input data to be stored in the memory cell; A data output buffer for buffering data output from the memory cell; Data encoding means for encoding the input data output from the data input buffer into a weighted value code and transmitting the data to the memory cell array block after data compression; And data decoding means for decoding the data output from the memory cell array block, restoring the data to an original state, and transmitting the data output buffer to the data output buffer. The method of claim 1, And the weighting code has a 2 ³ × N decimal value. The method of claim 1, And said alphabet letter N is one or more natural numbers.