KR19980059924A - Tracking Error Detection Circuit - Google Patents

Abstract

The present invention relates to a tracking error detection circuit in a digital video disk (DVD) system. In particular, a light beam from an optical disk is detected using a plurality of photodetectors to be converted into an electrical signal. A photo detector for synthesizing and outputting the outputs of the devices, a comparator for comparing the two signals output from the photo detector with a preset reference signal, respectively, and outputting the square waves r and v, and r output from the comparator The phase difference detector detects the phase difference between the two signals, eliminates the abnormal signal caused by the disk defect, and outputs only the normal phase difference between the r and v signals, and low-pass filters the output of the phase difference detector and outputs the tracking error signal. It is configured to include an output unit, such as noise of the RF signal, disk defects such as disk defects, scratches By preventing an abnormal tracking error signal is not indicated by the output, it is possible to prevent the malfunction of the tracking servo due to the poor waveform performs exactly the search operation, such as data search.

Description

Tracking Error Detection Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video disc (DVD) system, and more particularly, to a tracking error detection circuit that prevents malfunction of a tracking servo by eliminating abnormal waveforms of tracking errors caused by a disc defect.

The function of tracking servo is to inject light while accurately finding the track.

That is, a tracking error signal corresponding to the beam trace state is detected and based on the signal, the objective lens and the main body of the optical pickup are moved to correct the position of the beam and track a predetermined track.

Conventionally, a signal that is out of the normal range due to a disc defect due to noise of a RF signal, a disc defect, a scratch, or the like is output as a tracking error signal as it is.

Therefore, the tracking servo could not perform accurate tracking due to an abnormal tracking error signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a tracking error detection circuit that prevents malfunction of a tracking servo by eliminating abnormal tracking error signals caused by a disk defect.

A feature of the tracking error detection circuit according to the present invention for achieving the above object is to detect the reflected light beam from the optical disk using a plurality of photodetectors to convert into an electrical signal, each of which is located at a diagonal position A photo detector for synthesizing and outputting the outputs of the photodetectors, a comparator for comparing the two signals output from the photo detector with a preset reference signal, respectively, and outputting the square waves r and v, and outputting the comparator After detecting the phase difference between r and v signals, eliminating the abnormal signal caused by the disk defect, and outputting the phase difference detector outputting the normal phase difference only between the r and v signals and the output of the phase difference detector, respectively, and outputting it as a tracking error signal. It is configured to include an output unit.

1 is an overall block diagram of a tracking elear detection circuit in accordance with the present invention.

FIG. 2 is a detailed block diagram of the phase difference detector of FIG. 1. FIG.

3 is a detailed circuit diagram of an error determining unit and a phase direction detecting unit of FIG. 2;

4A and 4B are signal waveform diagrams of normal errors

5A and 5B are signal waveform diagrams of abnormal errors exhibited by defects or scratches

6A to 6S are operation waveform diagrams of respective parts of the tracking error detection circuit according to the present invention.

Explanation of symbols for main parts of the drawings

10: phase difference detector 11, 13: equalizer

12, 14: Slicer 15: phase difference detector

16, 17: Low pass filter 18: Comparator

21, 22: Delay 23, 33, 35, 37: Exclusive OA gate

24: error determination unit 25: phase direction detection unit

26-28, 40: And gate 31, 34: Ora gate

32, 36, 38, 38: NAND gate 42: flip flop

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an overall block diagram of a tracking error detection circuit in accordance with the present invention.

1 shows an optical detector 10 converting a reflected light beam from a disk into an electrical signal and then outputting a + c and b + d, and a first RF signal output by a + c output from the photodetector 10. An equalizer 11 that increases only high frequency components, a first slicer 12 that outputs the equalizer 11 as a square wave by comparing the output of the equalizer 11 with a preset reference signal, and a b + d outputted by the photo detector 10; An equalizer 13 for increasing only the high frequency components of the 2RF signal, a second slicer 14 for outputting the output of the equalizer 13 as a square wave compared with a preset reference signal, and the first and second slicers 12 and 14. Low Pass Filter (LPF) for detecting the phase difference of the square wave output from the phase difference detector 15 and removing the abnormal signal caused by the disk defect, and low pass filtering the output of the phase difference detector 15, respectively. 16, 17, and the LPF 16, 1 And a comparator 18 for differentially amplifying the output of 7) and outputting a tracking error signal.

As shown in FIG. 2, the phase difference detector 15 outputs the output of the first delayer 21 and the second slicer 14 to delay the output r of the first slicer 12 by a predetermined time. The second delayer (22) for delaying a predetermined time, the exclusive oragate (23) for detecting the phase difference by logically combining the outputs of the first and second delayers (21, 22), the first and second slicers The phase for detecting the phase direction by comparing the outputs of the error determining unit 24 and the first and second slicers 12 and 14, which detect the phase error only in the normal signal by determining the similarity of the outputs of (12, 14). The AND detector 26 logically combines an output of the exclusive OR gate 23 with an output of the error determining unit 24, an output of the AND gate 26, and a phase direction detector 25. AND gate 27 for logically combining the output, and AND for logically combining the output of the AND gate 26 and the inverted output of the phase direction detection section 25. It consists of a gate 28.

3 illustrates a detailed circuit diagram of the error determiner 24 and the phase direction detector 25. The combination and arrangement of logic gates may vary depending on which logic gate is used.

Here, the photodetector 10 for detecting the light amount of the beam is composed of four photodetectors A, B, C, and D which are specifically divided in four directions, i.e., in the signal track direction and the radial direction of the optical disc. .

In the present invention configured as described above, the photodetector 10 a + c the electric signals a, b, c, and d proportionally to the amount of light obtained from each of the photodetectors A, B, C, and D to the equalizer 11. Output, b + d to output to equalizer 13. FIG.

Here, the first RF signal is a high frequency signal of a + c, the second RF signal is a high frequency signal of b + d.

The equalizer 11 amplifies only the high frequency components of the first RF signal with a predetermined gain and outputs the same to the first slicer 12, and the first slicer 12 outputs the square wave r in comparison with a preset reference signal. .

The equalizer 13 amplifies only the high frequency components of the second RF signal with a predetermined gain and outputs the result to the second slicer 14, and the second slicer 14 outputs the square wave v as compared with a preset reference signal. .

In this case, the phase difference between the two signals r and v output from the first and second slicers 12 and 14 is normally several tens of nsec (10 ⁻⁹ sec).

For example. In the case of single-speed DVD, more than 95% does not exceed 60 nsec. That is, the r and v signals made of the first and second RF signals have a rising edge of v as shown in FIG. 4b within 60 nsec before and after the rising edge of r as shown in FIG. 4a.

This is because the photodetecting elements A, B, C, and D of the four-segment photodetector 10 pass through a pit on the same disk to generate a signal.

On the other hand, if the RF defect occurs due to a disk defect or scratch, the phase difference between the two signals (r, v) output from the first and second slicers (12, 14) is abnormal as shown in Figure 5a, 5b The rising edge of v does not appear within tens of nsec before and after the rising edge.

As such, the outputs r and v of the first and second slicers 12 and 14 always have a similarity.

That is, the phase difference between the outputs r and v of the first and second slicers 12 and 14 does not exceed 60 nsec.

Therefore, by determining the similarity between the r and v signals, the phase error is detected in the signal determined to be normal and the phase error is not detected in the signal determined to be abnormal, thereby preventing the servo from malfunctioning with respect to the bad waveform.

To this end, the output of the first slicer 12 as shown in FIG. 6A is delayed by the first delay unit 21 for a predetermined time, and the output of the second slicer 14 as shown in FIG. 6B is transmitted to the second delay unit 22. After a predetermined time delay, the output is logically combined by the exclusive OR gate 23 as shown in FIG. 6N.

That is, the output of the exclusive OR gate 23 detects the phase difference between the two signals r and v as actual error signals.

6A and 6B, it is assumed that abnormal signals are output due to RF defects caused by disc defects or scratches, as shown by hatched portions of FIGS. 6A and 6B.

The delay time of the first and second delay units 21 and 22 is the time until the error determining unit 24 determines the similarity.

The error determining unit 24 determines whether a rising of another signal occurs within a specific time at a rising edge that first becomes 'high' in the r and v signals output from the first and second slicers 12 and 14. It is determined whether polling of another signal occurs within a specific time at a falling edge that is low, and a logic signal indicating a normal error is output only when the above condition is satisfied.

That is, the ora gate 31 of the error determining unit 24 logically combines two signals r and v output from the first and second slicers 12 and 14, respectively, as shown in FIG. And the NAND gate 38, and the NAND gate 32 outputs the r and v signals to the exclusive OR gate 37 and the NAND gate 39 in a logical combination as shown in FIG. 6D.

The OR gate 34 logically combines two output signals respectively output after being delayed by the first and second delayers 21 and 22 to the exclusive OR gate 35 as shown in FIG. 6E, and NAND. The gate 36 logically combines the two output signals of the first and second delayers 21 and 22 to the exclusive OR gate 37 as in FIG. 6F.

The exclusive oar gate 35 logically combines the output of the oar gate 31 with the output of the oar gate 31 and the signal delayed by a predetermined time, and outputs the logical oar gate 34 to the NAND gate 38 as in FIG. 6g. The exclusive OR gate 37 logically combines the output of the NAND gate 32 with the signal delayed by a predetermined time and outputs the output of the NAND gate 36 to the NAND gate 39 in a logical combination as shown in FIG. 6H.

The NAND gate 38 outputs the output of the ORA geat 31 and the exclusive ORA gate 35 to the AND gate 40 by logically combining the output as in FIG. 6I, and the NAND gate 39 is the NAND gate 39. The output of (32) and the output of the exclusive OR gate 37 are logically combined as in FIG. 6J and output to the AND gate 40.

That is, the NAND gate 38 first detects a few tens of nsec from the rising edge of the r or v signal that is high, and the NAND gate 39 first selects several tens of nsec from the falling edge of the r or v signal, which is low, for example, 60 nsec. Detect.

The end gate 40 logically combines the outputs of the NAND gates 38 and 39 as shown in FIG. 6K to provide a clock of the flip-flop 42.

Meanwhile, the exclusive oar gate 33 logically combines the two signals r and v outputted from the first and second slicers 12 and 14 as shown in FIGS. 6A and 6B, as shown in FIG. 6L. ) As the data input (D).

In this case, when the error occurs in the flip-flop 42 and there is no clock to latch before the error signal is output from the exclusive OR gate 33, the latched signal may be output as it is to output an error. The flip-flop 42 is cleared by inverting the output of the 33 with the inverter 41.

Accordingly, the flip-flop 42 outputs a low signal to the AND gate 26 through the Q output terminal as shown in FIG. 6M not only for the phase difference between the r and v signals but also for the error signal resulting from the missing RF signal. The high signal is output to the end gate 26 only for the part where there is no error.

The AND gate 26 logically combines the output of the exclusive OR gate 23 and the output of the flip-flop 42 which are delayed for a predetermined time to the AND gates 27 and 28 as shown in FIG. 6O.

On the other hand, the phase direction detection unit 25 is made of a flip-flop.

The phase direction detection unit 25 detects which phase of the r and v signals output from the first and second slicers 12 and 14 is faster, and receives the r signal as the D input. The signal is supplied to the clock input.

In this case, as shown in FIGS. 6A and 6B, the phase of the r signal is faster than the phase of the v signal.

Accordingly, the phase direction detection unit 25 outputs the low signal only to the RF missing portion of the r signal through the Q output terminal, and the high signal to the AND gate 27 in other cases.

Also, A signal opposite to the Q output terminal is output through the output terminal to the AND gate 28 as shown in FIG. 6Q.

The AND gate 27 logically combines the output of the AND gate 26 and the Q output of the phase direction detection unit 25 and outputs the same as illustrated in FIG. 6R, and the end gate 28 is connected to the AND gate 26. Of the output and phase direction detection section 25 The output is logically combined as shown in FIG. 6S.

That is, as shown in FIGS. 6R and 6S, the phase of the r signal is faster than the phase of the v signal, and the result of the AND gate 26 is output through the UP output terminal, which is the output terminal of the AND gate 27.

If the phase of the v signal is earlier than the phase of the r signal, the result of the AND gate 26 is output through the output terminal of the AND gate 28.

In this way, an error signal generated by a disk defect such as a disk defect or a scratch does not appear in the square wave signal output through the end gate 27.

The signal output through the UP output terminal of the phase detector 15 is smoothly low-pass filtered by the low pass filter 16 and then output to the non-inverting terminal (+) of the comparator 18.

In addition, the low signal output through the DN output terminal of the phase detector 15 is output to the inverting terminal (-) of the comparator 18 through the low pass filter 17.

The comparator 18 outputs a tracking error signal by comparing signals of the non-inverting terminal (+) with respect to the signal input to the inverting terminal (-).

The tracking error signal drives a tracking driver (not shown) of the optical pickup (not shown) to control tracking.

At this time, if an abnormal tracking error signal generated by noise of the RF signal, a disk defect, scratch, or the like is not output, the tracking servo tracks the track to the previous value so that a problem does not occur.

As described above, according to the tracking error detecting circuit according to the present invention, the tracking servo malfunctions due to a bad waveform by preventing the output of abnormal tracking error signals caused by noise of an RF signal or a disk defect such as a disk defect or a scratch. It is effective to perform search operation such as data retrieval by preventing the error.

Claims (4)

An optical detector which detects the reflected light beam from the optical disk by using a plurality of photodetectors and converts the signal into an electrical signal, and then synthesizes and outputs the outputs of two photodetectors at diagonal positions, respectively, and outputs from the photodetector Comparing the two signals to each of the predetermined reference signal and outputs a square wave (r, v) and the phase difference between the two signals output from the comparator, r, v to remove the abnormal signal represented by the disk defect And a phase difference detector for outputting only the normal phase difference of the two r and v signals, and an output unit for low pass filtering the output of the phase difference detector and outputting the tracking error signal. 2. The apparatus of claim 1, wherein the phase difference detector comprises: a delay unit for delaying the two signals r and v for a predetermined time, a first logic unit for detecting a phase difference between the two signals delayed from the delay unit, and An error determination unit which detects the phase difference between the two signals only when the phase difference between the two signals is within the normal range by determining similarity, and does not detect the phase error when the phase difference between the two signals is outside the normal range; And a phase direction detecting unit for determining whether the phase is fast and a second logic unit outputting through the UP or DN output terminal according to the detection result of the phase direction detecting unit after AND combining the output of the first logic unit and the output of the error determining unit. Tracking error detection circuit. 3. The tracking error detection circuit according to claim 2, wherein said first logic portion is composed of an exclusive oar gate. The tracking error detection circuit of claim 2, wherein the phase direction detector comprises a flip-flop receiving the r signal as a D input and a v signal as a clock input.