KR19980055941A - Erasing Method of Flash Memory Device - Google Patents

Abstract

The present invention relates to a method of erasing a flash memory device, and the operation characteristics of the device can be improved by allowing the erase operation to be performed on a word line basis in order to maintain a uniform threshold voltage of the erased memory cells and to prevent over erase. A method of erasing a flash memory device is provided.

Description

Erasing Method of Flash Memory Device

The present invention relates to a method of erasing a flash memory device, and more particularly, to a method of erasing a flash memory device to improve the operation speed and characteristics of the device.

In general, memory devices, such as Flash Eras (Electrically Erasable and Programmable Read Only Memory), have electrically programmed and erase functions. In addition, the memory cell of the flash memory device is divided into a stack-gate type and a split-gate type according to the shape of the gate electrode. The stacked-gate type flash memory cell is shown in FIG. 1. As shown, a gate electrode in which the tunnel oxide film 2, the floating gate 3, the dielectric film 4, and the control gate 5 are sequentially stacked on the silicon substrate 1 is formed. The source region 6 and the drain region 7 are formed in the silicon substrate 1, respectively.

In order to program information in the flash memory cell, that is, charge in the floating gate 3, a high potential voltage of about 9 V is applied to the control gate 5 and 5 to 5 in the drain region 7. A power supply voltage of about 6V is applied and a ground voltage is applied to the source region 6 and the silicon substrate 1, respectively. Then, a channel is formed in the silicon substrate 1 below the floating gate 3 by the high potential voltage applied to the control gate 5, and the voltage is applied to the drain region 7. A high electric field is formed in the silicon substrate 1 on the side of the drain region 7. At this time, a part of the electrons present in the channel receives energy from the high electric field region to become a hot electron, and a part of the hot electrons are applied to the high potential voltage applied to the control gate 5. It is injected into the floating gate 3 through the tunnel oxide film 2 with the help of an electric field formed in the vertical direction. Therefore, by this injection of the hot electrons as a threshold voltage of the flash memory cell: the (Threshold Voltage V _T) it is raised to about 5 to 6V.

In order to erase the information programmed in the flash memory cell, that is, to discharge the charge stored in the floating gate 3, a negative potential voltage of about -9V is applied to the control gate 5 and the source region 6 is applied. The power supply voltage of about 5V is applied and the ground voltage is applied to the silicon substrate 1 and the drain region 7, respectively. Then, the electrons injected into the floating gate 3 move to the source region 6 by FN tunneling (Fowler-Nordheim Tunneling) phenomenon, whereby the threshold voltage V _T of the memory cell is 1 to 1.5. Descends to about V.

In addition, in order to read the information programmed in the memory cell, a power supply voltage of about 5V is applied to the control gate 5 and a voltage of about 1V is applied to the drain region 7 and the silicon substrate 1 is applied. ) And a source voltage are applied to the source region 6, respectively. Then, the memory cell is turned on or turned off according to the state of the threshold voltage of the memory cell. In this case, the presence or absence of current flowing from the drain region 7 to the source region 6 is determined. By this, the state of the information stored in the floating gate 3 is read out.

However, the memory cell may be over erased during the erase operation. Transient erasing refers to a phenomenon in which the threshold voltage of the memory cell is lowered to 0 V or less (−0.5 to 1 V), thereby deteriorating an operating characteristic of the device. Therefore, the flash memory device has a recovery function to make the threshold voltage of an over erased memory cell equal to the threshold voltage of a normally erased memory cell. The recovery operation is performed by applying a voltage of about 5V to the source region 6 and applying a ground voltage to the control gate 5 and the source region 6, respectively, wherein the threshold of the normally erased memory cell is applied. The voltage is recovered with a gradual change over time (curve A) as shown in FIG. 2, while the threshold voltage of an over erased memory cell is recovered with a sharp change (curve B) as shown in FIG. 2. .

Next, the erase method of the conventional flash memory device will be described in detail with reference to FIG. 3.

3 is a flowchart illustrating a conventional method of erasing a flash memory device, and proceeds from a start step 11 to a step 12 to erase memory cells of a selected sector. In this case, an erase bias voltage as described above is applied to the control gate, the source region, the drain region, and the silicon substrate of each memory cell for the erase operation. In step 13, the erase state of all the memory cells of the selected sector is verified, and then, in step 14, the erase state of all the memory cells is checked. In this case, when even one memory cell is not erased, the operation returns to step 12 and the erase operation is repeatedly performed. However, if the erase operation is not performed even if the above operation is repeated a predetermined number of looping times, the erase operation is not performed. It generates a fail signal. On the other hand, when the erase of all the memory cells is confirmed in the step 14, the process proceeds to the step 15 to restore the threshold voltage of the over erased memory cell to the same as the threshold voltage of the normally erased memory cell during the erase operation. After performing the operation, the process proceeds to step 16 to end the erase operation.

However, in the case of using the above-described erase method, since the erase operation is performed in units of sectors, the number of selected memory cells is large, so that all of the selected memory cells are not completely erased by one erase operation. That is, different threshold voltages of the selected memory cells are maintained. Therefore, in order to keep all selected memory cells in a complete erase state, an erase operation may be repeatedly performed several times. At this time, an erase bias voltage is applied to the erased memory cell again, thereby causing excessive erase. Such over erased memory cells degrade the operation characteristics of the device and also increase the time required for the recovery operation.

Accordingly, an object of the present invention is to provide a method of erasing a flash memory device, which can solve the above disadvantages by allowing an erase operation to be performed on a word line basis.

According to an aspect of the present invention, there is provided a method of erasing memory cells connected to a first word line selected from a start signal, and an erase state of memory cells connected to the first word line from the first step. A second step of verifying; a third step of confirming whether or not the memory cells have been erased from the second step; and, if the memory cell of any one of the memory cells is not erased from the third step; A fourth step of returning to perform an erase operation; a fifth step of confirming that the selected word line is the last word line when all the memory cells are erased from the third step; and the selected step from the fifth step. A sixth step of returning to the first step after selecting the next word line if the word line is not the last word line; If the selected word line is the last word line from the fifth step is characterized in that it comprises a seventh step of performing a recovery operation so that the threshold voltage of the over erased memory cell is the same as the threshold voltage of the normally erased memory cell and then terminates. .

1 is a cross-sectional view of a typical stacked-gate flash memory cell.

2 is a graph for explaining a recovery operation of a flash memory device.

3 is a flowchart illustrating a method of erasing a conventional flash memory device.

4 is a flowchart illustrating a method of erasing a flash memory device according to the present invention.

Explanation of symbols on the main parts of the drawings

1 silicon substrate 2 tunnel oxide film

3: floating gate 4: dielectric film

5: control gate 6: source region

7: drain area

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

4 is a flowchart illustrating a method of erasing a flash memory device according to the present invention.

From step 21 to step 22, the memory cells connected to the selected first word line are erased. In this case, an erase bias voltage is applied to the control gate, the source region, the drain region, and the silicon substrate of each memory cell for the erase operation. In step 23, the erase state of the memory cells connected to the first word line is verified, and then, in step 24, the erase state of all the memory cells is checked. In this case, when any one of the memory cells is not erased, the process returns to step 22 and repeatedly performs the erase operation. However, even when the above-described operation is repeated for a predetermined number of loops, the erase operation is not completed. Generates a bad signal. On the other hand, if all of the memory cells are erased in step 24, the process proceeds to step 25 to determine whether the selected word line is the last word line. In this case, if the selected word line is not the last word line, the process proceeds to step 26 to select the next word line and returns to the step 22, and if the selected word line is the last word line, step 27 After performing the recovery operation so that the threshold voltage of the over erased memory cell is the same as the threshold voltage of the normally erased memory cell, the process proceeds to step 28 to end the erase operation.

In the case of using the above-described erase method, since the erase operation is performed on a word line basis, the number of selected memory cells is small, and thus all selected memory cells can be completely erased by one erase operation. That is, the threshold voltages of the selected memory cells are kept uniform. Therefore, the time required for the erase operation and the recovery operation is shortened to increase the operation speed of the device and to prevent excessive erasing, thereby improving the characteristics of the device.

As described above, according to the present invention, since the erase operation can be performed on a word line basis in order to prevent the deterioration of the operation characteristics of the device, which is generated when the conventional erase method is performed on a sector basis, the erase operation and the recovery operation are required. The time is shortened, the operation speed of the device is increased, and there is an excellent effect that the characteristics of the device can be improved by preventing excessive erasure.

Claims (2)

In the erase method of a flash memory device, Erasing memory cells connected to the first word line selected from the start signal; A second step of verifying erase states of memory cells connected to the first word line from the first step; A third step of confirming whether erasing of the memory cells is completed from the second step; A fourth step of returning to the first step and performing an erase operation again when at least one of the memory cells is not erased from the third step; A fifth step of checking whether the selected word line is the last word line when all the memory cells are erased from the third step; A sixth step of selecting a next word line and returning to the first step if the selected word line is not the last word line from the fifth step; And a seventh step of performing a recovery operation so that the threshold voltage of the over erased memory cell is equal to the threshold voltage of the normally erased memory cell when the selected word line is the last word line. Erasing method of a flash memory device. The method of claim 1, The erase operation of the fourth step may be repeated a predetermined number of loops, and if a complete erase operation is not performed during the looping number, a bad signal is generated.