KR19980053655A - Semiconductor memory device - Google Patents

Abstract

An object of the present invention is to provide a semiconductor memory device incorporating means for storing device parameters.

The present invention is a semiconductor memory device in which a memory cell array and a plurality of electrode pads for supplying electrical signals to the memory cell array are formed in one chip, wherein the process parameters and data are stored in the chip during the memory cell array process. Memory means for storing and an access enable pad to which a signal is applied to operate the memory means.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a ROM.

In general, when a bad package is generated during a test process of the semiconductor memory device, the DC or AC parameter of the semiconductor memory device is measured to analyze the cause of the failure.

The change in package characteristics of the conventional semiconductor memory device is determined by the data during the process. At this time, the data during the process is a parameter recording or photoresist pattern and the thickness of the nitride film, contact resistance, and the like, thereby analyzing the package characteristic change by the test process.

However, in the test process as described above, in order to analyze a change in package characteristics when a bad package occurs, each process data must be checked one by one.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and incorporates storage means for storing the main parameters and data during the process in the semiconductor memory device, and the data stored in the storage means during the failure analysis of the semiconductor memory device. It is an object of the present invention to provide a semiconductor memory device that uses the same.

1 is a block diagram schematically showing a memory device of the present invention;

FIG. 2 is a circuit diagram schematically showing the storage means of FIG.

Explanation of symbols on the main parts of the drawings

1: memory cell array 2: electrode pad

3: memory means 4: access enable pad

5: repair fuse 11: CMOS inverter

12: latch portion

In order to achieve the above object of the present invention, the present invention is a semiconductor memory device in which a memory cell array and a plurality of electrode pads for supplying an electrical signal to the memory cell array are formed in one chip, the chip And storage means for storing process parameters and data during the memory cell array process, and an access enable pad for receiving a signal to operate the storage means.

According to the present invention, the processing time is shortened by incorporating a storage means for storing the main parameters and data during the process in the semiconductor memory device so that the data recorded in the ROM can be used during the failure analysis of the semiconductor memory device.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically showing a memory device of the present invention, and FIG. 2 is a circuit diagram schematically showing the storage means of FIG.

First, referring to FIG. 1, in the schematic configuration of the present invention, a memory cell array 1 is positioned at a predetermined position on a chip, and a plurality of electrode pads 2 are arranged on one side of the memory cell array 1. Arranged on the phase.

On the same chip, storage means 3 for storing process parameters and data during the memory cell forming process is provided in the same number as the memory cell array, and access enable pads 4 for operating the memory means 3 are provided. do.

At this time, the storage means 3 is a ROM for storing data even when the power supply is cut off. On this semiconductor chip, a repair fuse 5 is provided on the semiconductor chip to replace an extra line when the wiring of the memory cell array is shorted. .

The semiconductor memory device of the present invention having such a configuration easily stores the main parameters and data in the memory cell forming process in the storage means and easily utilizes the data stored in the storage means in the process of analyzing the change in package characteristics. Analyze the characteristic change of.

Here, the ROM, which is the storage means 3, has a CMOS inverter 11 receiving an input signal from the ROM access enable pad 4 and a latch into which the output of the inverter 11 is input, as shown in FIG. And a portion 12. Here, the latch unit 12 is an N-MOS transistor.

First, when the memory cell array is operating normally, the ROM access enable pad 4 is floating, that is, a low signal is applied, so that the PMOS of the CMOS inverter 11 is turned on, and the output of the CMOS inverter indicates high, and the latch The part 12 is turned on.

That is, the input signal maintains the low signal unless the input signal is changed by the turn-on of the latch unit 12, so that the output of the CMOS inverter also maintains the high signal, so that the ROM does not operate. do.

On the other hand, in the memory cell forming process, when reading data stored in the ROM, a Vcc voltage, that is, a high signal is applied to the ROM access enable pad 4, so that the NMOS of the CMOS inverter 11 is turned on and the CMOS inverter ( The output of 11 indicates low, and the latch portion 12 is turned off. That is, the input signal does not maintain a constant signal due to the turn-off of the latch unit 12, and a voltage applied to the ROM access enable pad 4 becomes an input signal, and thus, the CMOS inverter 11 The output also depends on the input signal.

Therefore, as the high signal is input to the ROM access enable pad 4 to which the low signal is continuously applied, the CMOS 11 is converted from the high signal to the low signal, so that the operation of the memory cell is stopped and through the ROM. The stored data will be read.

As described in detail above, according to the present invention, a memory means for storing the main parameters and data during the process is built in the semiconductor memory device so that the data stored in the memory means can be used for failure analysis of the semiconductor memory device. The process time is shortened.

Claims (5)

A semiconductor memory device in which a memory cell array and a plurality of electrode pads for supplying electrical signals to a memory cell array are formed in one chip. And a storage means for storing process parameters and data during said memory cell array process, and an access enable pad for receiving a signal to operate said storage means. The semiconductor memory device according to claim 1, wherein the memory means is provided in equal numbers to correspond to the memory cell array. 2. The semiconductor memory device according to claim 1, wherein said storage means is a ROM for storing stored data even if the power supply is cut off. The semiconductor memory device of claim 1, wherein the ROM comprises a CMOS inverter configured to receive an input signal from an access enable pad and a latch unit configured to operate according to an output of the inverter. The semiconductor memory device according to claim 4, wherein the latch unit is an NMOS transistor.