KR19980052415A - Improved Output Buffer Circuit - Google Patents

Abstract

The present invention relates to an improved output buffer circuit that enables a buffer circuit output signal to sense a voltage level and to control pull-down switching of a distributed pull-down transistor using the sense signal. The delay means for turning on one pull-down transistor after a delay time using a primary delay circuit among the two pull-down transistors distributed in the circuit and then turning on another pull-down transistor after a predetermined delay time using a secondary delay circuit is not employed. By connecting one input of the NOA gate, which controls the switching of another pull-down transistor, to the output signal C of the buffer, a technique of detecting the output voltage level of the buffer and controlling the driving of the other pull-down transistor distributed based on the detection result Employ means. Therefore, the present invention can suppress an unnecessarily increase in chip area and can realize a constant pull-down swing irrespective of fluctuations in delay time caused by processor differences.

Description

Improved Output Buffer Circuit

The present invention relates to an output buffer for use in integrated circuit devices, and more particularly, to suppress undershoots and resulting noise components due to output swings with large currents in output buffers used in flash memory devices. An improved output buffer circuit is disclosed.

In recent years, with the development of semiconductor technology, development of flash memory capable of electrically rewriting data and enabling high-capacity data processing at high speed has been actively conducted everywhere. It is estimated that DRAM and SRAM will be replaced quickly because it is not necessary.

On the other hand, such a flash memory has an output buffer at its output side like DRAM, SRAM, etc. At this time, the output buffer amplifies the output signal or blocks noise or the like from flowing into the output signal and performs stable operation between circuits. It can be seen that it is necessary.

As described above, a typical example of the output buffer used for the flash memory is one of the type shown in FIG.

As shown in the figure, a typical conventional output buffer having one pull-up transistor M13 and two pull-down transistors M14 and M15 includes at least three control logic circuits. In this case, the input signal A is a sensing output signal, the input signal B is an output enable signal, and the output signal C is an output signal of an output buffer connected to an output pad (not shown).

Referring to FIG. 1, a pull-up driver for driving an up transistor M13 constituted by a P-type MOS transistor includes an inverter G11 that counteracts an input enable signal B and a sensing output signal A as one input. NAND gate G12 having the output of the inverter G11 as the other input, and NOR gate G14 having the output of the NAND gate G12 as one input and the output of the delay circuit D11 described later as the other input. And an inverter G15 for inverting the output of this noah gate G14.

Further, the first pull-down driver for driving the pull-down transistor M14 composed of the N-type MOS transistors has a noah gate (G13), the noah gate having the sensing output signal A as one input and the output enable signal B as the other input. Inverter G16 for inverting the output of G13, inverter G17 for inverting the output of NOR gate G13, delay circuit D12 for delaying the output of inverter G17 for a predetermined time, and delay circuit D12. Is composed of a NOR gate G18 having the output of the input as one input and the output of the inverter G16 as the other input.

Further, the second pull-down driver for driving the pull-down transistor M15 composed of the N-type MOS transistors includes a P-type transistor M11 having a source connected to the voltage VDD and a gate connected to the output of the inverter G16, which is a P-type transistor. The delay circuit D11 connected to the drain output of the M11, the gate is connected to the output of the inverter G16 in common with the gate of the transistor M11, and the source is the output of the delay circuit D11, the gate of the Noah gate G14. The N-type transistor M12 is connected to the gate of the other input and the pull-down transistor M15 in common.

Next, referring to the operation of the conventional output buffer circuit having the above-described configuration, in order to transfer the sensing output signal A to the output pad, if the output enable signal B is at the low level (L), the output buffer is enabled. When the output signal A is at the high level H, the output of the NAND gate G12 is at the low level L standby state, and is pulled down through the NOR gate G13, the inverter G16, and the NOR gate G18. The transistor M14 is first disabled, and the pulldown transistor M15 is also disabled through the NOR gate G13, the inverter G16, and the N-type transistor M12.

At this time, the output of the N-type transistor M12 is provided to the other input of the NOR gate G14, and as a result, the pull-up transistor H13 is turned on through the NOA gate G14 and the inverter G15, thereby outputting the output. The output signal C of the buffer is at the high level (H).

On the other hand, when the sensing output signal A is at the low level (L), the pull-up transistor M13 connected to the gate thereof through the NAND gate G12, the NOR gate G14, and the inverter G15 is in a disabled state. The pull-down transistor M15 connected to the NOR gate G13, the inverter G16, the P-type transistor M11, and the delay circuit D11 is slowly delayed by a predetermined time delayed by the delay circuit D11. A predetermined time which is turned on and the pull-down transistor M14 whose gate is connected through the NOR gate G13, the inverter G17, the delay circuit D12, and the NOA gate G18 is delayed at the delay circuit D12. It is turned on after a significant delay. Therefore, the output signal C is changed from the pull-down swing, that is, from the high level (H) state to the low level (L) state. Here, each of the delay circuits D11 and D12 may be composed of a resistor R and a capacitor C, for example.

That is, in the conventional output buffer circuit having the above-described configuration, when the output signal C pulls down from the high level state to the low level state, in order to reduce noise of the output switching, the pull-down transistor M15 is turned on so that the VIL level is reduced. When the voltage is lowered to the threshold voltage level, the pull-down transistor M14 is turned on with a delay time difference in the delay circuit D12. At this time, the delay time in the delay circuit D12 must be well adjusted. Is controlled by a resistor and a capacitor forming the delay circuit (D12).

In addition, since the pull-down transistor M15 is first turned on, when dividing the width sizes of the transistors M15 and M14, the split-down transistor M14 is divided into M15M14 in consideration of the speed of the output signal C, and the pull-down transistor M14 is merely an output signal C. Is sufficient to have a VIL level (threshold voltage level).

This is because if the delay time in the delay circuit D12 is short and the pull-down transistor M14 is turned on at a too fast time, the pull-down transistor becomes ineffective in two, and the delay time in the delay circuit D12 is too long, so the pull-down transistor is too long. If (M14) is turned on too late, it will adversely affect the speed delay.

On the other hand, in order to minimize undershoot and noise generation at the output stage as described above, the conventional output buffer circuit allocates a pull-down driver having a large size of the output stage to a small size, and one of the distributed pull-down drivers is normally The sensing output signal is driven through an output buffer stage, and the other is driven with a time difference for delaying the sensing output signal for a predetermined time using a delay circuit.

However, the conventional output buffer circuit as described above has a problem in that the chip area is unnecessarily increased due to the delay circuit composed of a resistor and a capacitor which requires a large area in design, and the time difference delay between the delay circuits is not accurate. If the pull-down transistor is turned on too quickly, the allocation effect of the pull-down transistor is lost, and if the pull-down transistor is turned on too late due to too many delays, there is a problem that a time difference is caused by the size allocation of the pull-down transistor, which adversely affects the swing speed. have.

Accordingly, the present invention is to solve the above-mentioned problems of the prior art, an improved output buffer circuit that can sense the voltage level of the buffer circuit output signal, and control the switching of the pull-down transistor distributed using the sense signal. The purpose is to provide.

1 is a logic diagram of a typical typical output buffer circuit,

2 is a logic diagram of an improved output buffer circuit according to a preferred embodiment of the present invention.

In order to achieve the above object, the present invention, in the output buffer circuit having a pull-up transistor and two pull-down transistors distributed to buffer the pull-down swing of the output buffer, the logic of the external sense output signal and the output enable signal A first logic circuit unit outputting a first control signal for pull-up driving control of the pull-up transistor by a combination; And a first control signal for controlling the driving of one of the two pull-down transistors distributed by the logical combination of the sense output signal and the output enable signal. A second logic circuit unit outputting a delayed second control signal; And outputting a third control signal for controlling driving of one of the two pull-down transistors distributed by the logic combination signal between the sensing output signal and the output enable signal and the output voltage level signal of the output buffer. A third logic circuit portion is provided.

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is an improved output buffer circuit diagram according to a preferred embodiment of the present invention.

Referring to FIG. 2, the output buffer circuit according to the present invention turns on one pull-down transistor M15 of two pull-down transistors distributed as in the conventional buffer circuit shown in FIG. Instead of having a delay circuit D12 to turn on another pull-down transistor M14 later, by connecting one input of the NOR gate G27 to control the switching of the other pull-down transistor M24 to the output signal C of the buffer. Detects the output voltage level of the buffer and controls the driving of the pull-down transistor M24 distributed based on the detection result (e.g., turns on the pull-down transistor M24 when the voltage Vout of the output signal is 2.0V). Having the greatest technical features, the object of the present invention will be achieved by these technical characteristics.

In addition, in the conventional buffer circuit, as shown in FIG. 1, the driving of the pull-down transistor M14 distributed using the delay signal obtained by delaying the output enable signal for a predetermined time period (pull-down swing of the output buffer is performed). In the improved output buffer circuit of the present invention, on the other hand, as shown in FIG. 2, the output voltage level of the output buffer is sensed and the pull-down transistor M24 distributed based on the detection result. Other components are substantially the same, except that they control the driving of (turn on for pull-down swing of the output buffer). Therefore, detailed description of the operation of other devices will be omitted in the following to avoid unnecessary overlapping materials.

Referring to FIG. 2, the output buffer circuit of the present invention has two pull-down drivers distributed as in the conventional circuit described above, one driver lowering the level of the buffer output voltage, and the other pull-down driver When the output voltage level reaches a predetermined level, that is, the threshold voltage of the NOR gate G27 (for example, 2.0V to 1.5V), the output voltage is sensed and turned on to automatically realize a pull-down swing of the output buffer. Therefore, the buffer circuit of the present invention does not need to include the inverter G27 and the delay circuit D22 of FIG. 2 required in the conventional circuit, and also needs to care about the turn-on timing of the pull-down transistor M24 having a delay time. There will be no.

That is, one input of the NOR gate G27 for turning on the pull-down transistor M24 distributed for the pull-down swing in the output buffer is connected to the output signal C of the buffer and the other input of the inverter G26 is the same as in the conventional circuit. Connected to the output. At this time, assuming that the threshold voltage of the NOR gate G27 logic is designed to be 2.0 V to 1.5 V as an example, when the voltage level of the output signal C of the output buffer becomes the threshold voltage level of the NOR gate G27, Gate G27 turns on pull-down transistor M24.

In this case, the reason why the output signal of the inverter G26 is used as the other input of the NOR gate G27 is that the pull-down transistor M24 is first disabled by using the output of the inverter G26 before the pull-up transistor M23 is turned on. To give.

As described above, according to the present invention, by eliminating the delay circuit composed of resistors and capacitors that require a large area in the conventional circuit, the chip area can be effectively suppressed from increasing unnecessarily, and the voltage level of the output buffer can be suppressed. And the pull-down transistor for the pull-down swing is turned on based on the detection result, thereby achieving a constant pull-down swing regardless of the variation in delay caused by the processor difference.

Claims (4)

An output buffer circuit having a pull-up transistor and two pull-down transistors distributed to buffer a pull-down swing of the output buffer, A first logic circuit unit outputting a first control signal for pull-up driving control of the pull-up transistor by a logic combination of an external sensing output signal and an output enable signal; And a first control signal for controlling the driving of one of the two pull-down transistors distributed by the logical combination of the sense output signal and the output enable signal. A second logic circuit unit outputting a delayed second control signal; And Outputting a third control signal for controlling driving of one of the two pull-down transistors distributed by the logic combination signal between the sensed output signal and the output enable signal and the output voltage level signal of the output buffer; An improved output buffer circuit with three logic circuit sections. The method of claim 1, The third logic circuit unit has a logic combination signal between the sensing output signal and the output enable signal provided by the second logic circuit unit as one input and the output voltage level signal of the output buffer as the other input, and the output is the input. An improved output buffer circuit, comprising a Noah gate connected to the gate of another pull-down transistor. The method of claim 2, And the NOR gate turns on the other pull-down transistor when the output voltage level signal sensed by the output buffer reaches a predetermined threshold voltage. The method of claim 3, wherein And a predetermined threshold voltage of the NOR gate is in the range of 2.0V to 1.5V.