KR19980048584A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

Disclosed are a semiconductor memory device and a method of manufacturing the same. A memory device of the present invention includes a semiconductor substrate of a first conductivity type; A gate electrode formed on the semiconductor substrate; Source and drain regions of a second conductivity type formed on both sides of the gate electrode; A first interlayer insulating film formed over the substrate including the gate electrode; And a bit line formed on the first interlayer insulating layer to be in contact with the drain region, and including a low concentration impurity region of a second conductivity type formed to increase the depletion length at the junction interface between the drain region and the substrate. It is done.

Description

Semiconductor memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a dynamic random access memory (DRAM) and a method of manufacturing the same.

In recent years, the widespread use of information devices such as computers has increased the demand for semiconductor memory devices. In particular, there is a great need for semiconductor memory devices having large storage capacities and operating at high speeds, which demands follow the development of techniques for improving the integration density, response and reliability of semiconductor memory devices.

Among semiconductor memory devices, a DRAM is known as a memory capable of inputting arbitrary information or outputting already stored information, and a general DRAM inputs an external signal and a portion of a memory cell array in which a large amount of information as a storage area is stored. Or a peripheral circuit portion for outputting.

In the conventional DRAM cell, as shown in FIG. 1, a MOS transistor T having a gate connected to a word line WL and selectively turned on / off, and a bit according to an on / off operation of the MOS transistor T It includes a charge storage capacitor (Cs) for charging or discharging the charge selectively input through the line (BL). Here, reference numeral Cb denotes a parasitic capacitor of the drain region in contact with the bit line.

In the conventional highly integrated high-capacity memory device, the capacitor of the bit line increases due to the following reasons.

That is, the bit line capacitor is proportional to the number of memory cells connected to one bit line, proportional to the source capacitance of the transistor of the memory cell, and the junction capacitance between the bit region and the bit line, and intersects the bit line and the bit line. Since the capacitance of the word line or power line is proportional to the coupling capacitance, in the current memory device, the capacitor of the bit line is increased.

Accordingly, the sensing voltage inversely proportional to the bit line capacitance [Vsen = (Cb x Vblp + Cs x Vcc) / (Cb + Cs) where Cb is the capacitance of the bit line, Vblp is the bit line precharge voltage, and Cs Is the storage node capacitance, and Vcc represents the power supply voltage.] The voltage value gradually decreases as the bit line capacitor increases, and the sensing margin decreases. As a result, a problem occurs that a malfunction of the DRAM device occurs.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of reducing the capacitance of a bit line and ensuring a sensing margin of a semiconductor DRAM element.

1 is a circuit diagram schematically showing a general DRAM cell.

2 is a cross-sectional view of a DRAM cell according to the present invention.

3A to 3C are cross-sectional views illustrating a method of manufacturing a DRAM cell according to the present invention.

* Description of the symbols for the main parts of the drawings *

11: semiconductor substrate 13: gate electrode

17A, 17B: source, drain region 18: first interlayer insulating film

19: low concentration impurity region 20: bit line

In order to achieve the above object of the present invention, the present invention is a semiconductor substrate of the first conductivity type; A gate electrode formed on the semiconductor substrate; Source and drain regions of a second conductivity type formed on both sides of the gate electrode; A first interlayer insulating film formed over the substrate including the gate electrode; And a bit line formed on the first interlayer insulating layer to be in contact with the drain region, and including a low concentration impurity region of a second conductivity type formed to increase the depletion length at the junction interface between the drain region and the substrate. It is done.

In addition, the present invention comprises the steps of forming a gate electrode on the semiconductor substrate of the first conductivity type; Forming source and drain regions of a second conductivity type on both sides of the gate electrode of the substrate; Forming a first interlayer insulating layer on the semiconductor substrate; Etching the first interlayer insulating layer to expose the drain region, thereby forming a first contact hole; Ion implanting a low concentration impurity of a first conductivity type into a junction interface between the exposed drain region and the substrate; And forming a bit line on the first interlayer insulating layer to contact the drain region through the first contact hole.

According to the present invention, by implanting a low concentration of impurities to increase the depletion length at the junction interface between the drain region and the substrate, the coupling capacitance of the drain is reduced, and the parasitic capacitance in the bit line of the DRAM is reduced. Therefore, the sensing margin of the DRAM device is increased, and malfunctioning is prevented.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a semiconductor DRAM device of the present invention, and FIG. 3 is a cross-sectional view illustrating a method of manufacturing a semiconductor DRAM device according to the present invention.

This embodiment proposes a DRAM cell having a structure for reducing a junction parasitic capacitor in a drain region and a method of manufacturing the same in order to reduce the bit line capacitor.

First, referring to FIG. 2, a source / drain region (i.e., composed of a first conductivity type region 14A, 14B of a second conductivity type, for example, N and a highly concentrated impurity region 16A, 16B, of type N) 17A and 17B are formed in the semiconductor substrate 11 of the first conductivity type, for example, at a predetermined distance from each other.

The gate oxide film 12 and the gate electrode 13 are formed in a predetermined portion above the semiconductor substrate 11. In this case, the gate electrode 13 is formed on the semiconductor substrate 11 between the source / drain regions 17A and 17B, and the side wall spacers 15 are formed of the first low concentration region 14A on both sides of the gate electrode 13. 14B) is formed on top.

The first interlayer insulating film 18 is formed on the resultant portion, and the first interlayer insulating film 18 is partially etched to expose the drain regions 17A and 17B.

The bit line 20 is formed on the first interlayer insulating film 18 and is in contact with the drain region 17B. At this time, a second low concentration impurity region 19 having a second conductivity type, for example, an N type impurity type, is formed at the interface between the drain region 17B and the substrate 11, and the second low concentration impurity region 19 is formed. ) Has a lower concentration than the first low concentration impurity region 14B.

The second interlayer insulating film 21 is formed on the entire surface of the structure in which the bit line 20 is formed, and the storage node electrode 22 is formed on the second interlayer insulating film 21 to be in contact with the source region 17A. .

In the present embodiment, the second conductivity type second low concentration impurity region 19 formed at the junction interface between the drain region 17B and the substrate 11 increases the deflection length Xd of the substrate and the drain region 17B. Thereby reducing the coupling capacitance of the bit line.

That is, in more detail, a junction capacitance Cb is formed between the drain region 17B and the substrate 11, and the junction capacitance is C = eA / Xd (where e: dielectric constant, A: area, and Xd: Deflation length). From the above equation, the junction capacitance decreases as the length of deflation at the junction interface between the drain region 17B and the substrate 11 increases.

Hereinafter, a method of manufacturing a semiconductor memory device according to the present embodiment will be described with reference to FIGS. 3A to 3C.

First, referring to FIG. 3A, a gate oxide film 12 having a thickness of 50 to 150 kV is formed by a thermal oxidation method on the first conductivity type, for example, P-type semiconductor 11. The polysilicon film is formed to a predetermined thickness on the gate oxide film 1 by chemical vapor deposition (CVD). The polysilicon film and the gate oxide film 2 are patterned to form a gate electrode 13.

Thereafter, in order to form a junction region, a second conductivity type, for example, an N-type impurity is ion-implanted into the semiconductor substrate 11 on both sides of the gate electrode 13 to form source / drain regions 17A and 17B. do. Subsequently, an oxide film having a thickness of 1000 to 2000 GPa is deposited evenly on the resultant and then anisotropically etched to form the side wall spacers 15.

Referring to FIG. 3B, the first interlayer insulating film 18 is formed on the semiconductor substrate with a predetermined thickness. Here, the first interlayer insulating film 18 is a film having planarization characteristics, and is formed of a multilayer insulating film including a planarization film such as BPSG. The first interlayer insulating layer 18 is partially etched to expose the drain region 17B to be contacted with the bit line, thereby forming a contact hole H.

Subsequently, the second low concentration impurity 19 of the second conductivity type, for example, 31 P ions is implanted with predetermined energy so as to be disposed at the junction interface between the substrate and the drain region 17B, so that the drain region 17B and the substrate The second low concentration impurity region 19 is formed at the junction interface. The second low concentration impurity region 19 has a lower concentration than the first low concentration impurity for forming the junction region, and as described above, depletion at the junction interface between the drain region 17B and the substrate 11. It serves to increase the length, thereby reducing the bit line junction capacitance in the DRAM device.

As shown in FIG. 3C, a conductive layer such as polysilicon doped to contact is formed on the first interlayer insulating film 8 through the drain region 17B and the contact hole H by the bit line 20. . Thereafter, the second interlayer insulating film 21 is formed on the semiconductor substrate 11 to have a predetermined thickness. Here, the second interlayer insulating film 21 may also be formed of a multilayer insulating film including a film having a planarization characteristic, for example, a BPSG film single film or a BPSG film. Then, the second interlayer insulating film 21 and the first interlayer insulating film 18 are etched to expose the source region 17A, and then the storage node 22 is formed to contact the source region 17A.

As described above, the present invention ion implants low concentration impurities to increase the depletion length at the junction interface between the drain region and the substrate, thereby reducing the junction capacitance of the drain and reducing the parasitic capacitance in the bit line of the DRAM. Therefore, the sensing margin of the DRAM device is increased, and malfunctioning is prevented.

Claims (11)

A semiconductor substrate of a first conductivity type; A gate electrode formed on the semiconductor substrate; Source and drain regions of a second conductivity type formed on both sides of the gate electrode; A first interlayer insulating film formed over the substrate including the gate electrode; And a bit line formed on the first interlayer insulating layer to be in contact with the drain region, and including a low concentration impurity region of a second conductivity type formed to increase the length of the cavity at the junction interface between the drain region and the substrate. A semiconductor memory device. 2. The semiconductor memory device of claim 1, wherein the first conductivity type is P type and the second conductivity type is N type. The semiconductor memory device according to claim 1, wherein the low concentration impurity region of the second conductivity type has a lower concentration than the source drain region. 4. The semiconductor memory device according to claim 3, wherein the low concentration impurity region of the second conductivity type is made of the same impurity as the drain region. Forming a gate electrode on the first conductive semiconductor substrate; Forming source and drain regions of a second conductivity type on both sides of the gate electrode of the substrate; Forming a first interlayer insulating layer on the semiconductor substrate; Etching the first interlayer insulating layer to expose the drain region, thereby forming a first contact hole; Ion implanting a low concentration impurity of a first conductivity type into the exposed drain region and the junction surface of the substrate; And And forming a bit line on a first interlayer insulating layer to be in contact with the drain region through the first contact hole. The method of claim 5, wherein the forming of the gate electrode comprises: forming a gate oxide layer on the semiconductor substrate; Forming a polysilicon film on the gate oxide film; And partially etching the polysilicon film and the gate oxide film. The method of claim 5, wherein the forming of the source and drain regions comprises: implanting low concentration impurities of a second conductivity type into both sides of the gate electrode of the substrate; Forming sidewall spacers on both sidewalls of the gate electrode; And implanting a high concentration of impurities of a second conductivity type into both sides of said gate of said substrate. 6. The method of claim 5, wherein the first conductivity type is P type and the second conductivity type is N type. 8. The semiconductor device according to claim 5 or 7, wherein the low concentration impurity of the second conductivity type implanted into the junction interface between the substrate and the drain region has a concentration lower than that of the low concentration impurity region forming the source and drain regions. Method of manufacturing a memory device. 10. The method of claim 9, wherein the low concentration impurity of the second conductivity type is 31P. 6. The method of manufacturing a semiconductor memory device according to claim 5, wherein the low concentration impurity region of the second conductivity type is made of the same impurity as the drain region.