KR19980047430A - Nonvolatile Semiconductor Memory Device - Google Patents

Abstract

The present invention relates to a nonvolatile semiconductor memory device capable of preventing a malfunction of a memory device by improving a sensing margin of a flash type semiconductor memory device having an overlapped bit line structure. At least two reference voltage generators for generating a voltage; A voltage value of a reference cell string located closest to a selected cell string among the two or more reference cell arrays, including at least two reference cell arrays receiving respective reference voltages from the at least two reference voltage generators Is sensed as the reference voltage. By such a device, it is possible to prevent the under-program phenomenon caused by recognizing that the program is completed during the program operation and the over-program phenomenon caused by continuously performing the program operation. Therefore, the nonvolatile semiconductor memory device malfunctions. Can solve the problem.

Description

A nonvolatile semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and in particular, to improve sensing margin of a flash type memory device having a folded bit line structure (hereinafter, referred to as a “folded bit line” structure) to prevent malfunction of a memory device. A nonvolatile semiconductor memory device is provided.

In a conventional semiconductor memory device having a folded bit line structure, a main string level based on cell data is formed on either side of a sense amplifier, and the selected cell data is turned on. detect whether it is 'on' or 'off'.

1 schematically illustrates a configuration of a conventional nonvolatile semiconductor memory device.

Referring to FIG. 1, in the conventional nonvolatile semiconductor memory device, cell arrays 12 and 18 are formed on both sides of an upper page buffer 14 and a lower page buffer 16, respectively. ) Is connected to the row address decoders 24 and 26 that receive an address signal from the outside. Reference cell arrays 10 and 20 are formed at both sides of the cell arrays 12 and 18 to receive reference voltages Vref generated from the reference voltage generators 22 and 28.

In addition, referring to FIG. 2, the reference voltage generators 22 and 28 may include an orgate 30 that receives a read signal Oread and a program verify signal Opgmvf from an external device, and a gate terminal of the orifice 30. A first N-type MOS transistor 32 connected to an output terminal of the first N-type transistor, and a source terminal connected to a drain terminal of the first N-type transistor; A gate between the first and second resistors 36 and 38 connected in series with the drain terminal of the second N-type MOS transistor 34, and between the second N-type MOS transistor 34 and the first resistor 36. The terminal is connected, the drain terminal is connected to the drain terminal of the first N-type MOS transistor, and the source terminal comprises a P-type MOS transistor 40 connected to the gate terminal of the second N-type MOS transistor. Have

The reference level of the nonvolatile semiconductor memory device having such a configuration is to locate the reference cell string farthest from the bit line (hereinafter referred to as BL) with respect to the page buffer. The 'Develope' of the BL caused by the cell string (which means that the current flows through the selected cell string from the precharged level and gradually the BL level drops to the ground potential) is turned on. It can be formed by maintaining a middle level between the development degree of the BL by the cell and the development degree of the BL by the worst 'off' cell.

In this case, however, the degree of BL development by the reference cell looks at all the RC loadings of the BL. At this time, since about 512 cell strings are located in the BL, the BL near the page buffer is less loaded, and the BL near the reference cell string has a larger loading, resulting in a difference in BL loading. There is a difference in RC when it is developed from this level.

Accordingly, as shown in FIG. 3, a difference in the degree of development is generated according to the position of each cell string, which causes a problem that the sensing margin varies depending on the position. In particular, this phenomenon causes a greater problem with higher precharge levels, even if it is limited to BL development by 'on' cells.

Such a difference in BL loading causes a more serious problem in program verify that verifies the presence or absence of a program in a conventional nonvolatile semiconductor memory device (hereinafter referred to as 'NVDRAM').

The program verification process in NVDRAM is the same as the conventional read sensing process, and the precharged level is relatively higher than that of read.

For example, as illustrated in FIGS. 4A to 4B, when programming a cell located relatively far from the page buffer and when programming a cell located close to the page buffer, the programmed degree after the first program is executed. If the same is verified, if it is verified, the far side from the page buffer is delayed and sensed as 'off' due to the difference in the developer depending on the position.

Therefore, during the next cycle of program operation, the program is recognized as being completed and program inhibited, resulting in a lower under-program phenomenon than the program is intended to program.

On the contrary, cells located close to the page buffer are sensed as 'on' because they are rapidly developed due to their relatively low loading, and more over-programs can be performed by continuing the program operation during the next cycle of programming. Over-programming occurs, causing a serious problem of malfunctioning all strings containing over-programmed cells.

Accordingly, the present invention proposed to solve the above problems, to provide a nonvolatile semiconductor memory device that can prevent the malfunction of the memory device by improving the sensing margin of the flash-type semiconductor memory device having an overlapping bit line structure Its purpose is to.

1 is a schematic view showing the configuration of a conventional nonvolatile semiconductor memory device;

2 is a circuit diagram schematically showing the configuration of a conventional reference voltage generator;

3 is a diagram illustrating a sensing margin at the time of reading of the nonvolatile semiconductor memory device of FIG. 1;

4A through 4B are diagrams illustrating a sensing margin during program verification of the nonvolatile semiconductor memory device of FIG. 1;

5 is a schematic view of a configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention;

6 is a circuit diagram schematically showing the configuration of a reference voltage generator according to an embodiment of the present invention;

FIG. 7 is a view illustrating a sensing margin at read time of the nonvolatile semiconductor memory device of FIG. 4; FIG.

* Explanation of symbols on the main parts of the drawing

10, 20: reference cell array 12, 18: cell array

14: upper page buffer 16: lower page buffer

22, 28: reference voltage generator 24, 26: low decoder

(Configuration)

According to an aspect of the present invention for achieving the above object, in the nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device, at least two generating a reference voltage in response to a predetermined signal applied from the outside The above reference voltage generator; A voltage value of a reference cell string located closest to a selected cell string among the two or more reference cell arrays, including at least two reference cell arrays receiving respective reference voltages from the at least two reference voltage generators Is sensed as the reference voltage.

In this apparatus, the reference voltage generator comprises: an orgate for receiving a predetermined signal from the outside; An AND gate having one input terminal connected to an output terminal of the or gate and a type force terminal receiving an address signal from the outside; A first MOS transistor having a gate terminal connected to an output terminal of the AND gate and a source terminal grounded; A second MOS transistor having a source terminal connected to a drain terminal of the first MOS transistor; A first resistor connected in series between the output terminal of the AND gate and the drain terminal of the second MOS transistor; A second resistor connected between the output terminal of the AND gate and the first resistor; A gate terminal is connected to the drain terminal of the second MOS transistor, a drain terminal is connected to the drain terminal of the first MOS transistor, and a source terminal includes a third MOS transistor connected to the gate terminal of the second MOS transistor. .

In this apparatus, the first and second MOS transistors are N-channel conductive MOS transistors, and the third MOS transistor is a P-channel conductive MOS transistor.

(Action)

By such a device, it is possible to prevent the under-program phenomenon caused by recognizing that the program is completed during the program operation and the over-program phenomenon caused by continuously performing the program operation. Therefore, the nonvolatile semiconductor memory device malfunctions. Can solve the problem.

(Example)

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail based on attached drawing FIG.

Referring to FIG. 5, a nonvolatile semiconductor memory device according to a preferred embodiment of the present invention may include at least two reference voltage generators generating a reference voltage in response to a predetermined signal applied from the outside; A voltage value of a reference cell string located closest to a selected cell string among the two or more reference cell arrays, including at least two reference cell arrays receiving respective reference voltages from the at least two reference voltage generators Is sensed as the reference voltage. Such a device can solve the problem that the nonvolatile semiconductor memory device malfunctions.

In FIGS. 5 to 7, the same reference numerals are given to components that perform the same functions as those of the nonvolatile semiconductor memory device illustrated in FIGS. 1 to 4.

5 schematically illustrates a configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 5, in the nonvolatile semiconductor memory device according to the embodiment of the present invention, cell arrays 12b and 18a are formed at both sides of the upper page buffer 14 and the lower page buffer 16, respectively. The cell arrays 12b and 18a are connected to row address decoders 24b and 26a that receive address signals from the outside. Reference cell arrays 10b and 20a are formed at both sides of the cell arrays 12b and 18a to receive reference voltages Vref generated from the reference voltage generators 22b and 28a, respectively.

In addition, different cell arrays 12a and 18b are formed on both sides of the reference cell arrays 10b and 20a, and different reference cell arrays 10a and 20b are formed on both sides of the other cell arrays 12a and 18b. Similarly, the other cell arrays 12a and 18b are connected to row address decoders 24a and 26b receiving an address signal from an external source, and the other reference cell arrays 10a and 20b are connected to other reference voltage generators. 22a, 28b).

Here, referring to FIG. 6, the reference voltage generators 22a, 22b, 28a, and 28b according to the embodiment of the present invention may include an orgate 30 that receives a read signal Oread and a program verify signal Opgmvf from an external source. ), One input terminal is connected to the output terminal of the or gate 30, the other input terminal is an AND gate 31 that receives the address signal (x0) from the outside, and the gate terminal is connected to the output terminal of the AND gate 31; A first N-type MOS transistor 32 connected with a source terminal grounded, a second N-type MOS transistor 34 with a source terminal connected to a drain terminal of the first N-type transistor, and the second N First and second resistors 36 and 38 connected in series between the drain terminal of the type Morse transistor 34 and the output terminal of the AND gate 31, and the second N-type Morse transistor 34 and the first resistor ( The gate terminal is connected between 36), and the drain terminal is The P-type MOS transistor 40 is connected to the drain terminal of the first N-type MOS transistor, and the source terminal is connected to the gate terminal of the second N-type MOS transistor.

The operation of the nonvolatile semiconductor memory device having the configuration as described above is as follows.

First, in a nonvolatile semiconductor memory device according to an embodiment of the present invention, a plurality of reference cell strings are positioned in a BL, and a reference cell string of a closest side according to a position of a selected cell string (which is appropriately developed according to a position) Is set to the degree to which) will be detected based on this.

In other words, as shown in FIG. 5, 256 blocks far from the page buffer and 256 blocks close to the page buffer are distinguished among the x-addresses (for example, if there are nine addresses for distinguishing 512 blocks (cell strings)). Assume that the address to be x0.

This address is input together to the enable signal of a reference voltage generator (upper reference voltage generator) that generates a reference voltage signal (vref) for a conventional reference cell and is selected when one cell string of the upper 256 blocks is selected. Enable to form a reference BL level (which can be adjusted to suit the width or length of the reference cell transistor to match the 'on' / 'off' margins of the upper 256 cell strings, or by adjusting the reference voltage upper level appropriately). By inputting the x0 # signal to the enable signal of the lower reference voltage generator (Vref-bottom), it can be implemented by disabling the upper 256 block selection.

Similarly, in the opposite case, when selecting one cell string of the lower 256 blocks, on the contrary, an improved sensing margin is achieved by selecting the reference cell string appropriately set to the lower 256 blocks of the cell string by invoking the x0 # signal. You will get

As described above, by forming a plurality of (n) reference cell strings, an improved sensing margin of n times can be obtained and the program can be prevented from being over or under programmed.

Claims (3)

In a nonvolatile semiconductor memory device, The nonvolatile semiconductor memory device may include at least two reference voltages 10a and 10b for generating a reference voltage Vref in response to a predetermined signal applied from the outside; The at least two reference cells including at least two reference cell arrays 12a and 12b receiving respective reference voltages Vref-top and Vref-bottom from the at least two reference voltages 10a and 10b. Non-volatile semiconductor memory device, characterized in that for sensing the voltage value of the reference cell string located closest to the selected cell string of the cell array (12a, 12b) as a reference voltage. The method of claim 1, The reference voltage generators 10a and 10b may include an orgate 30 to which a predetermined signal (Oread, Orgmvf) is applied from the outside; An AND gate 31 having one input terminal connected to an output terminal of the or gate 30 and a type force terminal receiving an address signal x0 from the outside; A first MOS transistor 32 having a gate terminal connected to an output terminal of the AND gate 31 and a source terminal grounded; A second MOS transistor 34 having a source terminal connected to the drain terminal of the first MOS transistor 32; A first resistor (36) connected in series between the output terminal of the AND gate (31) and the drain terminal of the second MOS transistor (34); A second resistor (38) connected between the output terminal of the AND gate (31) and the first resistor (36); A gate terminal is connected to the drain terminal of the second MOS transistor 34, a drain terminal is connected to the drain terminal of the first MOS transistor 32, and a source terminal is connected to the gate terminal of the second MOS transistor 34. And a third MOS transistor (40) connected to the nonvolatile semiconductor memory device. The method of claim 2, And the first and second MOS transistors (32, 34) are N-channel conductive MOS transistors, and the third MOS transistor (40) is a P-channel conductive MOS transistor.