KR19980046010A - Capacitor Formation Method for DRAM Device - Google Patents

Abstract

The present invention discloses a method of forming a capacitor of a DRAM device capable of increasing DRAM capacity. The disclosed invention comprises the steps of forming an insulating film on top of a semiconductor substrate provided with a transistor; Forming a contact hole to expose one of the junction regions of the transistor; Forming a storage node electrode having a curvature on the surface; Forming a dielectric layer on the storage node electrode and the insulating layer; And forming a plate electrode over the dielectric layer.

Description

Capacitor Formation Method

The present invention relates to a method of forming a capacitor of a DRAM device, and more particularly to a method of forming a capacitor of the DRAM for increasing the capacity of the DRAM.

In general, DRAM devices are organized in a matrix form and are called along rows and columns to memory or play data. In particular, a compact memory element has one capacitor and one transistor, which acts as a switch to transfer or call the capacitor. In this case, when the metal oxide semiconductor (MOS) capacitor is used, the information needs to be periodically refreshed because the charge is discharged within a predetermined time. Although additional circuitry is required for this recharging, the DRAM is small enough to have millions of memory cells in a single chip and has low power consumption, making it a very popular device in current integrated circuits. This configuration DRAM must increase the surface area of the capacitor included in the DRAM as is known in order to increase its capacity (Capacitance = ε A / d, ε: dielectric constant, A: surface area of the electrode d: distance between electrodes).

As shown in FIG. 1, a capacitor of a conventional DRAM for securing a large capacity includes an insulating film 3 to electrically isolate a transistor between a transistor and a capacitor to be formed later on a semiconductor substrate on which a transistor (not shown) is formed. ) Is formed, and then the insulating film is partially etched to expose the source region 2 of the transistor under the insulating film.

Then, a polysilicon film for storage node electrodes is deposited on the resultant to a thickness such that it is in contact with the source electrode, and a predetermined portion is patterned to form the storage node electrode 4. Then, a dielectric film 5, for example, a high dielectric constant film such as oxide-nitride-oxde (ONO) is deposited on the storage node electrode 4 and the insulating film 3 in a thin thickness, and then the dielectric film 5 The plate electrode 6 is formed on the upper side of the circuit board, so that the capacitor 7 is formed.

However, the DRAM capacitor of the conventional method as described above has a problem that is difficult to apply to the current 16M or 64M DRAM collection that requires a large capacity.

Furthermore, after the DRAM element is formed, about 200 fC of charge is generated in the semiconductor substrate by α particles radiated from heavy metals (UTh, etc.) included in the subsequent packaging process, which is a noise, and thus a highly reliable DRAM In order to form, it is necessary to secure a charge storage capacity of 200 fC or more.

Accordingly, an object of the present invention is to provide a method for forming a capacitor of a DRAM device capable of conserving a capacitor capacity even in the scattering of α particles and ensuring a large capacity in a fine cell.

1 is a cross-sectional view of a capacitor of a DRAM element for explaining a method of forming a capacitor of a conventional DRAM element.

2A and 2B are cross-sectional views of a process sequence for explaining a method of forming a capacitor of a DRAM device according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

11: semiconductor substrate 12: source region

13: insulating film 14-1: first polysilicon film

14-2: second polysilicon film 15: storage node electrode

16: dielectric film 17: plate electrode

In order to achieve the above object of the present invention, the present invention comprises the steps of forming an insulating film on the semiconductor substrate with a transistor; Forming a contact hole to expose one of the junction regions of the transistor; Forming a storage node electrode having a curvature on the surface; Forming a dielectric layer on the storage node electrode and the insulating layer; And forming a plate electrode over the dielectric layer.

According to the present invention, in order to increase the surface area of the storage node electrode during the capacitor formation step of the DRAM element, the surface of the storage node electrode is increased by increasing the surface area of the storage node electrode to secure the capacity of the DRAM element.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A and 2B are cross-sectional views of a process sequence for explaining a method of forming a capacitor of a DRAM device according to an embodiment of the present invention.

First, as shown in FIG. 2A, an insulating film 13 is deposited on the semiconductor substrate 11 provided with a transistor (not shown). The insulating film 13 serves to insulate the transistor between the lower transistor and the capacitor to be formed later. The insulating layer 13 is partially etched to expose one of the junction regions of the transistor, for example, the source region 12, so that a contact hole (not shown) is formed. Subsequently, the first polysilicon film 14-1 for the storage node electrode is deposited to contact the source region 12 in the contact hole. At this time, the first polysilicon film 14 is deposited within 596 to 670 ° C as is known. Then, without breaking the vacuum, the deposition temperature is raised to about 690 to 710 ° C., and then the second polysilicon film 14-2 for the storage node electrode is deposited. At this time, since the second polysilicon film 14-2 is formed relatively thinner than the first polysilicon film 14-1 and is deposited at an elevated temperature, the grains have a columnar shape, and thus the second polysilicon film 14-2 is formed. The surface of the polysilicon film 14-2 is curved.

Thereafter, as shown in FIG. 2B, the first polysilicon film 14-1 and the second polysilicon film 14-2 for the storage node are patterned to a predetermined size to form the storage node electrode 15. . Subsequently, a dielectric constant 16 having a high dielectric constant, such as an ONO film, is evenly deposited on the resultant, and a plate electrode 17 is formed on the dielectric film 16 to form a capacitor of the DRAM device.

As described in detail above, according to the present invention, in order to increase the surface area of the storage node electrode during the capacitor formation process of the DRAM device, the surface of the storage node electrode is increased by treating the electrode surface to have a bend, thereby increasing the surface area of the DRAM device. The capacity of is secured.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (5)

Forming an insulating film on the semiconductor substrate including the transistor; Forming a contact hole to expose one of the junction regions of the transistor; Forming a storage node electrode having a curvature on the surface; Forming a dielectric layer on the storage node electrode and the insulating layer; And forming a plate electrode on the dielectric layer. The method of claim 1, wherein forming the storage node electrode comprises: forming a first polysilicon layer to be in contact with the junction region; Forming a second polysilicon film having a surface curvature on the first polysilicon film; Patterning the first polysilicon film and the second polysilicon film; and forming a capacitor of a DRAM device. 3. The method of claim 1, wherein the first polysilicon film is deposited at a temperature of 595 to 670 ° C. 4. 3. The method of claim 1, wherein the second polysilicon film having surface curvature is deposited to have a column or grain at a temperature range of 690 to 710 ° C. 4. The method of claim 1, wherein the dielectric film is an ONO film.