KR19980044701A - Interface circuit - Google Patents

Abstract

The present invention relates to an interface circuit, comprising: receiving a data register for temporarily storing input data, an address register for temporarily storing the input address, and an address stored in the addressless register as an input to determine an internal register for storing the data; And an internal register selection circuit configured to receive data stored in the data register as an input and transfer the data stored in the data register to the internal register, and write to the internal register selection circuit to output the data stored in the data register and the address stored in the address register. A synchronization configured to receive an enable signal and a clock signal as inputs, synchronize the write enable signal and the clock signal, and then transfer the synchronized signal to the data register and the address register; A circuit to provide the effect of setup / hold timing and the timing of the write enable signal so as to suppress the error in the signal output operation to occur is not consistent.

Description

Interface circuit

1 is a block diagram showing a conventional interface circuit.

2 is a timing chart showing the operation of a conventional interface circuit.

3 is a block diagram showing an interface circuit of the present invention.

4 is a logic circuit diagram illustrating a synchronization circuit of the present invention.

5 is a timing chart showing the operation of the synchronization circuit of the present invention.

* Description of the symbols for the main parts of the drawings *

110, 210: Data register 120, 220: Address register

130, 230: internal register selection circuit 140, 240: internal register

310, 320, 330, 340: D flip-flop AND: AND gate

INV: Inverter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit. In particular, the write enable signal and the clock signal for determining the data input / output timing of a temporary register are synchronized with each other so as to prevent an error caused by a timing mismatch between the write enable signal and the clock signal. Relates to an interface circuit.

A general interface circuit is described with reference to FIG. 1 as follows.

1 is a block diagram showing a conventional interface circuit.

As shown in FIG. 1, the data register 110 is connected to receive externally input data and temporarily store it, and the address register 120 is connected to receive externally input address and temporarily store it. do.

The data register 110 and the address register 120 are connected such that a clock signal CLK is inputted so that input and output timings of data and addresses are synchronized.

In addition, the data register 110 and the address register 120 are connected so that a write enable signal / WR instructing to output a temporarily stored value is input.

The data output from the data register 110 and the address output from the address register 120 are connected to be input to the internal register selection circuit 130.

A plurality of signals output from the internal register selection circuit 130 are connected such that each signal is input to the corresponding internal register 140.

When the address input to the internal register selection circuit 130 is n bits, the number of internal registers 140 provided is 2 ⁿ .

The operation of the conventional interface circuit configured as described above will be described with reference to FIG.

2 is a timing chart showing the operation of the conventional interface circuit.

Data is input and stored in the data register 110, and a unique address of the data stored in the data register 110 is input and stored in the address register 120.

At this time, if the write enable signal / WR is input to the data register 110 and the address register 120 and instructed to output the stored value to the internal register selection circuit 130, it is synchronized to the rising edge of the clock signal CLK. Data and address are output.

The internal register selection circuit 130 decodes the input address, and selects the internal register 140 to store the input data from among a plurality of internal registers 140 provided according to the decoding result to select the data. Output

Data output from the internal register selection circuit 130 is input to and stored in the corresponding internal register 140.

In the conventional interface circuit operating as described above, the input timing of the write enable signal / WR input to the data register 110 and the address register 120 does not necessarily match the input timing of the clock signal CLK. The case occurs.

In general, the output timing is determined by a clock signal, which is a reference signal. There is a setup time for deciding an output signal before a state change of the clock signal, and a hold for maintaining the determined output signal after the change of the clock signal. hold) There is time.

In FIG. 2, the section denoted by the quotation marks t represents the setup / hold time.

Data determined by such a setup / hold operation is generally output by an output indication signal.

Since the output signals at the front and rear ends of the determined output signals are out of the range of the setup / hold time, they are invalid signals that are not valid signals to be output by the reference signals.

In view of this fact, the above-described conventional interface circuit is designed that the data or address determined at the setup time is output by the write enable signal (/ WR), and the output data or address signal must be maintained for the hold time. Nevertheless, there is a serious error in the input / output operation of the interface circuit such that the setup / hold time of the clock signal CLK does not coincide with the timing of the write enable signal / WR, so that an invalid signal is output instead of a valid valid output signal. It has the potential to occur.

That is, in FIG. 2, since the write enable signal / WR is enabled before the clock signal CLK, an invalid signal before the setup operation is output is output.

Accordingly, an object of the present invention is to synchronize the clock enable signal with the clock enable signal and then to the data register and the address register so that the correct signal is output from the data register and the address register so that the setup / hold timing and the write enable signal can be controlled. The reason for this is to suppress errors in signal output operation caused by timing mismatch.

The present invention for this purpose is to determine the data register for temporarily storing the input data, the address register for temporarily storing the input address, and the internal register to store the data by receiving the address stored in the address register as input An internal register selection circuit configured to receive data stored in a register as an input and transfer the data stored in the register to the internal register, a write enable signal instructing the internal register selection circuit to output data stored in the data register and an address stored in the address register; A synchronization circuit configured to receive a clock signal as an input, to synchronize the write enable signal and the clock signal, and then transfer the synchronized signal to the data register and the address register; The lure is.

An embodiment of the present invention made as described above will be described with reference to FIGS. 3 to 5 as follows.

3 is a block diagram showing an interface circuit of the present invention.

As shown in FIG. 3, the data register 210 is connected to receive externally input data as an input and temporarily store it, and the address register 220 is connected to receive an externally input address as an input and temporarily store it. do.

In addition, the synchronization circuit 300 is connected such that a write enable signal / WR for instructing to output a value temporarily stored in the data register 210 and the address register 220 is input.

The synchronization signal SYNC output from the synchronization circuit 300 is connected to be input to the data register 210 and the address register 220, respectively.

The clock register CLK is connected to the data register 210, the address register 220, and the synchronization circuit 300 such that input / output timings of data and addresses are synchronized.

The address output from the data address register 220 output from the data register 210 is connected to be input to the internal register selection circuit 230.

A plurality of signals output from the internal register selection circuit 230 are connected such that each signal is input to the corresponding internal register 240.

When the address input to the internal register selection circuit 230 is n bits, the number of internal registers 240 provided is 2 ⁿ .

4 is a logic circuit diagram showing a synchronization circuit of the interface circuit of the present invention.

As shown in FIG. 4, the write enable signal / WR is connected to the D flip-flop 310, and the output of the de- flip-flop 320 is output to the de flip-flop 320. The signal Q1 is connected to be input, and the de flip-flop 330 is connected to receive the output signal Q2 of the de flip-flop 320.

The output signal / Q3 of the de flip-flop 330 is an inverted signal of the output signal Q2 of the de flip-flop 320.

The output signal / Q3 of the flip-flop 330 and the output signal Q2 of the flip-flop 320 are connected to the AND gate AND.

The output signal A of the AND gate AND is connected to be input to the de flip-flop 340, and the signal output from the de flip-flop 340 is a synchronization signal SYNC that is an output signal of the synchronization circuit 300. .

The clock signal CLK is connected to the de-flop flops 310, 320, and 330, and the clock signal CLK is connected to the de-flip flop 340 so as to be inverted and input by the inverter INV.

The operation of the synchronization circuit 300 of the present invention configured as described above will be described with reference to FIG.

5 is a timing chart showing the operation of the synchronization circuit 300 of the present invention.

When the write enable signal / WR activated at the low level without being synchronized with the clock signal CLK is input to the de-flip-flop 310, the first clock input after the write enable signal / WR is inputted. In 1), the output of the low level signal Q1 of the de flip-flop 310 is performed.

If the write enable signal / WR is deactivated to a high level after the second clock input 2, the output signal Q1 of the de-flip flop 310 is generated immediately after the write enable signal / WR is deactivated. The clock input 3 outputs a high level signal.

Therefore, the input / output of the signal of the de-flip-flop 320 is delayed by one clock signal CLK rather than the input / output timing of the signal of the de-flip-flop 310.

That is, the input of the signal of the de-flop 320 is made at the second clock input 2 after the write enable signal / WR is input, and the output of the signal is made at the fourth clock input 4.

Similarly, the input / output of the signal of the de-flip-flop 330 is also delayed by one clock signal CLK from the input / output timing of the signal of the de-flip-flop 320, and the output signal Q3 of the de-flip-flop 330 is Has the inverted phase of the output signal of the de-flop flop 320.

The output signals Q2 and Q3 of the de-flip-flops 320 and 330 are input to the AND gate AND, respectively, but the output signal Q2 of the de-flip-flop 320 is de-flip in the input timing. Since the output signal A of the AND gate AND is the output signal Q2 of the de-flip-flop 320 and the de-flip-flop (1) since the clock signal CLK of one cycle is faster than the output signal Q3 of 330. The output signal Q3 of the 330 becomes a high level only for one period of the fourth clock input 4, which is a period where all of the output signals Q3 become a high level.

As such, the high level signal output from the AND gate AND is input to the de-flip-flop 340 so as to have a high level section equal to one cycle of the clock signal CLK at the falling edge of the fourth clock input 4. do.

In this case, the timing at which the signal is output from the de-flip-flop 340 is performed at the falling edge of the fourth clock input 4. This is because the falling edge of the fourth clock input 4 is inverted to the rising edge when the falling edge of the fourth clock input 4 is input to the flip-flop 340.

As can be seen from the foregoing, the write enable signal / WR input without being synchronized with the timing of the clock signal CLK is synchronized with the clock signal CLK through the synchronization circuit 300 of the present invention. It is output as a signal SYNC.

The synchronization signal SYNC is input to the data register 210 and the address register 220, respectively, so that the data or address synchronized with the clock signal CLK is output.

Therefore, in the present invention, the write enable signal is synchronized with the clock signal and then inputted to the data register and the address register so that the correct signal is output from the data register and the address register so that the setup / hold timing and the timing of the write enable signal are improved. There is an effect to suppress the error of the signal output operation caused by a mismatch.

Claims (5)

A data register for temporarily storing the input data, an address register for temporarily storing the input address, and an address stored in the address register are received as inputs to determine an internal register for storing the data, and then the data stored in the data register is input. A data input / output interface circuit comprising an internal register selection circuit adapted to receive and transfer the internal register, The write enable signal and the clock signal are input to receive the data stored in the data register and the address stored in the address register to the internal register selection circuit, and receive the write enable signal and the clock signal. And a synchronization circuit for synchronizing and then transferring the synchronized signal to the data register and the address register. The method of claim 1, wherein the synchronization circuit, A first flip-flop connected to a data input terminal so that the write enable signal is input, and outputting data in synchronization with the clock signal; A second flip-flop that receives the output data of the first flip-flop as an input and outputs data in synchronization with the clock signal; A third flip-flop that receives the output data of the second flip-flop as an input and outputs data in synchronization with the clock signal; A logic gate which receives the output data of the second flip-flop and the output data of the third flip-flop as inputs and performs a logical sum operation; A fourth flip-flop that receives the output data of the logic gate as an input and outputs data in synchronization with an inverted signal of the clock signal; And an inverter for inverting a clock signal input to the fourth flip flop. The method of claim 2, And the first flip-flop, the second flip-flop, the third flip-flop, and the fourth flip-flop are D flip-flops. The method of claim 2, And the output data of the third flip-flop is inverted data of data transferred from the second flip-flop. The method of claim 2, And the logic gate is an AND gate.