KR19980037107A - Spatial switching device capable of switching mixed signals of dependent signals (TU) 12 and 11 - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

A spatial switching device capable of switching a mixed signal of the dependent signals (TU) 12 and 11.

2. The technical problem to be solved by the invention

Added space switch function of TU11 unit to space switch function of TU12 unit, and facilitates wiring and layout during chip fabrication.

3. Summary of Solution to Invention

The switching means includes an input stage switching means for verifying transmission error of input data, multiplexing means for selecting a plurality of data output from the input stage switching means, and an output stage switching for inserting and outputting a BIP to data output from the multiplexing means. A timing generation means for receiving a system clock and a frame clock and outputting various timing signals for various control; and a TU (Tributary Unit) 12/11 data of a specific bus using asynchronous connection matrix storage means and multiplexing means. Means connected to the central processing unit to output the.

4. Important uses of the invention

Used for switching device of transmission device.

Description

Spatial switching device capable of switching mixed signals of dependent signals (TU) 12 and 11

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spatial switching device that performs spatial position shift of data. In particular, when a tributary unit (TU) 12 and a TU11 signal are mixed using an extended 3-port asynchronous memory (RAM) and a multiplexing device. The present invention relates to a spatial switching device capable of performing spatial position shift.

In general, a switching function in a communication network is a function widely used in a transmission device as well as an exchange. In order to perform such a switching function, the analog relay used in the past performs a switching function using a digital memory.

Recently, due to the rapid development of integrated circuits, large-capacity switches have been converted into specific-purpose integrated circuits (ASICs), and general switches are divided into time switches that change the position of data in time and spatial switches that perform spatial position movement. In general, most switch networks have a time / space / time multi-stage structure that applies them together.

In the switch network of the TU12 and TU11 mixed unit to which the present invention is applied, it is designed based on the concept that there is no complete blocking that can be switched without rearranging the switching paths that are already in service during congestion.

In the conventional space switch having such a characteristic, it is difficult to integrate a large-scale / integrated system by using a latch or flip-flop, and the like, and in particular, there are more than 1500 corresponding channels such as a TU12 and TU11 mixed unit space switch to which the present invention is applied. Not only is it impossible to implement at the current ASIC design and manufacturing level, but even if the memory is used, it is not easy to simultaneously connect the external central processing unit (CPU) and the multiplexing device.

In addition, when designing with a certain logic, a large amount of nets are generated, which places a lot of constraints on layout and layout, and it is difficult to duplicate the connection matrix memory itself.

Accordingly, in order to overcome and solve these problems, the present inventors have applied for a TU12 unit space switching device using 3-port asynchronous RAM (MUX) and MUX (Patent No. 53997) filed in 1995. I have suggested.

However, looking at the synchronous digital hierachy (SDH) hierarchy used, not only TU12 unit signals but also TU11 unit signals are widely used in existing transmission networks.

Therefore, in a network using only TU12 signals, the proposed TU12 spatial switching device may be used, but the TU12 dedicated switching technology cannot be used when TU12 signals as well as TU12 signals are mixed.

In addition, although wiring is easy using memory, current ASIC manufacturing technology is limited by the number of memory, which has the problem of reducing the number of memory used as much as possible.

Accordingly, the present invention devised to overcome the above-mentioned problems of the prior art is a low-bus (Low) bus, which is a connection standard in a low-speed broadband digital cross-switch signal of the unit of TU11 and TU12 based on synchronous digital layer (SDH) LTU), even if they are mixed in units of TU groups, expands three-port asynchronous memory, adds the space switch function of TU11 unit to the space switch function of TU12 unit already proposed using appropriate control algorithm, and is used separately. It is an object of the present invention to provide a space switching device in which two memories are used as one memory having a double capacity to facilitate wiring and arrangement during chip fabrication.

1 is an overall configuration diagram of a switching network to which the present invention is applied;

2 is a block diagram of an input / output signal according to the present invention;

3 is a configuration diagram of mixed signals of TU11 and TU12 signals in an input / output signal according to the present invention;

4 is a block diagram of an embodiment of a space switching device according to the present invention;

5 is a connection relationship diagram of a connection matrix memory according to the present invention;

6 is a structural diagram of a connection matrix memory according to the present invention;

* Explanation of symbols for main parts of the drawings

410: low speed bus (LBUS) 411: input stage switching unit

412,432: multiplexer 413: output stage switching unit

420: timing generator 430: CPU connection unit

431: 3-port asynchronous memory 433: CPU read port

The present invention for achieving the above object is, timing generation means for receiving a frame clock and a system clock to generate a control signal for switching and a signal indicating a fixed dummy position and a signal for reading the address for multiplexing, and the timing It is connected to a plurality of switching means for performing an error of input data under the control of the generating means and performing spatial switching, and a central processing unit (CPU), and receives an address from the central processing unit from the central processing unit. CPU connection means for storing the input data or outputting the stored data, and outputting a selection signal for multiplexing under the control of the timing generating means, wherein the switching means includes one frame of data input according to a system clock. Input switching means for verifying a transmission error for A multiplexing means for selecting and outputting data except for a fixed pile among a plurality of data outputted from the input stage switching means by a call, and retiming the data output from the multiplexing means, and detecting a transmission error at a next stage. And an output stage switching means for calculating and inserting a bit interleaved parity (BIP) for a frame so that the CPU connection means is controlled by a CPU to store and output an address, and under the control of the timing generation means. And three port asynchronous storage means for outputting an address for use as the selection signal of the multiplexing means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

FIG. 1 is a schematic diagram of a switch network to which the present invention is applied. The switch network does not have a blocking probability of TU12 units 5544 X 5544 and TU11 units 7392 X 7392 using the time switches 1 and 3 and the space switch 2. Indicates.

As shown in the figure, the front-end time switch 1 inputs 252 TU12 unit signals and 336 TU11 unit signals and spatially expands them so that there is no blocking probability. Is output.

Therefore, the space switch 2 collects and switches the low speed bus BUS from the front end time switch 1 for each output line, and is doubled as work and protection, and the back end time switch 3 In the reverse process of the shear time switch (1). One back-end time switch 3 receives data through four LBUSs and performs TU12 unit 504 X 252 and TU11 unit 672 X 336 switching.

2 is a block diagram of an input / output signal corresponding to a low speed bus that is a connection signal used in the switch network of FIG. 1.

The low-speed bus (LBUS) is based on 38M, and a simple two-minute 19M is also used as the low-speed bus (LBUS). In terms of 38M, it is synchronized with the clock generated by simply dividing the 155.520M class signal, which is a STM-1 (Synchronous Transfer Mode-1) signal, and 12 fixed piles (LBUS) (for 38M) There are a fixed dummy 21 and six pseudo dummy 22. Therefore, when combined with 126 TU12 channels and 168 TU11 channels, it appears that there are 12 fixed piles, 132 TU12 channels, and 180 TU11 channels.

In addition, since the 19M low speed bus is simply divided into two at 38M, it has six fixed piles 23 and three pseudo piles 24.

FIG. 3 is a configuration diagram of the TU11 and 12 signals in the input / output signal of FIG. 2 and shows 6.48M frames in three units of an AU (Administration Unit). 19M, or STM-1, can be multiplexed three times, and two STM-1 capacities can be multiplexed six times.

FIG. 4 is a block diagram of an embodiment of a spatial switching device for switching dependent signals in a case where TU12 and TU11 signals are mixed according to the present invention. In the drawing, 410 is a low speed bus, 411 is an input stage switching unit, and 412 and 432 are multiplexed. 413 denotes an output stage switching unit, 420 denotes a timing generator, 430 denotes a central processing unit (CPU) connection unit, 431 denotes a 3-port asynchronous memory, and 433 denotes a CPU read port.

As shown in the figure, there are twelve low-speed buses 410, which are sub-switch blocks, which are composed of an input stage switching unit 411, a multiplexing unit 412, and an output stage switching unit 413.

First, the input stage switching unit 411 calculates a bit interleaved parity (BIP) value for one frame during the frame clock 2K, and extracts the BIP value received from the front end to verify the transmission error at the front end. After comparing the extracted value with the extracted BIP value, the calculated BIP value is accumulated. The bytes used at this time use one byte of the fixed dummy. The 38M system clock is used as a single clock.

The multiplexer 412 receives data from the 12 input stage switching units 411 and performs a space switching function except for 12 fixed piles per 72K. Since the corresponding slots are allocated so that they do not have the same output port in the time slots, 12 12 multiplexers are required.

The output stage switching unit 413 retimes the data output from the multiplexing unit 412 to 38M level to receive stable data, and to generate a BIP for one frame during the frame clock 2K so as to detect a transmission error in the next stage ASIC. Calculate and insert. Inserted bytes also use a fixed stack.

The timing generator 420 receives the 38M clock and the 2K frame clock to generate timing signals such as 19M, 72K clock, fixed dummy position, and multiplexing control.

The CPU connection unit 430 includes a three-port asynchronous memory 431 of the connection matrix memory 528X8, a 2: 1 multiplexer 432, and a CPU read port 433, which are three ports of the three-port asynchronous memory 431. Means write port 1 port, read port 2 port, and write and read ports are connected to an external CPU port, and the remaining read ports are read from the timing generator 420 in 38M units to read the read address in the multiplexer 412. It is used to output TU12 and TU11 data of a specific bus by outputting it to the selection terminal of).

In addition, the CPU connection unit 430 has two three-port asynchronous memory 431 and six 2: 1 multiplexer 432 for multiplexing them, so that CM-1 to CM-6 are generated as connection memory (CM) signals. do.

FIG. 5 is a diagram illustrating a configuration of a three-port asynchronous memory, which is the connection matrix memory of FIG. 4, in which 528 X 4 word memories A and B are configured as one 528 X 8 word memory. It represents the input source channel where the contents written to the memory will be output.

As shown in the figure, the three-port asynchronous memory (51, 52) is composed of three ports, one port receives the read address (raddr3) according to the read cycle (read cycle) from the CPU address bus address output terminal do3 It is used as a CPU read port to output an address.

When a write enable signal (WE) 1, 2 from the CPU read / write pin is selected and an address addr1 of a write cycle is input from the CPU address bus, a port is provided with the CPU data bus at the designated address. Used as a port to write data (di) input from.

The other port receives the read address raddr2 from the timing generator 420 in accordance with the 38M clock and is used to output data through the data output terminal do2.

The 2: 1 multiplexer 53 selects the do2 output of the three-port asynchronous memory 51 or the do3 output of the three-port asynchronous memory 52 according to the connection memory selection signal CM CHOICE. ) Signal is output to the multiplexer 412 via a main path.

Also, the 2: 1 multiplexer 54 multiplexes the do2 output of the three-port asynchronous memory 52 or the do3 output of the three-port asynchronous memory 51 according to the read / write selection signal R / W choice. The write signal is output to the CPU through the CPU read port 433.

FIG. 6 is a diagram illustrating a configuration of a 528 X 8 word memory, which is the concatenated matrix memory of FIG. 5, wherein a 4-bit 528 X 4 word memory A having a physical address of $ 0 to $ 527 and 4 bits of $ 528 to $ 1055. Instead of 528 X 4 word memory (B), it consists of 8-bit 528 X 8 word memory with physical addresses $ 0 to $ 527.

Here, the first four bits of the physical addresses $ 0 to $ 527 are the logical addresses $ 0 to $ 527, and the fourth four bits are the logical addresses $ 528 to $ 1055.

According to the characteristics of the present invention, when designing a connection matrix memory as a three-port memory, and if you want to change the value of the connection matrix by dual-structuring it, select another memory, change the value, and then do the actual switching. When the command is given to reflect the changed value of the connection matrix, the value can be changed at the appropriate timing.

Accordingly, except for the connection matrix memory, only the simple multiplexer 412 for performing the spatial movement of the input signal data needs to exist as many as the number of the input buses. The output of the dual-structured connection matrix memory is connected to the selection terminal of the multiplexer 412, and the low-speed bus (LBUS) 410 containing TU12 and TU11 data operates in units of 38M. After counting and extracting the corresponding address value, the spatial switching function can be performed.

Looking at the input signal processing process, the input data corresponding to the 38M low speed bus (LBUS) 410 is connected to the space switch, and 132 (126 pieces are TU12) in the connection signal low speed bus 410 (for 38M). There are 6 TU12 signals, 6 pseudopiles, 174 (168 TU11s, 6 pseudopiles), and 12 fixed piles.

In order to ensure the integrity of the bus, the input switch 411 of the switch ASIC performs bit interleaved parity (BIP) extraction and inspection, and the input data after the BIP processing has 132 TU12 channels, 174 including a fixed dummy. The multiplexer 412 is transmitted to the multiplexer 412 in units of TU11 channels.

In the multiplexer 412, there are 12 12: 1 multiplexers for spatially switching the TU12 and TU11 channels of the 12 input low-speed buses 410, and the output stage switching unit 413 transmits the signals at the front end of the next ASIC. The BIP is created and inserted to check for problems in the furnace.

As for the connection matrix memory, one connection matrix memory is required per low speed bus 410, so a total of 12 connection matrix memories are required, and the size of the memory is fixed in the low speed bus because TU11 and TU12 signals are mixed in the low speed bus. Except for the dummy, a combined capacity of 512 words is required, which is the sum of the mixed number of dependent signals TU1 and the pseudo pile.

In addition, since the size of the word is transmitted to the input of the 12: 1 multiplexer 412, 4 bits are required. That is, 12 512x4 bit memory is required, but the number of memory is restricted when wiring, so by using two 512x4 memory grouped into one 512x8 memory, the number of memory can be cut in half. By reducing the number of memories in half, there is no problem with the whole function and it becomes simpler in operation.

This concatenation matrix memory has a double buffer structure so that it can be safely executed even when the concatenation matrix value is changed. In particular, this asynchronous memory has three ports, which is divided into a port connected to a read process of an external CPU, a port connected to a write process, and a port connected to a multiplexer. The TU12 and TU11 unit space switches to which the present invention is applied are designed to perform a space switch function as much as 12 X 12 AU group capacity.

Looking at the switching scheme in the case where TU11 and TU12 are mixed using the hardware subblocks as described above, as shown in FIG. 3, if only a signal of TU12 unit exists in the low-speed bus, the same channel is formed for every 7 TU groups. The TU12 signal is repeated with a certain period.

In addition, even if only the TU11 unit signal exists, the same channel is formed for every seven TU groups, and the corresponding TU11 signal is repeated with a certain period.

However, if the TU11 signal and the TU12 signal are mixed differently for each TU group, there is no guarantee of the same TU data every 21st or every 28th as shown in FIG. That is, it can be seen that the repetition period is present variably between 21 and 28.

Therefore, if TU11 signal or TU12 signal is composed of only one type in the I / O bus, it is possible to use the same TU1 data existing in the bus at regular intervals, but if they are mixed, the repetition period is variable. Connection matrix memory as much as signal (TU1) data was prepared so that mixed TU11 and TU12 data could be switched under software control.

The present invention described above is capable of various substitutions, modifications, and changes within the scope without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and thus is limited to the above-described embodiments and drawings. It is not.

The present invention constructed and operated as described above provides a low-bus bus (LBUS) transmission error detection and three-port memory expansion and simple multiplexing in a spatial switch in a TU12 and TU11 signal unit using a low-speed bus (LBUS) 38M. It is possible to provide a space switch with a simple configuration even when the TU11 and TU12 signals are mixed using only the device.

In addition, it is possible to prevent the loss of switching data even when the switching is changed by preparing a dual structure of the connection matrix memory, and the switch basically includes a large number of nets, which makes it difficult to arrange and lay out the memory. By grouping the nets as much as possible, there is an effect that can prevent problems that may occur during layout (Layout).

In addition, it is possible to simplify the overall operation method by grouping the connection matrix memory used for the CPU connection, that is, converting a plurality of memory operations into one memory operation method.

Claims (3)

Timing generation means for receiving a frame clock and a system clock and generating a control signal for switching, a signal indicating a fixed dummy position, and a signal for reading an address for multiplexing; A plurality of switching means for checking whether or not an error of input data is controlled under the control of the timing generating means and performing spatial switching; It is connected to a central processing unit (CPU), receives an address from the central processing unit, stores the data input from the central processing unit or outputs the stored data, and outputs a selection signal for multiplexing by the control of the timing generating means. Provided with a CPU connection means, The switching means, Input stage switching means for verifying a transmission error for a frame of data input according to a system clock; Multiplexing means for selecting and outputting data except for a fixed pile from among a plurality of data outputted from the input stage switching means by the selection signal of the CPU connecting means, and An output stage switching means for retiming the data output from the multiplexing means and calculating and inserting a bit interleaved parity (BIP) for a frame so as to detect a transmission error at a next stage, The CPU connection means, A three-port asynchronous storage means for storing and outputting an address under control of a CPU, and outputting an address for use as a selection signal of the multiplexing means under control of the timing generating means; Device. The method of claim 1, The CPU connection means, The first read port and the write port are connected to the CPU to control the CPU, and the data is input and output, and the second read port is connected to the timing generating means to output data stored under the control of the timing generating means. 3-port asynchronous storage, A plurality of means having multiplexing means for selecting and outputting data output from the redundant three-port asynchronous storage means by means of a selection signal of the CPU; And a means for connecting with said CPU. The method of claim 2, The three port asynchronous storage means, Spatial switching device comprising a 528x8 size, divided into two 528x4 size memory area to store the physical address.