KR19980034160A - Nonvolatile Semiconductor Memory Device - Google Patents

Abstract

The present invention relates to a nonvolatile semiconductor memory device having lockable cells, and more particularly to a nonvolatile semiconductor memory device for preventing data stored in non-selectable lockable cells from being erased. Capacitors of desired predetermined values were formed on the pocket P-WELL and N-WELL regions of the semiconductor substrate in the word lines of the lockable cell unit arranged in parallel with each other. In addition, the minimum unit of lock and unlock is determined as a block, and word lines connected to the lockable cells are connected to one word line on the pocket P-WELL region or the N-WELL region. A capacitor having a predetermined predetermined value is formed on the word line on the pocket P-WELL region to the N-WELL region. The lockable cell passgate part is configured by one NMOS transistor to control the operation for locking and unlocking. As a result, an erase voltage may be prevented by increasing a voltage induced in word lines connected to unselected lockable cells during an unlock operation.

Description

Nonvolatile Semiconductor Memory Device

The present invention relates to a nonvolatile semiconductor memory device having lockable cells, and more particularly, to a nonvolatile semiconductor memory device for preventing data stored in non-selectable lockable cells from being erased.

In using a semiconductor memory device, a user who wants a semiconductor memory in which desired data remains intact under any circumstances (malfunction caused by noise, immature system use, POWER DOWN, etc.) after storing data in a specific area of the semiconductor memory device. These demands have led to a need for a method capable of preventing data destruction that may occur due to the above causes. For the same reason as described above, the memory cell array of the semiconductor memory device includes lockable cells corresponding to word line units (hereinafter referred to as page units) or block units (when several pages are grouped together and used as one division unit). In this case, information about a lock or unlock of the memory cell array is stored in each page or block unit.

A method of classifying memory cell arrays and storing information on lock or unlock by the above method is disclosed in Korean Patent Publication No. 1341, Publication No. 94-20426, Application No. 94-2159, and Patent No. A configuration of the lockable cell control method of the memory device and a lock and unlock control method for the lockable cell are described in detail. During the programming mode of the EEPROM, it often happens that a user wishes to protect it so that data written (or programmed) to a particular memory cell is not erased. For example, even when the erase operation is not performed, the memory device malfunctions due to a sudden change in the power supply voltage level or external noise, which causes the programmed data to be destroyed or erased. . Therefore, it is necessary to prevent the data from being destroyed due to a malfunction of the memory device. To this end, the recent EEPROM uses a lockable cell having an erase lock function to prevent the data of the selected memory cell from being destroyed.

1 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory device having lockable cells according to the prior art.

In the conventional nonvolatile semiconductor memory device, as shown in FIG. 1, the block select circuit 1, the pass gate unit 2, the memory cell array unit 3, the lockable cell unit 4, and the lockable cell path are shown. It consists of the gate part 5. The block selection circuit 1 outputs a page selection control signal PGATE, which is a predetermined control signal, to the pass gate unit 2. The memory cell array unit 3 includes a plurality of cell transistors M1n to M8n having a channel connected in series between the first select transistor S1n (where n is a positive integer) and the second select transistor G1n. It consists of a plurality of strings consisting of. A string select line SSL is commonly connected to each gate of each of the first selection transistors S1n, and bit lines BLn corresponding to respective drains are connected to each drain. The gate selection line GSL is commonly connected to each gate of each of the second selection transistors G1n, and the common source line CSL is connected to each source.

The lockable cell unit 4 is disposed between the first lockable select transistor S1n connected to the string select line SSL and the second lockable select transistor G1n connected to the ground select line GSL. The channel consists of a string consisting of a plurality of lockable cell transistors M1n-M8n connected in series. The pass gate unit 2 outputs page selection signals S1 to S8 in response to the page selection control signal PGATE output from the block selection circuit 1 in units of pages of the memory cell array unit 3. Transfer to each word line WL1-WL8. In addition, the lockable cell passgate unit 5 locks the lockable page selection signals LS1 to LS8 in response to the page selection control signal PGATE. Each word line LWL1 of the lockable cell unit 3 is stored. LWL8).

2 is a cross-sectional view taken along the word line of FIG. 1. FIG. 3 is an equivalent circuit diagram of the capacitive coupling based on the word line of the page unit shown in FIG. 2, and includes word lines WLi including the memory cell array unit 3 and the passgate unit 5. The capacitance capacitors for i = 1-8) are shown as Cp and Ca, respectively. The capacitor capacitors for the word lines LWLi including the lockable cell portion 4 and the lockable cell passgate portion 5 are shown as Cla and Clp, respectively.

4 is an operation timing diagram of a conventional nonvolatile semiconductor memory device. 1 to 4, the unlock operation in the conventional nonvolatile semiconductor memory device will be described. As shown in FIG. 4, when a SUNLOCK signal, which is a flag signal for an unlock operation, transitions to a high level, the semiconductor memory device performs an unlock operation. All of the page select signals S1-S8 for designating a predetermined page of the memory cell array unit 3 in synchronization with the SUNLOCK signal transitioned to the high level are transitioned to the high level. The page selection signal of the selected cell among the page selection signals LS1 to LS8 for selecting the page of the lockable cell unit 4 is maintained at a low level, and the page selection signals of the unselectable lockable cells are maintained. (LS0-LS8) all transition to a high level. At the same time, the string select signal line SSL and the ground select signal line GSL are also transitioned to the high level. In addition, the passgate control signal PGATE of the selected block output from the block selection circuit 1 is shifted to a high level so that the channels of the plurality of NMOS transistors SP1, MP1-MP8, and GP1 of the passgate unit 2 are transferred. This is conducting.

Voltages of (Vcc-1Vth) are respectively applied to the plurality of word lines WL1-WL8 of the memory cell array unit 3 through the pass gate unit 2. The word lines of the selected lockable cell transistors of the lockable cell unit 4 are charged with a voltage of 0 volts, and the word lines of the unselected lockable cell transistors are charged with a voltage of (Vcc-1Vth). Although not shown in the drawing, when the erase voltage pump circuit operates to pump the erase voltage Vera to a voltage of about 20 volts or more, the N-WELL region 7 and the pocket P-WELL region 8 shown in FIG. The erase voltage Vera of about 20V or more is charged. The plurality of word lines WL1 to WL8 of the memory cell array unit 3 and the plurality of word lines LWL1 to LWL8 corresponding to an unselected block of the lockable cell unit 4 are formed in the pocket P-WELL. The region 8 is boosted as it is charged with the erase voltage Vera.

At the same time, the plurality of transistors SP1, MP1-MP8, and GP1 of the passgate unit 2 and the unselected plurality of lockable cell transistors of the non-selectable lockable cell unit 4 are all shut off. off). Accordingly, due to the coupling ratio of the capacitors of the equivalent circuit diagram of FIG. 3, the plurality of word lines WL1 to WL8 included in the memory cell array unit 3 and the passgate unit 2 may have Vboost1 = [ Ca / (Ca + Cp) x (Vera + Vcc-1Vth) voltage is induced. At the same time, the plurality of word lines LW1 to LW8 corresponding to the unselected cells of the non-selectable lockable cell portion 4 and the non-selectable lockable cell passgate portion 5 are Vboost2 = [Cla / (Cla). + Clp) × (Vera + Vcc-1Vth) is induced. In addition, zero volts are maintained in the word lines LW1 to LW8 corresponding to the selected lockable cell transistors M1n to M8n of the lockable cell unit 4.

In the above operation, the selected cell transistors M1n to M8n of the lockable cell unit 4 typically satisfy a bulk erase condition in the nonvolatile semiconductor memory device. Therefore, all data stored in the lockable cell transistors M1n to M8n of the lockable cell unit 4 corresponding to the selected block are erased. Cell transistors M1n-M8n of the memory cell array unit 3 and word lines LWL1-LWL8 of unselected lockable cell transistors M1n-M8n of the unselectable lockable cell unit 4. The Vboost1 voltage and the Vboost2 voltage are derived, respectively. The voltage difference between the Vboost1 voltage and the Vboost2 voltage between the erase voltage Vera charged in the pocket P-WELL region 8 is sufficiently small that the erase condition for the cell is not satisfied. As a result, the cell transistors M1n-M8n of the memory cell array unit 3 and the unselected lockable cell transistors M1n-M8n of the unselectable lockable cell unit 4 are unlocked without being erased. The old data will be retained.

However, according to the nonvolatile semiconductor memory device described above, the voltage Vboost1 charged in the plurality of word lines WL1 to WL8 of the memory cell array unit 3 is high because the capacitor Ca is relatively large compared to the capacitor Cp. Voltage is induced. On the other hand, in the case of the lockable cell unit 4, since the capacitor Cla is smaller than the capacitor Clp, the Vboost2 voltages of the unselected word lines LWL1 to LWL8 of the unselectable lockable cell unit 4 are lower than the Vboost1 voltage. Voltage is induced. Accordingly, the voltage difference between the Vboost2 and the erase voltage Vera applied to the pocket P-WELL region 8 satisfies an erase condition, thereby unselecting the lockable cell transistors M1n to M8n of the lockable cell unit 4. There is a problem that erase stress (erase stress) that is erased in the data stored in the).

Accordingly, an object of the present invention has been proposed to solve the above-mentioned problems. Cell transistors of the unselectable lockable cell unit are connected by connecting a capacitor having a predetermined value between the word lines of the lockable cell unit and the well region of the semiconductor substrate. Disclosed is a nonvolatile semiconductor memory device capable of preventing an erase stress from erasing data stored in the memory.

Another object of the present invention is to solve the above-mentioned problems. The present invention is to provide a common connection of word lines of a lockable cell unit into one word line and a capacitor having a predetermined value between the common connected word line and a well region of a semiconductor substrate. The present invention provides a nonvolatile semiconductor memory device capable of preventing erasing stress in which data stored in cell transistors of an unselectable lockable cell unit is erased.

1 is a block diagram showing a schematic configuration of a conventional nonvolatile semiconductor memory device;

2 is a cross-sectional view showing a section cut in the word line direction of FIG.

3 shows an equivalent circuit of a capacitor viewed based on the word line of FIG.

4 is an operation timing diagram of an unlock operation of a conventional nonvolatile semiconductor memory device;

5 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating an equivalent circuit of a capacitor having a cross section taken along the word line of FIG. 5 based on a word line; FIG.

7 is an operation timing diagram during an unlock operation according to the present invention;

8 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to another embodiment of the present invention;

9 is an operation timing diagram during an unlock operation according to another embodiment of the present invention;

* Description of symbols on the main parts of the drawings *

1: Block selection circuit 2: Pass gate part

3: memory cell array section 4: lockable cell section

5: lockable cell pass gate part 9, 10: boosting means

According to one aspect of the present invention for achieving the above object, a memory cell array unit for storing data; A lockable cell unit having a plurality of lockable cells and a plurality of word lines corresponding thereto, the lockable cell unit for storing lock and unlock data for the memory cell array unit in units of pages and blocks; And boosting means for increasing a voltage level boosted on unselected word lines of the lockable cell unit.

In a preferred embodiment of the device, the boosting means comprises a plurality of capacitors each connected to word lines of the lockable cell portion.

In a preferred embodiment of the device, the voltage across each capacitor is boosted to unselected word lines of the lockable cell portion at a level lower than an erase voltage of a predetermined level.

According to another feature of the present invention, a plurality of strings in which a plurality of cell transistors are connected in series between a first select transistor and a second select transistor, each string selected line and each of the first select transistors A memory cell array unit having a ground selection line connected in common to each of the two selection transistors, and having a plurality of word lines corresponding to the plurality of cell transistors of each string; The plurality of lockable cell transistors may be formed of a string connected in series between a first passgate select transistor connected to the string select line and a second passgate select transistor connected to the ground select line. A lockable cell unit having word lines corresponding to the lock lines; Boosting means for increasing a voltage level boosted at each unselected word line of the lockable cell unit; And a lockable cell passgate unit configured to transmit a lockable page selection signal to the sub-putting means in response to a predetermined control signal.

In a preferred embodiment of the device, the boosting means is provided with a capacitor electrically connected to a word line to which a plurality of word lines of the lockable cell unit are commonly connected.

In a preferred embodiment of the device, the voltage across the capacitor is boosted to unselected word lines of the lockable cell portion at a level lower than an erase voltage of a predetermined level.

In a preferred embodiment of the device, the lockable cell passgate portion is provided with an NMOS transistor.

According to still another aspect of the present invention, there is provided a memory device comprising: a block selection circuit for outputting a page selection control signal; A plurality of strings in which a plurality of cell transistors are connected in series between the first select transistor and the second select transistor, each string selected line for each first select transistor and a ground select line for each second select transistor A memory cell array unit connected in common and connected to a plurality of word lines respectively corresponding to the plurality of cell transistors of the strings; A first passgate selection transistor connected to the string selection line and the ground to transfer page selection signals to word lines of the memory cell array unit corresponding to the page selection control signal output from the block selection circuit; A pass gate unit including a second pass gate select transistor connected to a select line and a plurality of transfer transistors respectively corresponding to the word lines; The plurality of lockable cell transistors may be formed of a string connected in series between a first passgate select transistor connected to the string select line and a second passgate select transistor connected to the ground select line. A lockable cell unit having respective word lines connected thereto, the capacitors having predetermined values connected to each word line; A lockable cell passgate including a plurality of transfer transistors corresponding to the word lines to transfer the lockable page selection signals to respective word lines of the lockable cell unit in response to the page selection control signal. Contains wealth.

In a preferred embodiment of the device, the voltage across each capacitor is boosted to each unselected word line of the lockable cell portion at a level lower than the erase voltage.

In a preferred embodiment of this apparatus, the page select control signal output from the block select circuit is simultaneously applied to the pass gate portion and the lockable cell pass gate portion.

In a preferred embodiment of the device, each capacitor is formed in one well region of either a pocket P well region or an N well region of a semiconductor substrate.

According to still another aspect of the present invention, there is provided a memory device comprising: a block selection circuit for outputting a page selection control signal; A plurality of strings in which a plurality of cell transistors are connected in series between the first select transistor and the second select transistor, each string selected line for each first select transistor and a ground select line for each second select transistor A memory cell array unit connected in common and connected to a plurality of word lines respectively corresponding to the plurality of cell transistors of the strings; A first passgate selection transistor connected to the string selection line and the ground to transfer page selection signals to word lines of the memory cell array unit corresponding to the page selection control signal output from the block selection circuit; A pass gate unit including a second pass gate select transistor connected to a select line and a plurality of transfer transistors respectively corresponding to the word lines; The plurality of lockable cell transistors may be formed of a string connected in series between a first passgate select transistor connected to the string select line and a second passgate select transistor connected to the ground select line. A lockable cell unit connected to word lines, the word lines being commonly connected to one word line, and having a capacitor having a predetermined value connected to the word line; And a lockable cell pass gate part provided as a transfer transistor to transfer the lockable page selection signal to the word line of the lockable cell part corresponding thereto in response to the page selection control signal.

In a preferred embodiment of the device, the voltage across each capacitor is boosted to each unselected word line of the lockable cell portion at a level lower than an erase voltage of a predetermined level.

In a preferred embodiment of this apparatus, the page select control signal output from the block select circuit is simultaneously applied to the pass gate portion and the lockable cell pass gate portion.

In a preferred embodiment of the device, each capacitor is formed in one well region of either a pocket P well region or an N well region of a semiconductor substrate.

In a preferred embodiment of the device, the word line is formed in one well region of either the pocket P well region or the N well region of the semiconductor substrate.

Hereinafter, a description will be given with reference to FIGS. 5 to 9 according to the present invention.

5 to 9, the same reference numerals are given to the components having the same functions as the components shown in FIGS. 1 to 4.

First embodiment

According to the nonvolatile semiconductor memory device according to the first exemplary embodiment of the present invention, the semiconductor substrates may be formed on the word lines LWL1 to LWL8 of the lockable cell unit 4 arranged in parallel with the memory cell array unit 3. Boosting means 9 having capacitors Cadd of desired predetermined values were formed on the pocket P-WELL regions 8 to N-WELL regions 7). Thus, the erase stress can be prevented by increasing the voltage boosted on the word lines LWL1 to LWL8 connected to the lockable cell unit 4 corresponding to the unselected block during the unlock operation.

5 is a block diagram illustrating a configuration of a nonvolatile semiconductor memory device according to an exemplary embodiment of the present invention.

In the nonvolatile semiconductor memory device according to the present invention shown in FIG. 5, the block selection circuit 1, the pass gate unit 2, the memory cell array unit 3, the lockable cell unit 4, and the boosting unit 9 are provided. And a lockable cell passgate section 5, and the block selection circuit 1 outputs a page selection control signal PGATE. The memory cell array unit 3 includes a plurality of strings in which a plurality of cell transistors M1n to M8n are connected in series between the first select transistor S1n and the second select transistor G1n. A string select line SSL is connected to each of the first select transistors S1n, and a ground select line GSL is connected to each of the second select transistors G1n in common, and a plurality of cell transistors of each string are connected. A plurality of word lines WL1 to WL8 are respectively connected to M1n to M8n.

The pass gate unit 2 transmits page selection signals S1 to S8 corresponding to the page selection control signal PGATE output from the block selection circuit 1. Transfer to each word line (WL1-WL8) of 3). The passgate unit 2 includes a first passgate select transistor SP1 connected to the string select line SSL, a second passgate select transistor GP1 connected to the ground select line GSL, and the word lines. A plurality of transfer transistors MP1 to MP8 respectively corresponding to WL1 to WL8 are formed. The lockable cell unit 4 includes a plurality of lockers between a first passgate select transistor S1n connected to a string select line SSL and a second passgate select transistor G1n connected to the ground select line GSL. The cell transistors M1n to M8n consist of a string connected in series. In addition, word lines LWL1 to LWL8 corresponding to the plurality of lockable cell transistors M1n to M8n are respectively connected, and the boosting means 9 is configured to select an unselected portion of the lockable cell unit 4. This is to increase the voltage level boosted on the word lines LWL1 to LWL8.

The boosting means 9 may include a plurality of capacitors Cadd connected between the word lines LWL1 to LWL8 of the lockable cell unit 4 and a predetermined well region of the semiconductor substrate 6. have. The voltages across the capacitors Cadd are boosted to the unselected word lines LWL1 to LWL8 of the lockable cell unit 4 at a level lower than that of the erase voltage Vera. The predetermined well region of the semiconductor substrate 6 may be formed in one of the pocket P well region 8 and the N well region 7. The lockable cell passgate unit 5 corresponds to the lockable page selection signals LS1 to LS8 in response to the page selection control signal PGATE, and corresponds to each word line of the lockable cell unit 4 corresponding thereto. LWL1-LWL8). The lockable cell passgate part 5 includes a plurality of transfer transistors MLP1 to MLP8 respectively corresponding to the word lines LWL1 to LWL8.

FIG. 6 is a diagram illustrating an equivalent circuit of a capacitor having a cross section taken along the word line of FIG. 5 based on a word line, and FIG. 7 is an operation timing diagram during an unlock operation according to a first embodiment of the present invention. Is shown. 5 to 7, the unlock operation will be described below.

As illustrated in FIG. 7, when a SUNLOCK signal, which is a flag signal for an unlock operation, transitions to a high level, the semiconductor memory device performs an unlock operation. All of the page select signals S1-S8 for designating a predetermined page of the memory cell array unit 3 in synchronization with the SUNLOCK signal transitioned to the high level are transitioned to the high level. The selected signal among the page selection signals LS1 to LS8 for selecting the page of the lockable cell unit 4 is maintained at a low level, and the page selection signals LS0 to LS8 of the unselected lockable cell are maintained. ) All transition to a high level. At the same time, the string select signal line SSL and the ground select signal line GSL are also transitioned to the high level. Then, as the passgate control signal PGATE of the selected block output from the block selection circuit 1 transitions to a high level, the plurality of NMOS transistors SP1, MP1-MP8, and GP1 of the passgate unit 2 are shifted. The channel is conducting.

Voltages of (Vcc-1Vth) are respectively applied to the word lines WL1-WL8 of the memory cell array unit 3 through the pass gate unit 2. Each word line LWL1 to LWL8 of the lockable cell transistors M1n to M8n selected from among the plurality of lockable cell transistors M1n to M8n of the lockable cell unit 4 has a voltage of 0 volts. It is charged. On the other hand, each word line LWL1-LWL8 of the unselected lockable cell transistors M1n-M8n is charged to a voltage of (Vcc-1Vth). Although not shown in the drawing, when the erase voltage pump circuit operates to pump the erase voltage Vera to about 20 volts or more, the N-WELL region 7 and the pocket P-WELL region 8 shown in FIG. The erase voltage Vera of 20V or more is charged. The plurality of word lines WL1 to WL8 of the memory cell array unit 3 and the plurality of word lines LWL1 to LWL8 corresponding to an unselected block of the lockable cell unit 4 may be formed in the pocket P−. The WELL region 8 is boosted as it is charged with the erase voltage Vera.

At the same time, the plurality of transistors SP1, MP1-MP8, and GP1 of the passgate unit 2 and the unselected plurality of lockable cell transistors MLP1 to MLP8 of the lockable cell passgate unit 5 are provided. Are all shut off. Therefore, the plurality of word lines WL1 to WL8 included in the memory cell array unit 3 and the passgate unit 2 may have Vboost1 = [by the coupling ratio of the equivalent circuit diagram of the capacitor illustrated in FIG. 6. Ca / (Ca + Cp) x (Vera + Vcc-1Vth) voltage is induced. At the same time, the plurality of word lines LW1-LW8 corresponding to the unselected cells of the lockable cell unit 4 and the lockable cell unit 4 are each Vboost3 = [(Cla + Cadd) / (Cla + Cadd + Clp) × (Vera + Vcc-1Vth) is induced. In addition, the plurality of word lines LW1 to LW8 corresponding to the selected lockable cell transistors M1n to M8n of the lockable cell unit 4 are maintained at 0 volts.

In the above operation, the selected lockable cell transistors M1n to M8n of the lockable cell unit 4 typically satisfy a bulk erase condition in the nonvolatile semiconductor memory device. Therefore, all data stored in the selected lockable cell transistors M1n to M8n of the lockable cell unit 4 are erased. In the cell transistors M1n-M8n of the memory cell array unit 3 and the word lines LWL1-LWL8 of the unselectable lockable cell transistors M1n-M8n of the lockable cell unit 4, respectively. The voltage Vboost1 and voltage Vboost3 are derived. The voltage difference between the Vboost1 voltage and the erase voltage Vera in which the Vboost3 voltage is charged in the pocket P-WELL region 8 is applied to the unselectable lockable cell transistors M1n-M8n of the lockable cell unit 4. It is small enough not to satisfy the erase condition. As a result, the cell transistors M1n-M8n of the memory cell array unit 3 and the unselected lockable cell transistors M1n-M8n of the lockable cell unit 4 are not erased, but before the unlock operation. To keep the data.

Second embodiment

In the nonvolatile semiconductor memory device according to another embodiment of the present invention, the minimum unit of lock and unlock is set as a block, and word lines LWL1 to LWL8 connected to the lockable cells M1n to M8n are respectively located in the pocket P-WELL region. (8) to N-WELL regions 7 are connected to one word line LWL0. A capacitor Cadd having a desired value is formed on the word line LWL0 on the pocket P-WELL region 8 to the N-WELL region 7. The lockable cell passgate portion 5 is constituted by one NMOS transistor MLP0 to control operations for locking and unlocking. As a result, in the unlock operation, the voltage induced in the word lines connected to the non-selectable lockable cells may be increased.

8 is a block diagram illustrating a configuration of a nonvolatile semiconductor memory device according to another embodiment of the present invention.

As shown in FIG. 8, the nonvolatile semiconductor memory device according to the second exemplary embodiment of the present invention may include a block selection circuit 1, a pass gate unit 2, a memory cell array unit 3, and a lockable cell unit. (4) and the boosting means (10) and the lockable cell passgate portion (5). Here, since the block selection circuit 1, the pass gate unit 2, and the memory cell array unit 3 are implemented in the same configuration as the first embodiment described above, a detailed description thereof will be omitted. The lockable cell unit 4 includes a plurality of lockables between a first passgate select transistor S1n connected to a string select line SSL and a second passgate select transistor G1n connected to a ground select line GSL. The cell transistors M1n to M8n consist of a string connected in series. A plurality of word lines LWL1 to LWL8 are respectively connected to the plurality of lockable cell transistors M1n to M8n.

The boosting means 10 increases the voltage level boosted on the unselected word lines LWL1 to LWL8 of the lockable cell unit 4 during the unlock operation. The lockable cell pass gate unit 5 is provided with one NMOS transistor MLP0 and transmits the lockable page selection signal LS0 to the sub- suting means 10 in response to a predetermined control signal PGATE. . In this case, the boosting means 10 has a plurality of word lines LWL1 to LWL8 of the lockable cell unit 4 connected to a word line LWL0 formed in a predetermined well region of the semiconductor substrate 6. have. The boosting means 10 is provided with a capacitor Cad connected between the word line LWL0 and a predetermined well region of the semiconductor substrate 1. The predetermined well region of the semiconductor substrate 6 may be formed in any one of the pocket P well region 8 and the N well region 7, and the voltage across the capacitor Cad may be an erase voltage ( It is boosted to the unselected word line LWL0 of the lockable cell unit 4 at a lower level than Vera.

9 is an operation timing diagram when an unlock operation is performed according to another embodiment of the present invention. 8 to 9, the unlock operation of the nonvolatile semiconductor memory device according to the present invention will be described.

As illustrated in FIG. 9, when the SUNLOCK signal, which is a flag signal for the unlock operation, transitions to a high level, the semiconductor memory device performs an unlock operation. All of the page select signals S1-S8 for designating a predetermined page of the memory cell array unit 3 in synchronization with the SUNLOCK signal transitioned to the high level are transitioned to the high level. The page select signal LS0 for selecting the page of the lockable cell unit 4 is maintained at a low level. At the same time, the string select signal line SSL and the ground select signal line GSL are also transitioned to the high level. The pass gate control signal PGATE of the selected block output from the block selection circuit 1 is applied with a high level, so that the channels of the plurality of NMOS transistors SP1, MP1-MP8, and GP1 of the passgate unit 2 are applied. This is conducting.

Voltages of (Vcc-1Vth) are respectively applied to the plurality of word lines WL1-WL8 of the memory cell array unit 3 through the pass gate unit 2. The selected word line LWL0 of the lockable cell unit 4 becomes 0 volt. Subsequently, although not shown in the drawing, when the erase voltage pump circuit operates to raise the erase voltage Vera to a voltage of 20 volts or more, the erase voltage of the N-WELL region 7 and the pocket P-WELL region 8 is about 20 V or more. Voltage Vera is applied. Thus, the erase voltage Vera is charged in the N-WELL region 7 and the pocket P-WELL region 8, respectively. The plurality of word lines WL1-WL8 of the memory cell array unit 3 and the unselected word lines LWL1-LWL8 of the lockable cell unit 4 are formed in the pocket P-WELL region 8. The battery is boosted as it is charged with the erase voltage Vera. At the same time, all of the cell transistors SP1, MP1-MP8, and GP1 of the passgate unit 2 are shut off.

Accordingly, the plurality of word lines WL1 to WL8 included in the memory cell array unit 3 and the passgate unit 2 have Vboost1 = [Ca / (Ca + Cp) × Vera + Vcc-1Vth] voltages. This is induced. At the same time, the selected word lines LWL1 to LWL8 of the lockable cell unit 4 maintain zero volts. In the above operation, the selected lockable cell transistors of the lockable cell unit 4 satisfy a bulk erasing condition in a typical nonvolatile semiconductor device, thereby erasing data stored in the selected cell transistors. The voltage Vboost1 is induced on the word lines WL1 to WL8 connected to the cell transistors M1n to M8n of the memory cell array unit 3. The Vboost1 voltage is sufficiently different from the erase voltage Vera of the pocket P-WELL region 8 so that the erase condition is not satisfied for the cell transistors, thereby reducing the cell transistors of the memory cell array unit 3 ( M1n-M8n) are not erased and retain the data before the unlock operation.

In addition, the word lines WL1 to WL8 of the memory cell array unit 3 of the unselected block are induced with the voltage Vboost4 = [Ca / (Ca + Cp) × Vera] during the unlock operation. The word lines LWL1 to LWL8 of the lockable cell unit 4 of the block are induced with the voltage Vboost3 = [(8 × Cla + Cadd) / (8Cla + Cadd + Clp) × Vera]. The voltage difference between the Vboost3 voltage and the Vboost4 voltage between the erase voltage Vera charged in the pocket P-WELL region 8 is sufficiently small that the erase conditions for the unselected cell transistors M1n-M8n are not satisfied. . Therefore, the cell transistors M1n-M8n of the memory cell array unit 3 and the unselected lockable cell transistors M1n-M8n of the lockable cell unit 4 are not erased and data before the unlock operation is performed. Will be maintained.

As described above, capacitors having desired values are formed in the word lines of the lockable cell unit arranged in parallel with the memory cell array unit on the pocket P-WELL region and the N-WELL region of the semiconductor substrate. In addition, the minimum unit of lock and unlock is determined as a block, and word lines connected to the lockable cells are connected to one word line on the pocket P-WELL region or the N-WELL region. A capacitor having a predetermined predetermined value is formed on the word line on the pocket P-WELL region to the N-WELL region. The lockable cell passgate part is configured by one NMOS transistor to control the operation for locking and unlocking. As a result, an erase voltage may be prevented by increasing a voltage induced in word lines connected to unselected lockable cells during an unlock operation.

Claims (16)

A memory cell array section 3 for storing data; A lockable cell unit (4) having a plurality of lockable cells and a plurality of word lines corresponding thereto, for storing lock and unlock data of the memory cell array unit (3) in units of pages and blocks; And a boosting means (9) for increasing a voltage level boosted on unselected word lines of the lockable cell portion (4). The method of claim 1, The boosting means (9) is a nonvolatile semiconductor memory device provided with a plurality of capacitors (Cadd) respectively connected to the word lines of the lockable cell unit (4). The method of claim 2, The voltage across both of the capacitors (Cadd) is boosted to the unselected word lines of the lockable cell unit (4) to a level lower than the erase voltage (Vera). A plurality of strings of cell transistors M1n to M8n are connected in series between the first select transistor S1n and the second select transistor G1n, and each of the first select transistors S1n includes a string. A selection line SSL and a ground selection line GSL are commonly connected to each of the second selection transistors G1n, respectively, and a plurality of word lines corresponding to the plurality of cell transistors M1n to M8n of each string. Memory cell array sections 3 to which WL1 to WL8 are connected; A plurality of lockable cell transistors M1n to M8n between the first passgate select transistor S1n connected to the string select line SSL and the second passgate select transistor G1n connected to the ground select line GSL. A lockable cell unit (4) having a string connected in series and having word lines LWL1 to LWL8 corresponding to the plurality of lockable cell transistors M1n to M8n, respectively; Boosting means (10) for increasing the voltage level boosted on each of the unselected word lines (LWL1 to LWL8) of the lockable cell unit (4); A nonvolatile semiconductor memory device comprising a lockable cell passgate (5) for transmitting a lockable page selection signal (LS0) to the sub- susting means (10) in response to a predetermined control signal (PGATE). The method of claim 4, wherein The boosting means 10 is a nonvolatile device including a capacitor Cad electrically connected to a predetermined word line LWL0 to which a plurality of word lines LWL1 to LWL8 of the lockable cell unit 4 are commonly connected. Semiconductor memory device. The method of claim 5, The voltage across the capacitor Cad is boosted to the unselected word lines LWL1 to LWL8 of the lockable cell unit 4 at a level lower than that of the erase voltage Vera. The method of claim 4, wherein The lockable cell pass gate part (5) is provided with an NMOS transistor (MLP0). A block selection circuit 1 for outputting a page selection control signal PGAGE; A plurality of strings of cell transistors M1n to M8n are connected in series between the first select transistor S1n and the second select transistor G1n, and each of the first select transistors S1n includes a string. A select line SSL and a ground select line GSL are connected to the second select transistor G1n in common, respectively, and a plurality of words corresponding to the plurality of cell transistors M1n to M8n of the respective strings, respectively. A memory cell array unit 3 to which lines WL1 to WL8 are connected; In response to the page selection control signal PGATE output from the block selection circuit 1, the page selection signals S1 to S8 correspond to word lines WL1 to WL8 of the memory cell array unit 3 corresponding thereto. ), A first passgate select transistor SP1 connected to the string select line SSL, a second passgate select transistor GP1 connected to the ground select line GSL, and the word lines WL1. A passgate portion 2 composed of a plurality of transfer transistors MP1-MP8 respectively corresponding to WL8; A plurality of lockable cell transistors M1n to M8n between the first passgate select transistor S1n connected to the string select line SSL and the second passgate select transistor G1n connected to the ground select line GSL. ) Is formed in a string connected in series, and word lines LWL1 to LWL8 corresponding to the plurality of lockable cell transistors M1n to M8n are connected to each other, and each word line LWL1 to LWL8 is predetermined. A lockable cell unit 4 to which capacitors Cadd having values are respectively connected; In order to transfer the lockable page selection signals LS1 to LS8 to the respective word lines LWL1 to LWL8 of the lockable cell unit 4 corresponding to the page selection control signal PGATE. 10. A nonvolatile semiconductor memory device comprising a lockable cell passgate portion (5) consisting of a plurality of transfer transistors (MLP1-MLP8) corresponding to lines LWL1-LWL8, respectively. The method of claim 8, The voltage across both capacitors Cadd is lower than the erase voltage Vera at a predetermined level and is boosted on each of the unselected word lines LWL1 to LWL8 of the lockable cell unit 4. . The method of claim 8, And a pass select unit (2) and the lockable cell pass gate unit (5) to which the page selection control signal (PGATE) output from the block select circuit (1) is simultaneously applied. The method of claim 8 or 9, And each capacitor (Cadd) is formed in any one of a pocket P well region (8) and an N well region (7) of the semiconductor substrate (6). A block selection circuit 1 for outputting a page selection control signal PGAGE; A plurality of strings of cell transistors M1n to M8n are connected in series between the first select transistor S1n and the second select transistor G1n, and each of the first select transistors S1n includes a string. A select line SSL and a ground select line GSL are connected to the second select transistor G1n in common, respectively, and a plurality of words corresponding to the plurality of cell transistors M1n to M8n of the respective strings, respectively. A memory cell array unit 3 to which lines WL1 to WL8 are connected; In response to the page selection control signal PGATE output from the block selection circuit 1, the page selection signals S1 to S8 are corresponding to each word line WL1 to WL8 of the memory cell array unit 3 corresponding thereto. ), A first passgate select transistor SP1 connected to the string select line SSL, a second passgate select transistor GP1 connected to the ground select line GSL, and the word lines WL1. A passgate portion 2 composed of a plurality of transfer transistors MP1-MP8 respectively corresponding to WL8; A plurality of lockable cell transistors M1n to M8n between the first passgate select transistor S1n connected to the string select line SSL and the second passgate select transistor G1n connected to the ground select line GSL. ) Is a string connected in series, and word lines LWL1 to LWL8 corresponding to the plurality of lockable cell transistors M1n to M8n are connected, but the word lines LWL1 to LWL8 are connected to one another. A lockable cell unit 4 connected in common to a word line LWL0 and having a capacitor Cad having a predetermined value connected to the word line LWL0; In order to transfer the lockable page selection signal LS0 to the word line LWL0 of the lockable cell unit 4 corresponding thereto in response to the page selection control signal PGAGE, a transfer transistor MLP0 is provided. A nonvolatile semiconductor memory device including the lockable cell passgate part 5. The method of claim 12, The voltage across the capacitor Cad is lower than the erase voltage Vera at a predetermined level and is boosted on the unselected word line LWL0 of the lockable cell unit 4. The method of claim 12, And a pass select unit (2) and the lockable cell pass gate unit (5) to which the page selection control signal (PGATE) output from the block select circuit (1) is simultaneously applied. The method of claim 12 or 13, The capacitor (Cadd) is formed in any one of the pocket P well region (8) and N well region (7) of the semiconductor substrate (6). The method of claim 12, And the word line (LWL0) is formed in one of the pocket P well region (8) and the N well region (7) of the semiconductor substrate (6).