KR19980033965A - Clock and Data Recovery Circuit for Optical Communication Receiver - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to clock and data recovery circuits, and more particularly, to clock and data recovery circuits for optical communication receivers that enable clock signal recovery, data determination and conversion of multi-channel parallel data from transmitted data signals.

Such a clock and data recovery circuit for an optical communication receiver of the present invention includes a delay unit for outputting a reference signal to be exactly synchronized with the input data; A PLL circuit for achieving phase synchronization with the output signal of the delay unit; And a data determination and conversion circuit for converting and determining received serial data into parallel data using clock signals of the PLL circuit and outputting data including clock information to synchronize input data and the extracted clock signal. Has its features.

Description

Clock and Data Recovery Circuit for Optical Communication Receiver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to clock and data recovery circuits, and more particularly, to clock and data recovery circuits for optical communication receivers that enable clock signal recovery, data determination and conversion of multi-channel parallel data from transmitted data signals.

In general, most data transmission systems transmit and receive information in the form of modulated or unmodulated digital bits, and transmit only data signals except clock signals to reduce hardware configuration costs.

Therefore, the receiver must include a clock and data recovery circuit which extracts the clock signal used in the transmitter from the transmitted data and synchronizes it with the data bits to accurately determine the data state.

The clock and data recovery circuits have been researched and applied in various fields, such as disk drives, local area networks (LANs), and optical communications. However, Phase Locked Loop (PLL) circuits, which are relatively less affected, are in the spotlight.

In addition, in the conventional PLL structure such as the frequency synthesizer used in the measurement equipment, since the input signal has a periodicity, the output of the phase comparator is continuous, easily synchronized and stabilized.

Hereinafter, a clock and data recovery circuit for a conventional optical communication receiver will be described with reference to the accompanying drawings.

1 is a block diagram showing a conventional clock and data recovery circuit for an optical communication receiver.

A conventional clock and data recovery circuit for an optical communication receiver includes a photo receiver 11, a 1/2 bit delay unit 12a and an exclusive oar as shown in FIG. A non-return to zero (NRZ) converter 12 composed of a gate 12b to double the input data rate, a phase detector 13a, a low pass filter (LPF) 13b, and voltage control A PLL (Phase Locked Loop) circuit 13 configured to extract a periodic clock signal from the aperiodic input data transmitted by the oscillator (VCO: Voltage Controlled Oscillator) 13c, and extracted from the PLL circuit 13 A data divider circuit 14 which returns to serial data by a clock signal and a frequency divider for outputting the serial data recovered by the data detector circuit 14 as parallel data of eight channels. Frequency Divider (15) and Demultiplexer (1 6) is configured to include.

Referring to the operation of the conventional clock and data recovery circuit for the optical communication receiver configured as described above are as follows.

First, the serial data transferred through the optical cable is converted and amplified to a voltage level capable of sufficiently driving the NRZ converter 12 and the data determination circuit 14 by the optical receiver 11. do.

Subsequently, in order to extract the clock signal having the same frequency as the input data rate by receiving the double input data signal transmitted from the optical receiver 11, the NRZ converter 12, i.e., a half bit delay of a clock, is delayed. The delayed output signal is applied to the PLL circuit 13 through an Exclusive-OR-Gate 12b so that a clock signal having the same frequency as the input data rate is applied. Extract.

At this time, an output signal which is a function of the phase difference between the two signals is generated in the phase detector 13a which receives the output signal extracted from the NRZ converter 12 and the output signal of the voltage controlled oscillator (VCO) 13c.

Subsequently, the output signal generated in the phase detector (PD) 13a is removed from the low pass filter (LPF: Low Pass Filter) 13b so that the high frequency component is removed and the feedback loop (VCO) 13c of the feedback loop ( The feedback loop) locks the clock component extracted from the NRZ converter 12 and the output of the voltage controlled oscillator (VCO) 130c.

The output signal of the voltage controlled oscillator 13c is applied to the data determination circuit 14 together with the input signal of the optical receiver 11 to synchronize the extracted clock signal with the data to transmit the data. Restore to serial data correctly.

Subsequently, the serial data recovered by the data determination circuit 14 is passed through the demultiplexer 16 and the frequency divider 15 to the data link control block 17 in parallel with eight channels. Print the data.

However, as described above, the conventional clock and data recovery circuit for an optical receiver has the following problems.

First, in the optical communication receiver, an aperiodic signal in which the states of '1' and '0' are changed irregularly is received.

Second, the time constant of the low pass filter must be large because the input data and the clock signal are compared and synchronized.

In other words, it takes a long time to be locked.

Third, the configuration is complicated because it must include a demultiplexer and a frequency divider for conversion to multi-channel parallel data.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a clock and data recovery circuit for an optical communication receiver which simultaneously realizes conversion and determination of input data transmitted through an optical receiver to parallel data of multiple channels. There is a purpose.

1 is a block diagram showing a clock and data recovery circuit for a conventional optical communication receiver;

2 is a block diagram showing a clock and data recovery circuit for the optical communication receiver of the present invention.

3 is an equivalent circuit diagram of a charge filter PLL in a clock and data recovery circuit for an optical communication receiver of the present invention.

4 is a circuit diagram illustrating a phase and frequency detector in the charge filter PLL equivalent circuit diagram of FIG. 3.

5A through 5D are waveform diagrams illustrating verification results of the phase and frequency detectors of FIG. 4.

6 illustrates a charge pump circuit and a loop filter in the charge filter PLL equivalent circuit of FIG. 3.

7A and 7B are circuit diagrams showing a circuit showing a voltage controlled ring oscillator and a verification model thereof in a clock and data recovery circuit for an optical communication receiver according to the present invention.

8 shows a verification model of a VCO used in a voltage controlled ring oscillator.

9 is a circuit diagram showing a data determination and change circuit in a clock and data recovery circuit for an optical communication receiver of the present invention.

FIG. 10 is a waveform diagram illustrating a result of verifying a data determination and conversion circuit of FIG. 9. FIG.

11 is a waveform diagram showing a verification result of the clock and data recovery circuit for the optical communication receiver of the present invention;

* Description of the symbols for the main parts of the drawings *

21: Optical receiver 22: 1/2 bit delay part

23: charge pump PLL circuit 24: data determination and conversion circuit

25: frequency oscillator 26: charge pump circuit

27 loop filter 28 voltage control ring oscillator

Clock and data recovery circuit for the optical communication receiver of the present invention for achieving the above object is a delay unit for outputting a reference signal to be exactly synchronized with the input data; A PLL circuit for achieving phase synchronization with the output signal of the delay unit; And a data determination and conversion circuit for converting and determining received serial data into parallel data using clock signals of the PLL circuit and outputting data including clock information to synchronize input data and the extracted clock signal. Has its features.

Hereinafter, a clock and data recovery circuit for an optical communication receiver of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing a clock and data recovery circuit for the optical communication receiver of the present invention.

The clock and data recovery circuit for the optical communication receiver of the present invention includes an optical receiver 21, a 1/2 bit delay unit 22, a charge pump PLL circuit 23, data determination and conversion as shown in FIG. Data Decision and Conversion Circuit (24).

In addition, the charge pump phase locked loop (PLL) circuit 23 includes a phase frequency detector (PFD) 25, a charge pump circuit 26, resistance and capacitance in series. It consists of a connected loop filter (27), and a voltage controlled ring oscillator (VCO) (28). By adjusting the gain for each block applied, designers can achieve the desired performance.

Referring to the operation of the clock and data recovery circuit for the optical communication receiver of the present invention configured as described above are as follows.

First, serial data transmitted through the optical cable is converted into a voltage level capable of sufficiently driving the 1 / 2-bit delay unit 22 and the data determination and conversion circuit 23 by the optical receiver 21. And amplify.

The 622.08 Mbps NRZ data input from the optical receiver 21 is generated by the 1/2 bit delay unit 22 by a delay of 1/2 bit, that is, 0.8 nsec.

The output signal delayed by the 1/2 bit delay unit 22 is a signal generated by a clock of the transmitter to delay the input data transmitted as it is and is a data signal including clock information of the transmitter.

Subsequently, a charge pump PLL circuit 23 including a voltage controlled ring oscillator 28 is used to extract a 77.76 Hz clock signal, which is 1/8 frequency of the input data rate.

The clock signals of eight channels having the same frequency and phase delayed by i / 8 (i = 1, 2, ..., 8) of each period are simultaneously applied to the data determination and conversion circuit 24.

Then, the data determination and conversion circuit 24 independently recovers eight bits of data using eight clock signals C ₁ -C ₈ applied thereto, and simultaneously performs eight channels of parallel data (DA ₁ −). DA ₈ ) to output it.

Hereinafter, the configuration and operation of each block of the clock and data recovery circuit for the optical communication receiver of the present invention will be described in detail with reference to the accompanying drawings.

3 is an equivalent circuit diagram showing a charge pump PLL in a clock and data recovery circuit for an optical communication receiver of the present invention.

As shown in FIG. 3, the charge pump PLL circuit 23 includes an output signal Phase-IN delayed by the 1/2 bit delay unit 22 and an output signal Phase applied by the data determination and conversion circuit 24. -OUT) detects the phase difference or the frequency difference by using the falling transition of the two signals in the phase and frequency detector (PFD) 25.

FIG. 4 is a circuit diagram illustrating a phase and frequency detector in the residual pump PLL circuit of FIG. 3.

The sequential phase frequency detector is composed of a combination of a NAND gate and an inverter as shown in FIG.

First, the phase and frequency detector has a frequency detector function added as compared to a phase detector using a multiplier, and detects a phase difference or a frequency difference by using a falling transition of two input signals.

In addition, the detected phase difference or frequency difference is output in the form of an UP / DOWN signal and applied to the charge pump circuit. When there is no phase difference or frequency difference between the two signals, any UP signal or down signal is applied. It does not generate a signal.

Therefore, the phase and frequency detector has a characteristic of outputting three forms with two output stages.

5A-5D are waveform diagrams showing the verification results of the phase and frequency detectors.

5A and 5B illustrate a case where two input signals have a phase difference, and as shown in FIG. 5A, an UP signal corresponding to a phase difference generated when the VCO signal is delayed in phase with respect to the REF signal is output.

5B illustrates the opposite case and outputs a DOWN signal corresponding to the phase difference.

5C and 5D show a case where two input signals have a frequency difference, and as shown in FIG. 5C, when the VCO signal has a lower frequency than the REF signal, an UP signal corresponding to a frequency difference generated is output. In the opposite case, a DOWN signal is output as shown in FIG. 5D.

FIG. 6 is a diagram illustrating a charge pump circuit and a loop filter in an equivalent circuit diagram of the charge pump PLL of FIG. 3.

First, the charge pump circuit is composed of two current sources G1 and G2 and two switches SW1 and SW2 as shown in FIG. 6, and the loop filter 27 includes a resistor RL and a capacitance CL. Are connected in series.

The two switches SW1 and SW2 are alternately controlled by an UP / DOWN signal generated by the phase and frequency detectors.

For example, when an UP signal is generated due to a phase difference or a frequency difference between two input signals, the switch SW1 is turned on, so that the pump current Ip of the current source G1 is changed by the loop filter 27. The capacitor CL is charged via the resistor RL.

On the contrary, when a DOWN signal is generated due to a phase difference or a frequency difference between two input signals, the switch SW2 is turned on so that the charge charged in the capacitor by the pump current Ip of the current source G2 is resistance. Discharge through.

Here, the sum of the voltage across the capacitor and the voltage across the resistor, which is changed by the charged and discharged charge, is applied to the control voltage of the voltage control ring oscillator to change the frequency and phase of the clock signal.

In the charge pump PLL circuit, the output of the charge control ring oscillator can be changed only when the switch of the charge pump circuit operates to charge and discharge the current, and can be interpreted as a linear circuit.

The output of the loop filter 27, which is the instantaneous control voltage every cycle in which the switch operates,

V _CONTROL = V _C (0) + ΔV _R

V _C (0) represents the initial voltage of the capacitor, ΔV _R represents the jump voltage by the pump current (Ip) and the resistor (RL).

Thus, the control voltage has a rectangular ripple shape in every operating cycle, and if the ripple is not appropriate, the voltage control ring oscillator may not be synchronized with the reference signal in the normal state, so the width and magnitude of the ripple are the amount of current in the constant current source. It is appropriately adjusted by the value of Ip and the resistance RL and the capacitor CL of the loop filter 27.

7A and 7B are circuit diagrams illustrating a voltage control ring oscillator circuit and a verification model thereof in a clock and data recovery circuit for an optical communication receiver of the present invention.

In general, the ring oscillator can vary the operating frequency of the oscillator by using the delay time of the inverter and the number of inverters, and the single-ended ring oscillator and the dual-output ring oscillator can be changed. Divided by (Double Ended Ring Oscillator).

A single output ring oscillator consists of an odd number of inverters to produce one output for each stage, and a dual output ring oscillator consists of an even number of inverters and outputs two waveforms with phase differences of 180 ° to each stage. do.

The voltage controlled ring oscillator used in the proposed charge pump PLL is composed of eight dual output inverters as shown in FIG. 7A and designed to have an oscillation frequency of 77.76MHz when the control voltage is 2.5V.

In the proposed voltage controlled ring oscillator, all sixteen nodes can be obtained, and each node has the same frequency of 77.76MHz and each has a phase delay of i / 16 (i = 1, 2,…, 16) of the period.

As shown in FIG. 7A, the output signals C ₁ -C ₈ , which are phase-delayed by i / 8 (i = 1, 2,..., 8) of periods, are applied as clock signals of the data conversion and determination circuits at the eight nodes. .

The verification model is composed of a VCO block and seven voltage controlled delay blocks as shown in FIG. 7B.

The VCO block outputs a 77.76MHz square wave having a sensitivity of 31MHz / V centered on a control voltage of 2.5V and delivers the square wave to a next voltage control delay block.

In the voltage controlled delay block, the output square wave has a delay time in inverse proportion to the control voltage and sequentially delays the same to obtain the same effect as the operation state of the actual ring oscillator.

8 illustrates a verification model of a VCO used in a voltage controlled ring oscillator.

As shown in FIG. 8, a voltage controlled inverter structure using a square wave converter, two voltage controlled current sources GT, GD, and four switches SW-1, SW-2, SW1, and SW2 is used.

V (CTRL) in the voltage controlled inverter represents the control voltage of the VCO, and Vc is the control voltage of the switch.

SW-1 and SW-2 are the same as the operating states of SW1 and SW2, respectively.

Referring to the operation of the VCO configured as described above are as follows.

SW1 and SW2 of the voltage control converter stage are turned on / off by the voltage of the SQU node of the square wave converter stage, so that the currents of the current sources GT and GD charge and charge the capacitor CL.

The triangular wave oscillates continuously at the TRI node due to the change in the amount of current charged and charged in the capacitor CL, and the generated triangular wave is converted into a square wave by a table (TABLE) statement which is an analog operation model of E7 at the square wave converter stage. Convert.

In addition, the oscillation frequency of the desired square wave is obtained by adjusting the current amount and the capacitor value of the voltage controlled current sources GT and GD.

9 is a circuit diagram showing a data determination and conversion circuit in the clock / data recovery circuit of the present invention.

As shown in FIG. 9, the data determination and conversion circuit is a circuit for converting and determining received serial data into parallel data using clock signals of a voltage controlled oscillator, and includes data including clock information such that the input data and the extracted clock signal are synchronized. Outputs

The data determination and conversion circuit is composed of eight D flip-flops and three tri-state buffers. Two inverters are connected in series at the final output stage to eliminate noise.

In addition, when there is no input data, the undefined section uses a pull-down resistor R (Pulldown) to make the low state.

The operation of the data determination and conversion circuit configured as described above is as follows.

First, the signals applied to the data determination and conversion circuit are the output signals C ₁ -C ₈ of the voltage controlled oscillator VCO, the control signals A ₁ -A ₈ of the three-phase buffer, and the input signal DATAIN.

For example, 622.08 Mbps Non Return to Zero (NRZ) data is recovered by the corresponding clock signal in bit units by the output signals (C ₁ -C ₈ ) of the VCO, and the eight parallel data signals (DA _1- ). DA ₈ ).

The recovered parallel data signal DA ₁ -DA ₈ uses a three-phase buffer to output the combined serial data signal DATAOUT, and the control signal A ₁ -A ₈ of the three-phase buffer for controlling the same. Will occur).

The control signal is AOi

AOi = COi (i = 1, 2, 3,…, 8)

The inverted signal of the clock signal adjacent to the clock signal COi ) Is easily implemented by an AND operation.

FIG. 10 is a waveform diagram illustrating a result of verifying a data determination and conversion circuit of FIG. 9.

As shown in FIG. 10, when the input signals DATAIN and the clock signals C ₁ -C ₈ are input, the control signals A ₁ -A ₈ of the three-phase buffer, the parallel data DA ₁ -DA ₈ , And shows the data (DATAOUT) combining the parallel data in order.

Arrows 1, 2, and 3 show the process of determining data by C ₃ , which is the output of the third tap among the eight taps of the clock generator.

The rising transition of the third clock signal C ₃ is applied to the input signal DATAIN as shown by arrow 1, and the third channel data DA ₃ is sequentially determined as shown by arrow 2.

In addition, the control signal A ₃ of the three-phase buffer sequentially recovers only the bits corresponding to the third channel data signal DA ₃ as shown by the arrow 3.

In this manner, the serial data signal DATAOUT including the clock information extracted by the three-phase buffer control signals A ₁ -A ₈ is output.

FIG. 11 is a waveform diagram illustrating a verification result of simulating a clock / data recovery circuit for an optical communication receiver of the present invention with a Design Center (Version 6.1). FIG.

As shown in FIG. 11, the clock signal extraction process according to the presence or absence of the input data and the conversion and recovery process from the input data to the multi-channel parallel data are shown well.

The extracted clock signals (C ₁ -C ₈ ) and the final output data signals (DA ₁ -DA ₈ ) of this circuit are shown, and the clock signals are applied to the input data and restored to parallel data. It is represented by.

Initially, the extracted clock signal C ₁ was advanced by pd compared to the reference clock signal X-TAL1 of 77.76 MHz, but is almost completely synchronized at the dotted line marked with lock.

The extracted clock signals C ₁ -C ₈ after the LOCK dotted line are output while maintaining a phase delay of i / 8 (i = 1, 2, ..., 8) of each period as in the dotted line.

At this time, the output clock signals are completely synchronized with the input data during the preamble time, and accurately convert and restore the input data DTATIN into parallel data signals DA ₁ -DA ₈ .

For example, as shown in FIG. 11, the rising transition of the sixth clock signal C ₆ is applied to the input data DARAIN as shown by arrow 1, and the sixth channel data signal DA ₆ is sequentially determined as shown by arrow 2. Indicates.

Even when no data is input from the verification result of FIG. 11, the clock signals of the clock generator maintain the output normally. When 622 Mbps serial data is input, the clock signals C ₁ -C ₈ are exactly synchronized with each other. It can be seen that the parallel data signals DA _{1 to} DA ₈ of the channel are converted and recovered.

As described above, the clock and data recovery circuit for the optical communication receiver of the present invention has the following effects.

First, clock recovery, data determination, and conversion to multichannel parallel data are simultaneously performed. Second, the oscillation frequency can be reduced by setting the output frequency of the voltage controlled oscillator for recovering the input data to 1/8 of the input data rate.

Third, by comparing the input data and the data recovered by the clock, it is possible to compare the clock signal of the transmitter and the clock signal of the receiver.

Fourth, the loop filter can reduce the locking time by reducing the time constant by achieving phase synchronization by comparing the input data with the recovered data rather than comparing the periodic data with the periodic clock signal. have.

Fifth, the configuration is simple compared to the conventional.

Claims (11)

A delay unit for outputting a reference signal to be exactly synchronized with the input data; A PLL circuit for achieving phase synchronization with the output signal of the delay unit; And And a data determination and conversion circuit for converting and determining received serial data into parallel data using clock signals of the PLL circuit and outputting data including clock information to synchronize input data and the extracted clock signal. A clock and data recovery circuit for an optical communication receiver. 2. The clock and data recovery circuit of claim 1, wherein the delay unit delays the input signal by 1/2 of phase only, that is, 0.8 nsec. 2. The circuit of claim 1, wherein the PLL circuit is A phase and frequency detector for outputting an up / down signal by detecting a phase difference or a frequency difference using a falling transition of two input signals; A charge pump circuit which alternately controls two switches by up / down signals of the phase and frequency detectors; A loop filter for outputting an instantaneous control voltage every cycle; A clock and data recovery circuit for an optical communication receiver, comprising a voltage controlled ring oscillator for varying an operating frequency of the oscillator. 4. The clock and data recovery circuit of claim 3, wherein the phase and frequency detector outputs three types with two output stages. 4. The clock and data recovery circuit of claim 3, wherein the charge pump circuit is composed of two current sources and two switches. 4. The clock and data recovery circuit of claim 3, wherein the loop filter is configured by connecting a resistor and a capacitance in series. 4. The clock and data recovery circuit of claim 3, wherein the voltage controlled ring oscillator is a dual output ring oscillator composed of an even number of inverters. 4. The clock and data recovery circuit of claim 3, wherein the voltage control ring oscillator outputs two waveforms each having a phase difference of 180 degrees for each stage. 4. The clock and data recovery circuit of claim 3, wherein the voltage control ring oscillator includes eight dual output inverters, and the oscillation frequency is designed to be 77.76 MHz when the control voltage is 2.5V. 4. The voltage controlled ring oscillator all obtains sixteen nodes, each node having the same frequency of 77.76 MHz, each i / 16 (i = 1, 2, ..., 16) of the period. Clock and data recovery circuit for an optical communication receiver characterized by a phase delay. 2. The clock and data of claim 1, wherein the data determination and conversion circuit includes eight D flip flops and eight three-phase buffers, and two inverters are connected in series to remove noise from a final output stage. Recovery circuit. 12. The clock and data recovery circuit of claim 11, wherein the data determination and conversion circuit uses a pull-down resistor to set an undefined section to a low state when there is no input data.